JP2000267992A - Multi-bus controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform data transfer at a state that a priority order is surely secured irrespective of whether requests are 'data transfer between buses' or 'data transfer in a bus' by efficiently performing data transfer of plural requests. SOLUTION: The data transfer executing part 33 is made to execute data transfer of all the requests in parallel when transfer destination buses of plural requests are not conflicted and a processing is held in a transfer destination bus judging part 30 when the transfer destination buses are conflicted by a confliction of transfer destination bus judging part 20 in a multi-bus mediating circuit 10 of this multi-bus controller. The priority orders of priority order parameters 38ai for request about plural requests are compared, an instruction is given to a cancellation processing part 34 to return cancellation to a bus mediating circuit to make a low-ordered request and an instruction for execution is given to a data transfer executing part 33 to make it execute data transfer of a high-ordered request by a priority order of request judging part 31 in the transfer destination bus judging part 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-bus computer system having a multi-bus arbitration function for efficiently executing "data transfer between buses" or "data transfer within a bus" in a computer system having a multi-bus configuration. The present invention relates to a control device. Note that, in the following description of the present specification, as an expression technique for clearly distinguishing the term “inter-bus data transfer” from the term “in-bus data transfer”,
The brackets are attached to each of them, and they are described as “data transfer between buses” and “data transfer within a bus”. Such a notation is not used in the description of the claims, and therefore, it is necessary to read the description carefully.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing an electric configuration of a multi-bus control device in a multi-bus configuration computer according to the prior art. In FIG. 13, 71
Is a multi-bus controller, B1 to B4 are first to fourth independently operating buses, and C1 to C4 are first to fourth bus arbitration circuits associated with each bus. C2 is a bus arbitration main circuit.
A microprocessor μPi is connected to each bus. When there is a request for “data transfer in the bus” from the microprocessor, the “data transfer in the bus” is transmitted via a unique bus arbitration circuit attached to the bus.
Is to be executed. When a request for "data transfer between buses" is made from a microprocessor connected to a certain bus to a microprocessor connected to another bus, the request is sent from the bus arbitration circuit to the bus arbitration main circuit C2. It is to be transmitted. As a configuration therefor, each bus arbitration circuit C1, C
3 and C4 and the bus arbitration main circuit C2 are connected via request lines 81, 83 and 84. All buses B1 to B4 are connected to a bus control circuit 90, and a control signal line 91 is connected from the bus arbitration main circuit C2 to the bus control circuit 90. When there is a request for "data transfer between buses", which is a data transfer from one bus to another bus, the bus arbitration main circuit C2 performs centralized arbitration processing, and in response to a command given from the control signal line 91 to the bus control circuit 90. , "Data transfer between buses" is given the highest priority.

[0003]

In the above-mentioned conventional configuration, when the "data transfer between buses" request is generated, the bus arbitration main circuit C2 and the bus control circuit 90 are required.
Priority is given to "data transfer between buses"
All buses operate in a centralized arbitration process. Therefore, when a "data transfer between buses" request is issued, all buses are occupied only by the "data transfer between buses" request, and other bus data transfer is stopped, so that efficient data transfer cannot be performed. There was a problem. For example, when a “data transfer within bus” request and a “data transfer between buses” request occur at the same time, even though the transfer destination bus does not collide,
The “data transfer between buses” request is prioritized, and the “data transfer within bus” request is stopped without being executed. Also, when two “inter-bus data transfer” requests occur at the same time, even if the transfer destination bus does not collide, one of them takes precedence and the other is stopped without being executed. Therefore, efficient data transfer cannot be performed.

Further, there is a problem that even in the case of a data transfer request having a high priority, the transfer order may be postponed in some cases.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to enable efficient data transfer when a plurality of data transfer requests occur simultaneously. Another object of the present invention is to make it possible to transfer data in a state in which the priorities are reliably secured as long as the necessary priorities are given in advance. This point is the same in “bus broadcast data transfer” in which a plurality of “bus-to-bus data transfers” are performed simultaneously.

[0006]

SUMMARY OF THE INVENTION A multi-bus control device according to the present invention has a function of executing a plurality of requests concurrently when a plurality of requests occur at the same time and the respective destination buses do not collide. It has a multi-bus arbitration circuit. Since the data transfer of a plurality of requests is executed in parallel on condition that the transfer destination bus does not collide, efficient data transfer becomes possible.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The multi-bus control device according to claim 1 of the present invention has the following configuration. A multi-bus arbitration circuit is provided for receiving a data transfer request from each of a plurality of bus arbitration circuits attached to each bus having a multi-bus configuration. This multi-bus arbitration circuit is configured to have a function of executing each request in parallel when a plurality of requests are made at the same time and each transfer destination bus does not collide.
As long as the transfer destination bus does not collide, data transfer of a plurality of requests is performed in parallel, so that data transfer can be performed efficiently.

According to a second aspect of the present invention, there is provided a multi-bus control device according to the first aspect, wherein the simultaneous requests are "an inter-bus data transfer" request and an "in-bus data transfer" request in which transfer destination buses are different. In some cases, these "inter-bus data transfer" requests and "intra-bus data transfer" requests are executed in parallel. As long as the transfer destination bus does not collide, both "inter-bus data transfer" and "intra-bus data transfer" can be executed efficiently regardless of the priority.

According to a third aspect of the present invention, there is provided a multi-bus control apparatus according to the first aspect, wherein the simultaneous requests are a plurality of "inter-bus data transfer" requests having different transfer destination buses. A plurality of "data transfer between buses" requests are executed in parallel. As long as the transfer destination bus does not collide, a plurality of "inter-bus data transfer" can be efficiently executed together regardless of the priority.

The multi-bus control device according to claim 4 of the present invention has the following configuration. A multi-bus arbitration circuit is provided for receiving a data transfer request from each of a plurality of bus arbitration circuits attached to each bus having a multi-bus configuration. This multi-bus arbitration circuit executes each request in parallel when a plurality of requests occur at the same time when the transfer destination buses do not collide, and executes the request for each request when the transfer destination buses conflict. It has a function of comparing the priorities of the priority parameters, returning a cancel to the bus arbitration circuit that made the low-order request, and performing data transfer of the high-order request. If priorities are set in advance for each request, regardless of whether multiple simultaneous requests are "bus-to-bus data transfer" or "bus-in-bus data transfer", the transfer destination bus of the multiple requests will collide In such a case, data transfer can be performed in a state where the priorities are securely ensured.

The multi-bus control device according to claim 5 of the present invention has the following configuration. A multi-bus arbitration circuit is provided for receiving a data transfer request from each of a plurality of bus arbitration circuits attached to each bus having a multi-bus configuration. This multi-bus arbitration circuit executes each request in parallel when a plurality of requests occur at the same time when the transfer destination buses do not collide, and executes the request for each request when the transfer destination buses conflict. The priority of the priority parameter is compared, a cancel is returned to the bus arbitration circuit that made the lower priority request, the data transfer of the higher priority request is performed, and when the requests have the same priority, the transfer source bus priority for each request is given. It has a function of comparing the priorities of the rank parameters, returning a cancel to the bus arbitration circuit that made the lower-order request, and executing data transfer of the higher-order request. By prioritizing each request in advance, and prioritizing the transfer source bus, whether multiple simultaneous requests are “bus-to-bus data transfer” or “bus-in-bus data transfer” is determined. Instead, when the transfer destination buses of the plurality of requests collide, data transfer can be performed in a state where the priorities are reliably ensured.

According to a sixth aspect of the present invention, there is provided a multi-bus arbitration circuit according to the fourth aspect, wherein at least one of the plurality of requests is a "bus broadcast data transfer" request. When at least one of the transfer destination buses of the plurality of requests collides, the priority of the request priority parameter for each request is compared, and a cancel is returned to the bus arbitration circuit that made the lower-order request, and Is configured to perform data transfer of the request. By assigning priorities to requests in advance, even if multiple simultaneous requests include “bus broadcast data transfer”, which is a composite of “data transfer between buses”, the transfer destination of the multiple requests When even one of the buses collides, data transfer can be performed in a state where the priority order is reliably secured.

According to a seventh aspect of the present invention, there is provided a multi-bus arbitration circuit according to the fifth aspect, wherein at least one of the plurality of requests is a "bus broadcast data transfer" request. When at least one of the transfer destination buses of the plurality of requests collides, the priority of the request priority parameter for each request is compared, and a cancel is returned to the bus arbitration circuit that made the lower-order request, and When the requests are tied, the priority of the transfer source bus priority parameter for each request is compared, and a cancel is returned to the bus arbitration circuit that made the low-order request, and Perform a data transfer of the request It is configured. If priorities are assigned to each request in advance, and priorities are also assigned to transfer source buses, when multiple simultaneous requests include "bus broadcast data transfer" which is a composite of "inter-bus data transfer" However, when even one of the transfer destination buses of the plurality of requests collides, data transfer can be performed in a state where the priorities are securely secured.

Hereinafter, specific embodiments of a multi-bus control device in a multi-bus computer according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an electrical configuration of the multi-bus control device according to the embodiment. The multi-bus control device 1 in this embodiment has a four-bus configuration with four buses. As shown in FIG. 1, the first to fourth buses B1 to B4 connected to the microprocessor μPi are configured to perform bus operations independent of each other. The operation timing of each bus is synchronized. The multi-bus control device 1
To the fourth buses B1 to B4.
To four bus arbitration circuits A1 to A4 and one multi-bus arbitration circuit 10. First bus arbitration circuit A
1 is connected to the first bus B1 via a connection line 41, and is connected to the multi-bus arbitration circuit 10 by a request line 51 and a cancel line 61. Similarly, the second bus arbitration circuit A2 is connected to the connection line 42
, And to the multi-bus arbitration circuit 10 via a request line 52 and a cancel line 62. The third bus arbitration circuit A3 is connected to the third bus B3 via the connection line 43, and is connected to the multi-bus arbitration circuit 10 by the request line 53 and the cancel line 63. The fourth bus arbitration circuit A4 is connected to the fourth bus B4 via the connection line 44, and the multi-bus arbitration circuit 1
0 is connected by a request line 54 and a cancel line 64.

The multi-bus arbitration circuit 10 has therein a transfer destination bus collision judgment unit 20 and a transfer destination bus judgment unit 30. The transfer destination bus determination unit 30 includes a request priority determination unit 31, a transfer source bus priority determination unit 32, a data transfer execution unit 33, and a cancel processing unit 34 therein.

The first bus arbitration circuit A1 has a first bus B
1 and is configured to issue a request to the multi-bus arbitration circuit 10 via the request line 51 when an inter-bus data transfer request for another bus from the microprocessor μP ₁₁ via the connection line 41 is received. I have. Similarly, the second bus arbitration circuit A2
A request is issued to the multi-bus arbitration circuit 10 via the request line 52 when an inter-bus data transfer request for another bus from the microprocessor μP ₂₁ via the second bus B2 and the connection line 42 is received. Is configured. Third bus arbitration circuit A3
The fourth bus arbitration circuit A4 has the same configuration.

When issuing a data transfer request, the microprocessor μPi issues a request priority parameter 38a shown in FIG. 2A and a transfer source bus priority parameter 38b shown in FIG. I do.

FIG. 2A shows the basic type of the request priority parameter 38a. When the transfer source bus number is "0", it means a request from the first bus B1 having the bus number # 0, and when it is "1", the second bus B2 having the bus number # 1. Means a request from the third bus B3 having the bus number # 2 when it is "2", and a fourth bus B4 having the bus number # 3 when it is "3". Means request from. Regarding the transfer destination bus number, when the bus number # 0 is “1”, it means data transfer to the first bus B1, and when the bus number # 1 is “1”, data transfer to the second bus B2. When the bus number # 2 is "1", it means data transfer to the third bus B3, and when the bus number # 3 is "1", it means data transfer to the fourth bus B4. I do. Regarding the request priority, when this parameter is “00”, it means request priority 1 having the highest priority, when it is “01”, it means request priority 2, and when it is “10”, it is. Request priority 3 means "11" means request priority 4 with the lowest priority.

FIG. 2B shows a basic type of the transfer source bus priority parameter 38b. Regarding the priority, when it is “1”, it means the priority 1 with the highest priority,
"2" means priority order 2, "3" means priority order 3, and "4" means priority order 4 with the lowest priority.

The destination bus collision determining unit 20 in the multi-bus arbitration circuit 10 determines whether or not each of the destination buses collides when there are a plurality of requests.
When there is no collision, the data transfer execution unit 33 is caused to execute data transfer of all requests in parallel, and when there is a collision, the process is deposited in the transfer destination bus determination unit 30.

In the transfer destination bus determining unit 30, first, the request priority determining unit 31 operates. The request priority determining unit 31 determines the request priority parameters 38ai for a plurality of requests that collide with the transfer destination bus.
In order to return the cancellation to the bus arbitration circuit which has made the lower priority request.
At the same time, an instruction is given to the data transfer execution unit 33 to execute the data transfer of the high-order request.

The source bus priority determining unit 32 compares the priority of the source bus priority parameter 38bi with respect to a plurality of requests having the same request priority, and cancels the request with the bus arbitration circuit that has made the lower priority request. , And an instruction to the data transfer execution unit 33 to execute the data transfer of the higher-order request. The cancel processing unit 34 is connected to each of the cancel lines 61 to 64, and returns a cancel signal to a necessary bus arbitration circuit according to an instruction from the request priority determination unit 31 or the transfer source bus priority determination unit 32. The data transfer execution unit 33 includes the transfer destination bus collision determination unit 20, the request priority determination unit 31, and the transfer source bus priority determination unit 3.
2 to execute data transfer for one or more requests.

Next, the operation of the multi-bus control device 1 configured as described above will be described.

[Execution Case 1] Execution case 1 is a case where only one "data transfer between buses" request occurs. Request priority parameter 38 of FIG.
As shown in a, the first bus B1 whose transfer source is the bus number # 0 to the fourth bus B4 whose transfer destination is the bus number # 3
Is described as an execution case 1. Since the data transfer is performed between buses having different bus numbers, this is "inter-bus data transfer". In execution case 1, there is only one request for data transfer, and no other requests exist.

The request of "data transfer between buses" is
The first bus arbitration circuit A1 received via the bus B1 and the connection line 41 determines the occurrence of the "data transfer between buses" request, and sets the request line 51 to execute the "data transfer between buses". A request is issued to the multi-bus arbitration circuit 10 via the interface. The first
The multi-bus arbitration circuit 10 that has received the request from the bus arbitration circuit A1 of the
At 0, the monitor confirms that there is no request from another bus arbitration circuit, and confirms the bus number # 3 of "1" for the transfer destination of the request priority parameter 38a, and the first bus It is determined that "inter-bus data transfer" from B1 to fourth bus B4 is executable. In this case, the request priority is “0”.
Request priority 1 which is 0 "and has the highest priority
However, since there is no other request, there is no need to determine the request priority. Then, the transfer destination bus collision determination unit 20 instructs the data transfer execution unit 33 to perform “inter-bus data transfer” for the request.

In the case of execution case 1, as a result of the above, the cancel processing unit 34 does not return a cancel signal to the first bus arbitration circuit A1. The data transfer execution unit 33 transmits the fourth bus B1 (bus number # 0) to the fourth bus B1.
"Data transfer between buses" to bus B4 (bus number # 3)
Execute

[Execution Case 2] Execution case 2 is a case where an "inter-bus data transfer" request and an "intra-bus data transfer" request that do not cause a collision occur simultaneously. As shown in the first request priority parameter 38a ₁ in FIG. 4, the transfer source bus number # 0
In it the same time the transfer destination from the first bus B1 there is a request of the "bus data transfer" to the fourth bus B4 is a bus number # 3, as shown in the second request priority parameter 38a _2, The execution case 2 will be described as a case where there is a request for “data transfer within the bus” from the second bus B2 whose transfer source is the bus number # 1 to the second bus B2 whose transfer destination is also the bus number # 1. . The former is "data transfer between buses" because data transfer is performed between buses having different bus numbers, and the latter is "data transfer in bus" because data transfer is performed between buses having the same bus number. . In execution case 2, there are only these two data transfer requests, and no other requests exist.

The request of "data transfer between buses" is sent to the first
The first bus arbitration circuit A1 received via the bus B1 and the connection line 41 determines the occurrence of the "data transfer between buses" request, and sets the request line 51 to execute the "data transfer between buses". A request is issued to the multi-bus arbitration circuit 10 via the interface. Also,
The second bus arbitration circuit A2, which has received the request for "data transfer within the bus" via the second bus B2 and the connection line 42, judges the occurrence of the "data transfer within the bus", and The request is issued to the multi-bus arbitration circuit 10 via the request line 52 in order to execute "."

As described above, the multi-bus arbitration circuit 10 that has received the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, It reaffirmed by monitoring that the request from the bus arbitration circuit is not present, "inter-bus data transfer from the bus number # 0 of the transfer source for the first request priority parameter 38a ₁ to the transfer destination bus number # 3 Does not occur between the transfer source bus number # 1 and the "bus data transfer" from the transfer source bus number # 1 to the same bus number # 1 with respect to the _second request priority parameter 38a2 (with the transfer destination bus number # 3). # 1 does not match), and "data transfer between buses" from the first bus B1 to the fourth bus B4.
And it is determined that “data transfer within the bus” in the second bus B2 can be simultaneously executed. In this case, for both requests, the request priority is “00” and the request priority is the highest, which indicates the request priority 1. However, since there is no collision, there is no particular need to determine the request priority. Then, the transfer destination bus collision determination unit 2
0 instructs the data transfer execution unit 33 to perform “data transfer between buses” and “data transfer in the bus”.

In the case of the execution case 2, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to both the first bus arbitration circuit A1 and the second bus arbitration circuit A2. do not do. Data transfer execution unit 33
From the first bus B1 (# 0) to the fourth bus B4 (# 3)
And "data transfer within the bus" in the second bus B2 (# 1) are executed in parallel.

[Execution Case 3] Execution case 3 is a change of execution case 2 in which an "inter-bus data transfer" request and an "intra-bus data transfer" request, at which a collision occurs, occur simultaneously. It is about. First request priority parameter 38a of FIG.
_As shown in FIG. 1, a first bus B1 whose transfer source is bus number # 0 to a second bus B2 whose transfer destination is bus number # 1
At the same time there is a request for "bus data transfer" to, as shown in the second request priority parameter 38a _2, the second bus B transfer source is the bus number # 1
2 to the second bus B whose transfer destination is also the bus number # 1.
The case in which there is a request for “data transfer within the bus” for No. 2 will be described as execution case 2. In execution case 3, there are only these two data transfer requests, and no other requests exist.

The multi-bus arbitration circuit 10, which has received the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, sets the other bus arbitration circuits in the internal transfer destination bus collision determination unit 20 to the other bus arbitration circuits. From the transfer source bus number # 0 to the transfer destination bus number # ₁ for the _first request priority parameter 38a1.
1 and the bus number # of the transfer source for the _second request priority parameter 38a2.
1 to the same bus number # 1 and a “data transfer within the bus” has occurred (the transfer destination bus numbers # 1 and #).
1 matches), the processing is deposited in the transfer destination bus determination unit 30. First, the transfer destination bus determination unit 30 operates the request priority determination unit 31.

The request priority determining unit 31, the parameter "01" of the request priority parameters of the request priority in the first request priority parameter 38a ₁ "00" and the second request priority parameter 38a ₂ Make a comparison. When the parameter is “00”, the request priority is the highest request priority 1, and when the parameter is “01”, the request priority is 2
It is. Therefore, from the first bus B1 to the second bus B
2 “Data transfer between buses” is given priority,
The “data transfer within the bus” in the second bus B2 is to be canceled. The request priority determination unit 31 gives an instruction to execute the “in-bus data transfer” related to the low-order second request priority parameter 38a ₂ to the cancel processing unit 34, and also sets the high-order first request priority parameter An instruction to execute “data transfer between buses” relating to 38 a ₁ is given to the data transfer execution unit 33.

In the case of the execution case 3, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to the second bus arbitration circuit A2. Upon receiving the cancel signal, the second bus arbitration circuit A2 determines that the request cannot be executed, and stops the "intra-bus data transfer". Also, the cancel signal is not returned to the first bus arbitration circuit A1. The data transfer execution unit 33 executes only “inter-bus data transfer” from the first bus B1 (# 0) to the second bus B2 (# 1).

As described above, when the transfer destination is the same bus and a collision occurs, the request priority parameter 38a
_1, to determine the priority of the request priority in 38a _2, executes only request a higher priority.

[Execution case 4] Execution case 4 is also a change of execution case 2, in which an "inter-bus data transfer" request and an "intra-bus data transfer" request, at which a collision occurs, occur simultaneously. It is about. Similar to run casing 3, and the bus number # 1 destination for bus number # 1 and the second request priority parameter 38a ₂ destination for the first request priority parameter 38a ₁ are colliding . Differs from the run casing 3 is that the first request priority parameter 38a ₁ of the request priority and the second request priority of the request priority parameter 38a ₂ are reversed.

The multi-bus arbitration circuit 10, which has received the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, has a collision of the transfer destination (the bus number # 1 of the transfer destination). And # 1 coincide with each other), the process is deposited in the transfer destination bus determination unit 30.

The request priority determining unit 31 in the transfer destination bus determining unit 30 determines the request priority parameter “01” in the first request priority parameter 38a ₁ and the second request priority parameter 38.
parameters of the request priority in a ₂ "00"
And judge. As a result, “data transfer within the bus” within the second bus B2 is prioritized, and “data transfer between buses” from the first bus B1 to the second bus B2 is performed.
Will be canceled. The request priority determination unit 31 gives an instruction to the cancel processing unit 34 regarding “inter-bus data transfer” related to the low-priority first request priority parameter 38a ₁ , and the high-priority second request priority parameter 38a _2. The instruction to execute the “data transfer in the bus” related to the data transfer execution unit 33 is given.

In the case of the execution case 4, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to the first bus arbitration circuit A1. Upon receiving the cancel signal, the first bus arbitration circuit A1 determines that the request cannot be executed, and stops the "data transfer between buses". Further, the cancel signal is not returned to the second bus arbitration circuit A2. The data transfer execution unit 33 executes only “intra-bus data transfer” in the second bus B2 (# 1).

As described above, when the transfer destination is the same bus and a collision occurs, the request priority parameter 38a
_1, to determine the priority of the request priority in 38a _2, executes only request a higher priority.

[Execution Case 5] Execution case 5 is a case where two "data transfer between buses" requests that do not cause a collision occur simultaneously. As shown in the first request priority parameter 38a ₁ in FIG. 7,
At the same time as a request for “data transfer between buses” from the first bus B1 whose transfer source is the bus number # 0 to the fourth bus B4 whose transfer destination is the bus number # 3, the second request priority parameter as shown in 38a _2, the case where the transfer source is on request of "bus data transfer" transfer destination from the second bus B2 is a bus number # 1 is for the third bus B3 is a bus number # 2 This will be described as execution case 5. In execution case 5, there are only these two data transfer requests, and no other requests exist.

The first bus arbitration circuit A1, which receives the first request for "data transfer between buses" via the first bus B1 and the connection line 41, judges the occurrence of the request for "data transfer between buses". "Data transfer between buses"
The request is issued to the multi-bus arbitration circuit 10 via the request line 51 in order to execute Also, the second “data transfer between buses” request received via the second bus B2 and the connection line 42
Bus arbitration circuit A2 determines the occurrence of the "inter-bus data transfer" request and issues a request to the multi-bus arbitration circuit 10 via the request line 52 to execute the "inter-bus data transfer" request. .

As described above, the multi-bus arbitration circuit 10 that has received the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, It reaffirmed by monitoring that the request from the bus arbitration circuit is not present, "inter-bus data transfer from the bus number # 0 of the transfer source for the first request priority parameter 38a ₁ to the transfer destination bus number # 3 And "inter-bus data transfer" from the transfer source bus number # 1 to the transfer destination bus number # 2 with respect to the _second request priority parameter 38a2 (the transfer destination bus number #). 3 and # 2 do not match).
The first "data transfer between buses" from the first bus B1 to the fourth bus B4 and the second "data transfer between buses" from the second bus B2 to the third bus B3 can be executed simultaneously. to decide. In this case, for both requests, the request priority is “00” and the request priority is the highest, which indicates the request priority 1. However, since there is no collision, there is no particular need to determine the request priority.
Then, the transfer destination bus collision determination unit 20 instructs the data transfer execution unit 33 to perform two “data transfer between buses”.

In the case of execution case 5, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to both the first bus arbitration circuit A1 and the second bus arbitration circuit A2. do not do. Data transfer execution unit 33
From the first bus B1 (# 0) to the fourth bus B4 (# 3)
To the first "data transfer between buses" and the second bus B2 (#
1) The second "data transfer between buses" to the third bus B3 (# 2) is executed in parallel.

[Execution Case 6] Execution case 6 is a case where two "bus-to-bus data transfer" requests that cause a collision with each other are simultaneously generated. As shown in the first request priority parameter 38a ₁ in FIG. 8, the transfer source between "bus for the fourth bus B4 destination is bus number # 3 from the first bus B1 is a bus number # 0 at the same time there is a request for data transfer ", as shown in the second request priority parameter 38a _2,
The execution case 6 is a case where there is a request for “data transfer between buses” from the second bus B2 whose transfer source is the bus number # 1 to the fourth bus B4 whose transfer destination is the same bus number # 3. explain. In execution case 6,
There are only these two data transfer requests, and no other requests exist.

Upon receiving the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, the multi-bus arbitration circuit 10 in the internal transfer destination bus collision determination unit 20 performs the other bus arbitration circuits. From the transfer source bus number # 0 to the transfer destination bus number # ₁ for the _first request priority parameter 38a1.
And "Bus data transfer" first to 3, the second "bus data transfer from the bus number # 1 of the transfer source for the second request priority parameter 38a ₂ to the transfer destination bus number # 3 Is confirmed (the transfer destination bus numbers # 3 and # 3 match), the process is deposited in the transfer destination bus determination unit 30. First, the transfer destination bus determination unit 30 operates the request priority determination unit 31.

The request priority determining unit 31 compares determine the "01" in the request priority parameter 38a ₂ of "00" and the second parameter of the request priority in the first request priority parameter 38a _1. Parameter “00” is request priority 1 and “01” is request priority 2. Therefore, priority is given to the first "data transfer between buses" request from the first bus B1 to the fourth bus B4, which is the first "data transfer between buses", and the second "data transfer between buses" is given priority. The request “data transfer between buses” from the second bus B2 to the fourth bus B4 is canceled. The request priority determination unit 31 determines the second priority
Involved in the request priority parameter 38a ₂ along with providing an instruction to the elimination processing unit 34 for the "Bus data transfer", run data transfer for according to the first request priority parameter 38a ₁ of high priority "bus data transfer" An execution instruction is given to the unit 33.

In the case of execution case 6, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to the second bus arbitration circuit A2. Upon receiving the cancel signal, the second bus arbitration circuit A2 determines that the request cannot be executed and stops the second "data transfer between buses". Further, it does not return a cancel signal to the first bus arbitration circuit A1. Data transfer execution unit 3
3 is a first bus B1 (# 0) to a fourth bus B4 (#
Only the first "transfer data between buses" to 3) is executed.

As described above, when the transfer destination is the same bus and a collision occurs, the request priority parameter 38a
_1, to determine the priority of the request priority in 38a _2, executes only request a higher priority.

[Execution Case 7] The execution case 7 is a case where two "data transfer between buses" requests that cause a collision with each other are generated at the same time, and both request priorities have the same priority. is there. FIG. 9 (a)
First as shown in the request priority parameter 38a ₁ of the transfer source is the transfer destination "bus data transfer for the fourth bus B4 is a bus number # 3 from the first bus B1 is a bus number # 0 at the same time there is a request for "as shown in the second request priority parameter 38a _2, the transfer source is the same bus number # 3 and the transfer destination from said second bus B2 is a bus number # 1 first The case where there is a request for “data transfer between buses” to the bus B4 of No. 4 will be described as execution case 7. In execution case 7, there are only these two data transfer requests, and no other requests exist.

Upon receiving the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, the multi-bus arbitration circuit 10 in the internal transfer destination bus collision determination unit 20 performs the other bus arbitration circuits. From the transfer source bus number # 0 to the transfer destination bus number # ₁ for the _first request priority parameter 38a1.
And "Bus data transfer" first to 3, the second "bus data transfer from the bus number # 1 of the transfer source for the second request priority parameter 38a ₂ to the transfer destination bus number # 3 Is confirmed (the transfer destination bus numbers # 3 and # 3 match), the process is deposited in the transfer destination bus determination unit 30. First, the transfer destination bus determination unit 30 operates the request priority determination unit 31.

[0053] The request priority determining unit 31 compares determine the parameters of the request priority in the first request priority parameter 38a requests priority parameters and second request priority parameter 38a ₂ in _1. In this case, the parameters are both "00" (request priority 1), which is the same. Therefore, the request priority determination unit 3
1 entrusts the processing to the transfer source bus priority determining unit 32.

The transfer source bus priority determining unit 32 is configured as shown in FIG.
The transfer source bus priority parameter 38b shown in FIG. The bus number of the transfer source of the first “data transfer between buses” request is # 0, which has the priority order 1. The bus number of the second “data transfer between buses” request is # 1, which has priority order 2.
Therefore, priority is given to the “first-request data transfer between buses” from the first bus B1 to the fourth bus B4, and the second request to the second bus B2
"Data transfer between buses" to the fourth bus B4 is canceled. The transfer source bus priority determining unit 32 determines the low-priority second request priority parameter 38a _2.
The instruction is given to the cancel processing unit 34 regarding the “data transfer between buses” relating to the “data transfer between buses”, and the execution instruction is given to the data transfer execution unit 33 for the “data transfer between the buses” relating to the first request priority parameter 38a ₁ having the higher priority. give.

In the case of the execution case 7, as a result of the above-described synthesis, the cancel processing unit 34 returns a cancel signal to the second bus arbitration circuit A2. Upon receiving the cancel signal, the second bus arbitration circuit A2 determines that the request cannot be executed and stops the second "data transfer between buses". Further, it does not return a cancel signal to the first bus arbitration circuit A1. Data transfer execution unit 3
3 is a first bus B1 (# 0) to a fourth bus B4 (#
Only the first "transfer data between buses" to 3) is executed.

As described above, when the transfer destination is the same bus and a collision occurs, the request priority parameter 38a
₁ , 38 a _2, the priority of the request is determined. If the priorities are the same, the priority based on the transfer source bus priority parameter 38 _b is further determined, and the request having the higher priority is determined. Only run.

[Execution Case 8] Execution case 8 is a case where only one "bus broadcast data transfer" request is generated. “Bus broadcast data transfer” refers to simultaneous data transfer from a certain transfer source to a plurality of transfer destinations. As shown in the request priority parameter 38a of FIG. 10, the transfer source is the bus number # 0 to the first bus B1.
The case where there is a request for “data transfer between buses” to three transfer destinations of the second bus B2, the third bus B3, and the fourth bus B4 of # 1, # 2, and # 3 will be described as execution case 8. . In execution case 8, there is only one data transfer request, and no other requests exist. A first “data transfer between buses” from bus number # 0 to bus number # 1, a second “data transfer between buses” from bus number # 0 to bus number # 2, and a bus from bus number # 0 to bus Third "data transfer between buses" to number # 3
And do not collide with each other.

The first bus arbitration circuit A1, which has received the request for "bus broadcast data transfer" which is a composite of "data transfer between buses" shown in FIG. It determines the occurrence of a “bus broadcast data transfer” request and issues a request to the multi-bus arbitration circuit 10 via the request line 51 to execute the “bus broadcast data transfer”. Upon receiving the request from the first bus arbitration circuit A1, the multi-bus arbitration circuit 10 checks in the internal transfer destination bus collision determination unit 20 that there is no request from another bus arbitration circuit by a monitor. Priority parameter 3
8a, the bus numbers # 1, # 2, and # 3 that are "1" for the transfer destination are checked, and the first bus B1
"Data transfer between buses" to the first bus B2 and the first bus B1.
From the first bus B1 to the fourth bus B4, that is, "bus broadcast data transfer" from the first bus B1 to the fourth bus B4. . In this case, the request priority is “00”, which indicates the request priority 1 having the highest priority, but there is no other request, so there is no need to determine the request priority.
Then, the transfer destination bus collision determination unit 20 instructs the data transfer execution unit 33 to perform “bus broadcast data transfer” for the request.

In the case of execution case 8, as a result of the above synthesis, the cancel processing unit 34 does not return a cancel signal to the first bus arbitration circuit A1. The data transfer execution unit 33 transmits the first bus B1 (# 0) to the second bus B2 (# 1), the third bus B3 (# 2), and the fourth bus B3 (# 2).
"Data transfer between buses" to bus B4 (# 3)
"Bus broadcast data transfer" is executed.

[Execution Case 9] Execution case 9 is a case where two "bus broadcast data transfer" requests that cause a collision with each other are simultaneously generated. First request priority parameter 3 in FIG.
8a1, the _first transfer source is the bus number # 0.
Of the first "bus broadcast data transfer" from the bus B1 to the three transfer destinations of the second bus B2, the third bus B3, and the fourth bus B4 of the bus numbers # 1, # 2, and # 3. there simultaneously, as shown in the second request priority parameter 38a _2, the transfer source bus number #
Bus numbers # 0, # 2, # 3 from the second bus B2 which is 1
The case where there is a request for the second “bus broadcast data transfer” to the three transfer destinations of the first bus B1, the third bus B3, and the fourth bus B4 will be described as an execution case 9. In execution case 9, there are only these two requests for data transfer, and no other requests exist. The bus numbers # 2 of the transfer destinations in both “bus broadcast data transfer” collide with each other, and the bus numbers # 3 of the transfer destination also collide with each other.

The first "data transfer between buses" shown in FIG.
The first bus arbitration circuit A1 that has received the request for “bus broadcast data transfer”, which is a combination of the two, via the first bus B1 and the connection line 41, determines the occurrence of the “data transfer between buses” request, A request is issued to the multi-bus arbitration circuit 10 via the request line 51 in order to execute “data transfer between buses”. Further, the second bus arbitration circuit A2, which has received the request for “bus broadcast data transfer”, which is a composite of the second “data transfer between buses”, via the second bus B2 and the connection line 42, generates the “bus broadcast data transfer”. Data transfer between
A request is determined, and a request is issued to the multi-bus arbitration circuit 10 via the request line 52 in order to execute “data transfer between buses”.

As described above, the multi-bus arbitration circuit 10 that has received the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, reaffirmed by monitoring that the request from the bus arbitration circuit is not present, the transfer from the bus number # 0 of the transfer source in the first "bus broadcast data transfer" shown in the first request priority parameter 38a ₁ in FIG. 11 "Data transfer between buses" to previous bus numbers # 2 and # 3
When, as "inter-bus data transfers" to the second request priority parameter 38a ₂ to the second showing of the bus number # 1 of the transfer source in the "bus broadcast data transfer" of the destination bus number # 2 and # 3 (The transfer destination bus numbers # 2 and # 3 match each other), and the process proceeds to the transfer destination bus determination unit 3.
Leave at 0.

The request priority determining unit 31 in the transfer destination bus determining unit 30 determines that the request priority parameter “00” in the first request priority parameter 38a ₁ and the second request priority parameter 3
Comparing determined and "01" in 8a _2. When the parameter is “00”, the request priority is the highest request priority 1, and when the parameter is “01”, the request priority is 2
It is. Therefore, the "bus-to-bus data transfer" from the first bus B1 to the second bus B2, the third bus B3, and the fourth bus B4, which is the first "bus broadcast data transfer" request, has priority. In this case, the "bus data transfer" from the second bus B2 to the first bus B1, the third bus B3, and the fourth bus B4, which is the second "bus broadcast data transfer" request, is canceled. And The request priority determining unit 31 determines the second request priority parameter 38a ₂ of the lower priority.
The instruction is given to the cancel processing unit 34 regarding the “bus broadcast data transfer” relating to the first request priority parameter 38a ₁ relating to the high-order first request priority parameter 38a ₁ , and the execution instruction is given to the data transfer execution unit 33 for the “bus broadcast data transfer” relating to the high priority first request priority parameter 38a1. give.

In the case of the execution case 9, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to the second bus arbitration circuit A2. Upon receiving the cancel signal, the second bus arbitration circuit A2 determines that the request cannot be executed, and stops the second “bus broadcast data transfer”. The first bus arbitration circuit A
No cancel signal is returned for 1. The data transfer execution unit 33 transmits the first bus B1 (# 0) to the second bus B2 (# 1), the third bus B3 (# 2), and the fourth bus B3 (# 2).
Only "bus broadcast data transfer" for the bus B4 (# 3) is executed.

As described above, when a plurality of “bus broadcast data transfer” requests are issued at the same time, if at least one of the two requests has the same transfer destination bus and a collision occurs, the request priority parameter 38 a _1, to determine the priority of the request priority in 38a _2, executes only request a higher priority.

[Execution Case 10] The execution case 10 is a case where two "bus broadcast data transfer" requests that cause a collision with each other are generated at the same time, and the request priorities are the same. is there. Figure 12 As shown in the first request priority parameter 38a ₁ (a), the transfer destination bus number from the first bus B1 transfer source is the bus number # 0 # 1, # 2,
The second bus B2, the third bus B3 and the fourth bus # 3
At the same time there is a request for the bus B4 first of the "bus broadcast data transfer", as shown in the second request priority parameter 38a _2, the transfer from the second bus B2 transfer source is the bus number # 1 Execution case when there is a request for the second “bus broadcast data transfer” to the first bus B1, the third bus B3, and the fourth bus B4 whose destinations are the bus numbers # 0, # 2, and # 3 Explanation is made as 10. In execution case 10, there are only these two data transfer requests, and no other requests exist. The bus numbers # 2 of the transfer destinations in both “bus broadcast data transfer” collide with each other, and the bus numbers # 3 of the transfer destination also collide with each other.

Upon receiving the request from the first bus arbitration circuit A1 and the request from the second bus arbitration circuit A2, the multi-bus arbitration circuit 10 in the internal transfer destination bus collision determination unit 20 executes the other bus arbitration circuits. with the request to check the monitor that does not exist from the transfer destination bus number from the bus number # 0 of the transfer source in the "bus broadcast data transfer" for the first request priority parameter 38a ₁ # 2 and # 3 "bus and" bus data transfer ", to the second request priority parameter 38a ₂ bus number of the transfer destination from the transfer source bus number # 1 in the" bus broadcast data transfer "# 2 and # 3 on to Between the transfer destination bus numbers # 2 and # 3. When it is confirmed that the two coincide with each other, the process is deposited in the transfer destination bus determination unit 30. First, the transfer destination bus determination unit 30 operates the request priority determination unit 31.

The request priority determining unit 31 determines whether
First request priority parameter 38 shown in FIG.
Request priority parameter of the a ₁ and a second
Determining compare city in the request priority parameter 38a ₂ of. In this case, the parameters are both “0”.
0 "(request priority 1), which is the same rank. Therefore, the request priority determination unit 31 deposits the processing in the transfer source bus priority determination unit 32.

The transfer source bus priority order determination section 32
The transfer source bus priority parameter 38b shown in FIG. The bus number of the transfer source of the first “bus broadcast data transfer” request is # 0, which has the priority order 1. The bus number of the second “bus broadcast data transfer” request is # 1,
It has priority 2. Therefore, the "bus-to-bus data transfer" from the first bus B1 to the second bus B2, the third bus B3, and the fourth bus B4, which is the first "bus broadcast data transfer" request, has priority. In this case, the "bus data transfer" from the second bus B2 to the first bus B1, the third bus B3, and the fourth bus B4, which is the second "bus broadcast data transfer" request, is canceled. And The transfer source bus priority determining unit 32 gives an instruction to the cancel processing unit 34 regarding “bus broadcast data transfer” related to the low-order second request priority parameter 38a _2, and also sets the high-order first request priority parameter. An instruction to execute “bus broadcast data transfer” relating to 38 a ₁ is given to the data transfer execution unit 33.

In the case of execution case 10, as a result of the above-mentioned synthesis, the cancel processing unit 34 returns a cancel signal to the second bus arbitration circuit A2. Upon receiving the cancel signal, the second bus arbitration circuit A2 determines that the request cannot be executed, and stops the second “bus broadcast data transfer”. Further, it does not return a cancel signal to the first bus arbitration circuit A1. The data transfer execution unit 33 sends the second data from the first bus B1 (# 0)
Only the "bus-to-bus data transfer" to the third bus B2 (# 1), the third bus B3 (# 2) and the fourth bus B4 (# 3) is executed.

As described above, when a plurality of “bus broadcast data transfer” requests are issued at the same time, if at least one of the two requests has the same transfer destination bus and a collision occurs, the request priority parameter 38 a ₁ , 38 a _2, the priority of the request is determined. If the priorities are the same, the priority based on the transfer source bus priority parameter 38 _b is further determined, and the request having the higher priority is determined. Only run.

[0072]

According to the present invention for the multi-bus control device, data transfer of a plurality of requests is performed in parallel as long as the transfer destination bus does not collide, so that data transfer can be performed efficiently. In addition, regardless of whether the simultaneous multiple requests are “bus-to-bus data transfer”, “bus-to-bus data transfer”, or “bus-broadcast data transfer”, the priority order is changed. Data transfer can be executed in a state in which data is securely secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a multi-bus control device in a multi-bus configuration computer according to an embodiment of the present invention.

FIG. 2 is a diagram showing basic types of a request priority parameter and a transfer source bus priority parameter which are issued by attaching to a data transfer request in the embodiment.

FIG. 3 is a diagram illustrating a request priority parameter in the case of execution case 1 in the description of the operation of the multibus control device according to the embodiment;

FIG. 4 is a diagram showing request priority parameters in the case of execution case 2 in the description of the operation of the multibus control device according to the embodiment;

FIG. 5 is a diagram illustrating a request priority parameter in the case of execution case 3 in the description of the operation of the multibus control device according to the embodiment;

FIG. 6 is a diagram showing a request priority parameter in the case of execution case 4 in the description of the operation of the multibus control device according to the embodiment;

FIG. 7 is a diagram showing a request priority parameter in the case of execution case 5 in the description of the operation of the multibus control device according to the embodiment;

FIG. 8 is a diagram showing request priority parameters in the case of execution case 6 in the description of the operation of the multibus control device according to the embodiment;

FIG. 9 is a diagram illustrating a request priority parameter and a transfer source bus priority parameter in the case of execution case 7 in the description of the operation of the multibus control device according to the embodiment;

FIG. 10 is a diagram illustrating a request priority parameter in the case of execution case 8 in the description of the operation of the multibus control device according to the embodiment;

FIG. 11 is a diagram illustrating a request priority parameter in the case of execution case 9 in the description of the operation of the multibus control device according to the embodiment;

FIG. 12 is a diagram illustrating a request priority parameter and a transfer source bus priority parameter in the case of execution case 10 in the description of the operation of the multibus control device according to the embodiment;

FIG. 13 is a block diagram showing an electric configuration of a multi-bus control device in a multi-bus configuration computer according to the related art.

[Explanation of symbols]

A1: first bus arbitration circuit, A2: second bus arbitration circuit, A3: third bus arbitration circuit, A4: fourth bus arbitration circuit, B1: first bus, B2: second bus, B3: Third bus, B4: Fourth bus, 1: Multibus control device, 10: Multibus arbitration circuit, 20: Transfer destination bus collision determination unit, 30: Transfer destination bus determination unit, 31: Request priority Judgment unit, 32 ... Transfer source bus priority order judgment unit, 33
... data transfer execution unit, 34 ... cancellation processing unit, 38a
... request priority parameter, 38b transfer source bus priority parameter, 41, 42, 43, 44 ... connection line, 51, 52, 53, 54 ... request line, 6
1, 62, 63, 64: cancel line, μPi: microprocessor

Claims (7)

[Claims] 1. A multi-bus arbitration circuit for receiving a data transfer request from each of a plurality of bus arbitration circuits attached to each bus of a multi-bus configuration, wherein the multi-bus arbitration circuit is configured to receive a plurality of requests at the same time. A multi-bus control device having a function of executing each request in parallel when each transfer destination bus does not collide. 2. The simultaneous bus request includes an inter-bus data transfer request and an intra-bus data transfer request having different transfer destination buses, and the multi-bus arbitration circuit generates the inter-bus data transfer request and the intra-bus data transfer request. 2. The multi-bus control device according to claim 1, wherein the multi-bus control device is configured to execute in parallel. 3. The simultaneous request is a plurality of inter-bus data transfer requests having different transfer destination buses, and the multi-bus arbitration circuit is configured to execute these plurality of inter-bus data transfer requests in parallel. 2. The multi-bus control device according to claim 1, wherein: 4. A multi-bus arbitration circuit for receiving a data transfer request from each of a plurality of bus arbitration circuits associated with each bus having a multi-bus configuration, wherein the multi-bus arbitration circuit is configured to receive a plurality of requests simultaneously. When the destination buses do not collide, each request is executed in parallel, and when the destination buses collide, the priority of the request priority parameter for each request is compared and the lower priority requests are compared. A multi-bus control device having a function of returning a cancel to the set bus arbitration circuit and executing a data transfer of a high-order request. 5. A multi-bus arbitration circuit for receiving a data transfer request from each of a plurality of bus arbitration circuits attached to each bus of a multi-bus configuration, wherein the multi-bus arbitration circuit is configured to receive a plurality of requests at the same time. When the destination buses do not collide, each request is executed in parallel, and when the destination buses collide, the priority of the request priority parameter for each request is compared and the lower priority requests are compared. In addition to returning a cancel to the bus arbitration circuit that performed the request, data transfer of the higher-order request was executed, and when the requests were tied, the priority of the transfer source bus priority parameter for each request was compared and a lower-order request was made. Return the cancellation to the bus arbitration circuit and A multi-bus control device having a function of executing data transfer. 6. A multi-bus arbitration circuit, wherein at least one of the plurality of requests is a request for bus broadcast data transfer, and the multi-bus arbitration circuit performs a request for each request when at least one of the transfer destination buses of the plurality of requests collides. 5. The multi-bus according to claim 4, wherein the priority of the request priority parameter is compared, a cancel is returned to the bus arbitration circuit that made the low-order request, and the data transfer of the high-order request is executed. Control device. 7. A multi-bus arbitration circuit according to claim 1, wherein at least one of said plurality of requests is a request for bus broadcast data transfer, and said multi-bus arbitration circuit performs a transfer of said plurality of requests when at least one of the transfer destination buses collides. The priority of the request priority parameter is compared, a cancel is returned to the bus arbitration circuit that made the low-order request, the data transfer of the high-order request is executed, and when the requests have the same order, the transfer source bus for each request is returned. 6. The multi-bus control according to claim 5, wherein the priority of the priority parameter is compared, a cancel is returned to the bus arbitration circuit that made the low-order request, and the data transfer of the high-order request is executed. apparatus.