JP2000261292A5 - - Google Patents
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- Publication number
- JP2000261292A5 JP2000261292A5 JP2000047899A JP2000047899A JP2000261292A5 JP 2000261292 A5 JP2000261292 A5 JP 2000261292A5 JP 2000047899 A JP2000047899 A JP 2000047899A JP 2000047899 A JP2000047899 A JP 2000047899A JP 2000261292 A5 JP2000261292 A5 JP 2000261292A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/256,420 US6636572B1 (en) | 1999-02-24 | 1999-02-24 | High-speed digital timing and gain gradient circuit employing a parallel architecture |
| US256420 | 1999-02-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000261292A JP2000261292A (ja) | 2000-09-22 |
| JP2000261292A5 true JP2000261292A5 (ja) | 2007-04-26 |
Family
ID=22972163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000047899A Abandoned JP2000261292A (ja) | 1999-02-24 | 2000-02-24 | ディジタル帰還制御信号を処理するアーキテクチャおよび方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6636572B1 (ja) |
| JP (1) | JP2000261292A (ja) |
| KR (1) | KR20000076722A (ja) |
| SG (1) | SG96545A1 (ja) |
| TW (1) | TW457413B (ja) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8694569B2 (en) * | 2007-09-18 | 2014-04-08 | Pentomics, Inc. | High-speed system having compensation for distortion in a digital-to-analog converter |
| US8780470B1 (en) | 2013-03-11 | 2014-07-15 | Western Digital Technologies, Inc. | Disk drive adjusting digital phase locked loop over sector data with frequency induced phase error measured over preamble |
| CN106840214A (zh) * | 2017-04-05 | 2017-06-13 | 贵州电网有限责任公司电力科学研究院 | 一种绝对值信号转换装置及方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4355284A (en) * | 1977-09-01 | 1982-10-19 | Honeywell Inc. | Phase correction system |
| US4980860A (en) * | 1986-06-27 | 1990-12-25 | Texas Instruments Incorporated | Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry |
| JPH03143027A (ja) * | 1989-10-27 | 1991-06-18 | Fujitsu Ltd | ３値出力形ｄ／ａ変換器 |
| JP2648554B2 (ja) * | 1992-08-13 | 1997-09-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Ｐｒｍｌディスク駆動システムの非同期ゲイン調整方法および装置 |
| US5341387A (en) * | 1992-08-27 | 1994-08-23 | Quantum Corporation | Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection |
| US5389927A (en) * | 1993-05-28 | 1995-02-14 | Motorola, Inc. | Method and apparatus for control of an analog to digital converter |
| US6426663B1 (en) * | 1996-03-04 | 2002-07-30 | Delphi Technologies, Inc. | Analog/digital feedback circuitry for minimizing DC offset variations in an analog signal |
| US5815101A (en) * | 1996-08-02 | 1998-09-29 | Fonte; Gerard C. A. | Method and system for removing and/or measuring aliased signals |
| US6111531A (en) * | 1997-05-30 | 2000-08-29 | Lucent Technologies | Parallel architecture for a bandpass sigma-delta modulator |
| US6160506A (en) * | 1998-06-12 | 2000-12-12 | Lockheed Martin Corp. | Low-noise sigma-delta analog-to-digital converter |
| US6191716B1 (en) * | 1998-12-31 | 2001-02-20 | Texas Instruments Incorporated | High-speed digital circuit employing a band-zero-determination-aside (BØDA) architecture |
-
1999
- 1999-02-24 US US09/256,420 patent/US6636572B1/en not_active Expired - Lifetime
-
2000
- 2000-02-21 SG SG200000912A patent/SG96545A1/en unknown
- 2000-02-24 KR KR1020000008998A patent/KR20000076722A/ko not_active Application Discontinuation
- 2000-02-24 JP JP2000047899A patent/JP2000261292A/ja not_active Abandoned
- 2000-03-01 TW TW089103241A patent/TW457413B/zh not_active IP Right Cessation