JP2000260986A - Field-effect transistor having bidirectional current blocking function and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of leakage current in an off-state. SOLUTION: A surface gate electrode 24 is formed on a single-crystal silicon layer 22 and a buried gate electrode 20 is formed under the single-crystal silicon layer 22. Namely, the buried gate electrode 20, the single-crystal silicon layer 22, and the surface gate electrode 24 are laid to overlap vertically. In such a structure, the extending direction of a depletion layer becomes the thickness direction of the single-crystal silicon layer 22. The thickness of the single-crystal layer 22 depends on the thin-film formation technology. Therefore, the single- crystal silicon layer 22 can be made to be 0.5 μm or less in thickness. Furthermore, generation of leakage current can be suppressed in an off-state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a bidirectional current blocking function, and more particularly to a field effect transistor in which a storage layer serves as a path through which carriers pass, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Some field-effect transistors have a bidirectional current blocking function. The bidirectional current blocking function is to control the current from one source / drain to the other source / drain, and to control the current from the other source / drain to one source / drain A function that can be performed. There are various uses of the field effect transistor having the bidirectional current blocking function. For example, there are the following uses. Electric vehicles are operated at voltages around 300V. As the power source, for example, a battery in which 80 4V battery cells are connected in series is used. When this battery is charged, the voltage of each battery cell varies. In order to eliminate this variation, by turning on the field effect transistor, a current flows from the battery cell in the high voltage state to the battery cell in the low voltage state, and the voltage of each battery cell is made equal. in this case,
Which battery cell has a lower voltage depends on the situation. For this reason, the field effect transistor, which is a switching element, needs to have a bidirectional current blocking function.

FIG. 25 is a partial cross-sectional view of a field effect transistor having a bidirectional current blocking function disclosed in Japanese Patent Application Laid-Open No. Hei 8-213613. First, the structure of the field effect transistor will be described. On an n ⁺ type semiconductor substrate 202, an n type epitaxial layer 204 and an n ⁻ type epitaxial layer 206 are sequentially stacked. An n ⁺ -type source region 208 is formed on the surface of the n ⁻ -type epitaxial layer 206. The trench 210 penetrates the source region 208 and the epitaxial layer 206 and reaches the epitaxial layer 204. A gate electrode 214 is embedded in the trench 210. A gate oxide film 212 is formed between the trench 210 and the gate electrode 214. On the gate electrode 214, an insulating film 220 is formed. On the source region 208, the source electrode 21
6 are formed. Source electrode 216 and gate electrode 2
14 is insulated by an insulating film 220. Under the semiconductor substrate 202, a drain electrode 218 is formed.

Next, the operation of the field effect transistor will be described. First, the ON operation of the field effect transistor will be described. When a positive voltage is applied to the gate electrode 214, the gate electrode 214 of the epitaxial layer 206
The electrons in the epitaxial layer 206 are gathered in a portion facing the above, and an accumulation layer 222 is formed. When the voltage of the drain electrode 218 is higher than the voltage of the source electrode 216, electrons move through the source region 208, the storage layer 222, the epitaxial layer 204, and the semiconductor substrate 202 and are attracted to the drain electrode 218. Conversely, the source electrode 216
Is higher than the voltage of the drain electrode 218, the electrons move through the semiconductor substrate 202, the epitaxial layer 204, the storage layer 222, and the source region 208, and
Attracted to.

[0005] The OFF operation of the field effect transistor will be described. When a negative voltage is applied to the gate electrode 214, the storage layer 222 disappears. Instead, trench 210
The depletion layer spreads from the side surface of the epitaxial layer 206,
It comes into contact with the depletion layer spreading from the side of the adjacent trench. Thereby, the source electrode 216 and the drain electrode 21
8 is interrupted.

[0006]

In the field effect transistor having the above structure, the depletion layer extending from the side surface of one trench and the depletion layer extending from the side surface of the other trench come into contact with each other to pinch off the current. Set to OFF state. However, if the distance between the trenches is larger than 0.5 μm, the contact between the depletion layers is incomplete, and leakage current occurs even in the OFF state. Therefore, the distance between the trenches is set to 0.
It is desired that the thickness be 5 μm or less. However, with the current trench processing technology, it is difficult to reduce the distance between trenches to 0.5 μm or less.

The gate electrode 214 and the source region 20
8, only the gate oxide film 212 is present. For this reason,
The allowable potential difference between the source and the drain when the field effect transistor is OFF and the source region 208 side is at a high voltage depends on the withstand voltage of the gate oxide film. Since the gate oxide film is thin in nature, the allowable potential difference is 2
It is limited to 0V. Then, the dielectric breakdown of the gate oxide film directly results in the breakdown of the field effect transistor.

Further, the shape on the source region 208 side and the drain region side (semiconductor substrate 20
The shape of (2) is asymmetric. For this reason, the switching speed of the field-effect transistor differs between the direction from the source region 208 to the drain region side (the semiconductor substrate 202 side) and the opposite case.

The drift region (epitaxial layer 2)
There is also a problem that it is difficult to lower the resistance in 04).

The present invention has been made to solve the conventional problem, and an object of the present invention is to provide a field effect transistor capable of reducing generation of a leakage current in an OFF state and a method of manufacturing the same.

[0011]

SUMMARY OF THE INVENTION The present invention is a field effect transistor having a bidirectional current blocking function and having a storage layer serving as a path for carriers to pass through, the first and second sources having a first conductivity type. / Drain, first source / drain and second
The semiconductor device includes a first conductive type first semiconductor layer located between the source and the drain, and a gate electrode formed on at least one of the upper and lower portions of the first semiconductor layer. When a voltage is applied to the gate electrode, an accumulation layer in which carriers flow along the gate electrode is formed in the first semiconductor layer. The present invention further includes a second semiconductor layer of the first conductivity type located between the first source / drain and the gate electrode;
A third semiconductor layer of the first conductivity type located between the second source / drain and the gate electrode.

In the present invention, the gate electrode is formed on at least one of the upper and lower portions of the first semiconductor layer. That is, the first semiconductor layer and the gate electrode are vertically overlapped. In such a structure, the direction in which the depletion layer extends is the thickness direction of the first semiconductor layer. First
The thickness of the semiconductor layer depends on the thin film forming technology. On the other hand, the distance between trenches depends on the photolithography technology. The thin film forming technology can be made finer than the photolithography technology. Therefore, the thickness of the first semiconductor layer can be made smaller than the distance between the trenches. Therefore, OF
In the F state, it is possible to reduce the occurrence of leakage current.

Further, the second and third semiconductor layers function as drift layers. A second semiconductor layer is located between the gate electrode and the first source / drain. Gate electrode and second
A third semiconductor layer is located between the source and the drain. Therefore, the allowable potential difference between the first source / drain and the second source / drain when the field effect transistor is off depends on the withstand voltage of the second and third semiconductor layers. Therefore, the above-mentioned allowable potential difference is improved as compared with the case where it depends on the withstand voltage of the gate insulating film.

Note that the accumulation layer is a path formed by the first conductivity type carriers formed in the first conductivity type semiconductor layer. For example, if the semiconductor layer is n-type, the storage layer is n-type. When the semiconductor layer is p-type, the storage layer is p-type.

[0015] In the present invention, the gate electrode is preferably formed on the first semiconductor layer. In this embodiment, a depletion layer is formed from the upper part of the first semiconductor layer, and the depletion layer extends downward.

Further, in the present invention, the gate electrode is a first electrode.
It is preferably formed below the semiconductor layer. In this embodiment, a depletion layer is formed from below the first semiconductor layer, and the depletion layer extends upward. Further, the gate electrode is preferably formed in the first trench located between the second semiconductor layer and the third semiconductor layer. When the gate electrode is formed in the first trench, the drift region (second and third semiconductor layers)
Can be made uniform. Thereby, the effective area of the drift region can be increased. Therefore, the resistance of the drift region can be reduced, so that the resistance when the field effect transistor is ON can be reduced.

Further, in the present invention, the gate electrode is a first electrode.
And a second gate electrode, wherein the first gate electrode is formed on the first semiconductor layer. Preferably, the second gate electrode is formed below the first semiconductor layer. According to this aspect, the current can be cut off by the depletion layer generated from the upper portion of the first semiconductor layer and extending downward and the depletion layer generated from the lower portion and extending upward. For this reason, it is possible to more effectively reduce the generation of leakage current.

Further, in the present invention, the gate electrode is a second electrode.
It is preferably of the conductivity type. That is, it is preferable that the conductivity type of the gate electrode is different from the conductivity type of the first semiconductor layer.
According to this aspect, it is possible to reduce the occurrence of leakage current. Details will be described in embodiments of the invention.

In the present invention, it is preferable that the shape of the second semiconductor layer and the shape of the third semiconductor layer are symmetric with respect to the gate electrode. According to this aspect, the first source /
The difference between the switching speed from the drain to the second source / drain and the switching speed in the opposite direction can be reduced.

In the present invention, it is preferable that at least one of the first and second source / drain is formed in the second trench. According to this aspect, it is possible to make the current flowing in the drift region between the source / drain in the second trench and the gate electrode more uniform. This makes it possible to reduce the resistance of the drift region.

In the present invention, it is preferable that the shape of the first source / drain and the shape of the second source / drain are symmetric with respect to the gate electrode. According to this aspect, it is possible to reduce the difference between the switching speeds.

In the present invention, the thickness of the first semiconductor layer is preferably 0.5 μm or less. The thickness of the first semiconductor layer depends on the thin film forming technology, and the thickness can be set to 0.5 μm or less. The thickness of the first semiconductor layer is 0.3
More preferably, it is not more than μm.

In the present invention, it is preferable that carriers flow in the storage layer in the lateral direction.

According to the present invention, there is provided a method of manufacturing a field effect transistor in which a storage layer serves as a path through which carriers pass, wherein the storage layer is embedded between a second semiconductor layer of a first conductivity type and a third semiconductor layer of a first conductivity type. Forming a first semiconductor layer of a first conductivity type on the buried layer, the first semiconductor layer being electrically connected to the second semiconductor layer and the third semiconductor layer, and forming the storage layer; Forming a gate electrode on at least one of the upper and lower semiconductor layers, and forming first and second source / drain so that the second and third semiconductor layers are located therebetween; Is provided.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Description of Structure} FIG. 1 is a sectional view of a first embodiment of the present invention. An n ⁻ -type single crystal silicon layer is formed on the p ⁻ -type silicon substrate 10. The single crystal silicon layer has a trench 1 reaching the silicon substrate 10.
6, 28 and 32 are formed. This single crystal silicon layer is divided into a single crystal silicon layer 12 and a single crystal silicon layer 14 by a trench 16. Trench 16
A p-type buried gate electrode 20 made of polysilicon is buried therein. A gate oxide film 18 is formed in trench 16 so as to cover buried gate electrode 20.

An n ⁻ -type single crystal silicon layer 22 is formed on the buried gate electrode 20. There is a gate oxide film 18 between the single crystal silicon layer 22 and the buried gate electrode 20. Single crystal silicon layer 22 is located between single crystal silicon layer 12 and single crystal silicon layer 14. Gate oxide film 26 is located on single crystal silicon layer 22. On the gate oxide film 26, a p-type surface gate electrode 24 is located.

A source / drain region 30 made of polysilicon is buried in trench 28. In the trench 32, a source / drain region 34 made of polysilicon is buried.

{Description of Operation} The operation of the field effect transistor according to the first embodiment of the present invention will be described. First, the ON operation of the field effect transistor will be described. When a positive voltage is applied to the surface gate electrode 24 and the buried gate electrode 20, the storage layers 36, 3
8, 40 and 42 are formed. Single crystal silicon layer 12,
Electrons are gathered in the portions of the substrates 14 and 22 facing the surface gate electrode 24, and the storage layer 36 is formed. Electrons gather in a portion of the single-crystal silicon layers 12, 14, and 22 facing the upper surface of the buried gate electrode 20, and an accumulation layer 38 is formed. Electrons are collected in a portion of the single-crystal silicon layer 12 facing the side surface of the buried gate electrode 20, and an accumulation layer 40 is formed. Electrons collect in a portion of the single-crystal silicon layer 14 facing the side surface of the buried gate electrode 20, and the accumulation layer 42
Is formed.

When the voltage of the source / drain region 30 is higher than the voltage of the source / drain region 34, electrons are emitted from the source / drain region 34, the single crystal silicon layer 12,
It moves in the order of the accumulation layers 36 and 38. At this time, certain electrons move directly from the single crystal silicon layer 12 to the storage layers 36 and 38. Some electrons pass through the accumulation layer 40 and accumulate in the accumulation layers 36, 3
Go to 8. The electrons that have moved through the accumulation layers 36 and 38 move through the single crystal silicon layer 14 and are attracted to the source / drain regions 30. At this time, certain electrons move directly from the storage layers 36 and 38 to the single crystal silicon layer 14. Some electrons pass through the storage layer 42 and pass through the single crystal silicon layer 1.
Move to 4.

When the voltage of the source / drain region 34 is higher than the voltage of the source / drain region 30, the electrons move in the opposite direction.

FIG. 2 is a simulation of the flow of electrons in the field effect transistor of FIG. The line indicated by the symbol a is an example of the flow of electrons. Electrons are single crystal silicon layer 1
It can be seen that the particles 2 and 14 flow almost uniformly.

The OFF operation of the field effect transistor will be described. When 0 V or a negative voltage is applied to the surface gate electrode 24 and the buried gate electrode 20, the accumulation layer 36,
38, 40 and 42 disappear. Instead, the depletion layer generated from the upper portion of the single crystal silicon layer 22 and extending downward contacts the depletion layer generated from the lower portion and extending upward. As a result, the flow of current between the source / drain region 30 and the source / drain region 34 is blocked.

{Explanation of Effects} (Effect 1) According to the first embodiment, the surface gate electrode 24 is formed on the single crystal silicon layer 22 and the buried gate electrode 20 is formed below the single crystal silicon layer 22. Have been. That is, the buried gate electrode 20, the single-crystal silicon layer 22, and the surface gate electrode 24 are configured to overlap in the vertical direction. In such a structure, the direction in which the depletion layer extends is the thickness direction of single crystal silicon layer 22. The thickness of the single crystal silicon layer 22 depends on the thin film forming technology. Therefore, the thickness of single crystal silicon layer 22 can be reduced to 0.5 μm or less. Therefore, it is possible to reduce the occurrence of leakage current in the OFF state.

According to such a structure, the depletion layer generated at the time of the OFF operation of the field-effect transistor includes a depletion layer generated from the upper portion of the single-crystal silicon layer 22 and extending downward, and a depletion layer generated from the lower portion and extending upward. There is. Therefore, the effect of blocking the current can be enhanced as compared with only the depletion layer in which the depletion layer is generated from the upper portion of the single crystal silicon layer 22 and extends downward or only the depletion layer which is generated from the lower portion and extends upward.

(Effect 2) According to the first embodiment, the gate electrode (surface gate electrode 24, buried gate electrode 2
0) and the source / drain region 30 are located between the single-crystal silicon layers 14. The single-crystal silicon layer 12 is located between the gate electrode (the surface gate electrode 24 and the buried gate electrode 20) and the source / drain region 34. Therefore, the source / drain region 30 and the source / drain region 3 when the field effect transistor is OFF
The allowable potential difference between the single crystal silicon layers 12 and 14
It depends on the breakdown voltage of Therefore, the above-mentioned permissible potential difference can be improved as compared with a case depending on the withstand voltage of the gate insulating film.

(Effect 3) According to the first embodiment, the buried gate electrode 20 and the source / drain regions 30 and 34 buried in the trench are provided. For this reason,
As described with reference to FIG. 2, it is possible to equalize the current flowing through the drift regions (single-crystal silicon layers 12 and 14). Thereby, the effective area of the drift region can be increased. Therefore, the resistance of the drift region can be reduced, so that the resistance when the field effect transistor is ON can be reduced.

(Effect 4) According to the first embodiment, the gate electrode (surface gate electrode 24, buried gate electrode 2
0) is p-type. Single crystal silicon layer 22 is n-type. This contributes to the effect of reducing the occurrence of leakage current. This will be described below using a graph.

FIG. 3 shows a gate electrode (surface gate electrode 2).
4, a buried gate electrode 20) is a p-type, and the single-crystal silicon layer 22 is an n-type, and is a graph showing a relationship between a drain current and a drain voltage when the transistor is OFF.

The conditions are as follows. Gate electrode
(Surface gate electrode 24, embedded gate electrode 20)
The type of the p-type impurity to be contained is boron, and its concentration is 1
× 10 ²⁰cm^-3It is. Included in the single crystal silicon layer 22
The type of the n-type impurity is phosphorus, and its concentration is 1 × 10
¹¹cm^-3It is. In addition, the conditions mentioned here are examples,
The present invention is not limited to this.

FIG. 4 shows a gate electrode (surface gate electrode 2).
4, a buried gate electrode 20) is an n-type, and the single-crystal silicon layer 22 is a graph showing the relationship between the drain current and the drain voltage when the single-crystal silicon layer 22 is off when it is off.

The conditions are as follows. The type of the n-type impurity contained in the gate electrodes (the surface gate electrode 24 and the buried gate electrode 20) is phosphorus, and the concentration thereof is 1 ×
10 ²⁰ cm ^-3 . The type of the n-type impurity contained in the single crystal silicon layer 22 is phosphorus, and the concentration thereof is 1 × 10 ¹¹
cm ^-3 . Note that the conditions described here are merely examples, and the present invention is not limited to these.

As can be seen by comparing FIGS. 3 and 4, the gate electrodes (surface gate electrode 24, buried gate electrode 2
0) is a p-type, and the drain current (leakage current) at the time of OFF can be smaller when the single crystal silicon layer 22 is an n-type. It is presumed that the same effect is produced even when only one of the surface gate electrode 24 and the buried gate electrode 20 is p-type. In addition, the gate electrodes (surface gate electrode 24, buried gate electrode 2
0) is n-type, and the same effect is presumed to be obtained when the single crystal silicon layer 22 is p-type.

(Effect 5) According to the first embodiment, the gate electrode (the surface gate electrode 24, the buried gate electrode 2
In contrast to 0), the shape of the single crystal silicon layer 12 and the shape of the single crystal silicon layer 14 are symmetric, and the shape of the source / drain region 30 and the shape of the source / drain region 34 are symmetric. Therefore, the source / drain region 30
The switching speed from the gate to the source / drain region 34 is equal to the switching speed in the opposite direction.

[Second Embodiment] FIG. 5 is a sectional view of a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that an SOI substrate is used. That is, the silicon substrate 10 and the single crystal silicon layers 12, 1
4, buried gate electrode 20, source / drain region 3
A buried oxide film 44 is located between the buried oxide films 44 and.
The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted. The operation of the second embodiment is the same as the operation of the first embodiment.
The second embodiment is (effect 1) of the first embodiment.
The same effect as (Effect 5) is produced.

[Third Embodiment] {Description of Structure} FIG. 6 is a sectional view of a third embodiment of the present invention. The difference from the first embodiment shown in FIG.
The point is that there is no buried gate electrode 20. That is, the silicon oxide film 46 is buried in the trench 16 instead of the buried gate electrode 20. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted.

{Description of Operation} The operation of the field effect transistor according to the third embodiment of the present invention will be described. First, the ON operation of the field effect transistor will be described. When a positive voltage is applied to the front gate electrode 24, the front gate electrode 2 of the single crystal silicon layers 12, 14, 22
Electrons gather in a portion facing the storage layer 4 and the storage layer 36.
Is formed.

When the voltage of the source / drain region 30 is higher than the voltage of the source / drain region 34, electrons are supplied to the source / drain region 34, the single crystal silicon layer 12,
It moves in the order of the accumulation layer 36. The electrons that have moved through the storage layer 36 move through the single crystal silicon layer 14 and are attracted to the source / drain regions 30. When the voltage of the source / drain region 34 is higher than the voltage of the source / drain region 30, the electrons move in the opposite direction.

The OFF operation of the field effect transistor will be described. When 0 V or a negative voltage is applied to the front gate electrode 24, the accumulation layer 36 disappears. Instead, a current flows between the source / drain region 30 and the source / drain region 34 is blocked by a depletion layer formed from above the single crystal silicon layer 22 and extending downward.

{Explanation of Effects} According to the third embodiment, the same effects as (Effect 2), (Effect 4) and (Effect 5) of the first embodiment are produced. Further, the third embodiment produces the following effects.

According to the third embodiment, surface gate electrode 24 is formed on single crystal silicon layer 22. That is, the single-crystal silicon layer 22 and the surface gate electrode 24 are vertically overlapped. In such a structure, the direction in which the depletion layer extends is the thickness direction of single crystal silicon layer 22. Therefore, the thickness of single crystal silicon layer 22 can be reduced to 0.5 μm or less. For this reason, OFF
In this state, the occurrence of leakage current can be reduced.

[Fourth Embodiment] {Description of Structure} FIG. 7 is a sectional view of a fourth embodiment of the present invention. The difference from the first embodiment shown in FIG.
The point is that there is no surface gate electrode 24. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted.

{Description of Operation} The operation of the field effect transistor according to the fourth embodiment of the present invention will be described. First, the ON operation of the field effect transistor will be described. When a positive voltage is applied to the buried gate electrode 20,
The storage layers 38, 40, and 42 described below are formed.
Electrons gather in a portion of the single-crystal silicon layers 12, 14, and 22 facing the upper surface of the buried gate electrode 20, and an accumulation layer 38 is formed. Single crystal silicon layer 12
The electrons gather in a portion of the buried gate electrode 20 facing the side surface of the buried gate electrode 20 to form the accumulation layer 40. Electrons gather in a portion of the single-crystal silicon layer 14 facing the side surface of the buried gate electrode 20, and the accumulation layer 4
2 are formed.

When the voltage of the source / drain region 30 is higher than the voltage of the source / drain region 34, electrons are supplied to the source / drain region 34, the single crystal silicon layer 12,
The accumulation layer 38 is sequentially moved. At this time, certain electrons move directly from the single crystal silicon layer 12 to the storage layer 38. Some electrons pass through the storage layer 40 and move to the storage layer 38. The electrons that have moved through the accumulation layer 38 move through the single crystal silicon layer 14 and are attracted to the source / drain regions 30.
At this time, certain electrons move directly from the storage layer 38 to the single crystal silicon layer 14. Some electrons move to the single crystal silicon layer 14 through the storage layer 42. When the voltage of the source / drain region 34 is higher than the voltage of the source / drain region 30, the electrons move in the opposite direction.

The OFF operation of the field effect transistor will be described. When 0 V or a negative voltage is applied to the buried gate electrode 20, the accumulation layers 38, 40, and 42 disappear.
Instead, a depletion layer generated from a lower portion of the single crystal silicon layer 22 and extending upward blocks a current from flowing between the source / drain region 30 and the source / drain region 34.

{Explanation of Effects} According to the fourth embodiment, the same effects as (effect 2) to (effect 5) of the first embodiment are produced. Further, the fourth embodiment has the following effects.

According to the fourth embodiment, the buried gate electrode 20 is formed below the single crystal silicon layer 22. That is, the buried gate electrode 20 and the single-crystal silicon layer 22 are configured to overlap in the vertical direction. In such a structure, the direction in which the depletion layer extends is the thickness direction of single crystal silicon layer 22. Therefore, the single crystal silicon layer 22
Can have a thickness of 0.5 μm or less. Therefore, it is possible to reduce the occurrence of leakage current in the OFF state.

[Fifth Embodiment] {Description of Structure} FIG. 8 is a sectional view of a fifth embodiment of the present invention. The difference from the first embodiment shown in FIG.
The source / drain regions 30, 34 are not buried,
This is a point formed on the surfaces of the single crystal silicon layers 12 and 14. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted.

{Description of Operation} The operation of the field effect transistor according to the fifth embodiment of the present invention will be described. First, the ON operation of the field effect transistor will be described. When a positive voltage is applied to the surface gate electrode 24 and the buried gate electrode 20, the storage layers 36, 3
8, 40 and 42 are formed. Single crystal silicon layer 12,
Electrons are gathered in the portions of the substrates 14 and 22 facing the surface gate electrode 24, and the storage layer 36 is formed. Electrons gather in a portion of the single-crystal silicon layers 12, 14, and 22 facing the upper surface of the buried gate electrode 20, and an accumulation layer 38 is formed. Electrons are collected in a portion of the single-crystal silicon layer 12 facing the side surface of the buried gate electrode 20, and an accumulation layer 40 is formed. Electrons collect in a portion of the single-crystal silicon layer 14 facing the side surface of the buried gate electrode 20, and the accumulation layer 42
Is formed.

When the voltage of the source / drain region 30 is higher than the voltage of the source / drain region 34, electrons are supplied to the source / drain region 34, the single crystal silicon layer 12,
It moves in the order of the accumulation layers 36 and 38. At this time, certain electrons move directly from the single crystal silicon layer 12 to the storage layers 36 and 38. Some electrons pass through the accumulation layer 40 and accumulate layers 36, 3
Go to 8. The electrons that have moved through the accumulation layers 36 and 38 move through the single crystal silicon layer 14 and are attracted to the source / drain regions 30. At this time, certain electrons move directly from the storage layers 36 and 38 to the single crystal silicon layer 14. Some electrons pass through the storage layer 42 and pass through the single crystal silicon layer 1.
Move to 4.

When the voltage of the source / drain region 34 is higher than the voltage of the source / drain region 30, the electrons move in the opposite direction.

The OFF operation of the field effect transistor will be described. When 0 V or a negative voltage is applied to the surface gate electrode 24 and the buried gate electrode 20, the accumulation layer 36,
38, 40 and 42 disappear. Instead, the depletion layer generated from the upper portion of the single crystal silicon layer 22 and extending downward contacts the depletion layer generated from the lower portion and extending upward. As a result, the flow of current between the source / drain region 30 and the source / drain region 34 is blocked.

{Explanation of Effects} According to the fifth embodiment, the same effects as (Effect 1), (Effect 2), (Effect 4) and (Effect 5) of the first embodiment are produced. . In addition, the fifth
The embodiment has the effects described below.

According to the fifth embodiment, the buried gate electrode 20 is provided. Therefore, it is possible to make the current flowing through the drift regions (single-crystal silicon layers 12 and 14) uniform. Thereby, the effective area of the drift region can be increased. Therefore, the resistance of the drift region can be reduced, so that the resistance when the field effect transistor is ON can be reduced.

[Sixth Embodiment] A manufacturing method according to the present invention will be described according to a sixth embodiment of the present invention. As shown in FIG. 9, the bonded SOI substrate has p
And a buried oxide film 52 formed thereon, and an n-type single-crystal silicon layer 54 formed thereon. The field oxide films 56, 5 are formed on the single crystal silicon layer 54 by using, for example, the LOCOS method.
8, 60 and 62 are formed.

As shown in FIG. 10, the field oxide film 5
6, 58, 60, and 62, the silicon oxide film 6 is formed on the single crystal silicon layer 54 by using, for example, a CVD method.
4 (thickness: 0.3 to 1.0 μm). The silicon oxide film 64 is used as a mask when forming the trench. A resist is formed on the silicon oxide film 64. Using the resist as a mask, the silicon oxide film 64 is selectively removed using, for example, anisotropic etching. Then, the resist is removed. Using the silicon oxide film 64 as a mask, the single crystal silicon layer 54 is selectively removed using, for example, anisotropic etching to form a trench 68 (3 to 10 μm deep) reaching the buried oxide film 52. And
For example, buffered hydrofluoric acid (Buffered H)
Using F), the silicon oxide film 64 is removed.

As shown in FIG. 11, a gate oxide film 70 (having a thickness of 0.1 mm) is formed on the surface of the trench 68 by, for example, thermal oxidation.
(0.5-0.2 μm). Next, for example, C is formed on the single crystal silicon layer 54 so as to fill the trench 68.
Using the VD method, the polysilicon film 72 (with a thickness of 0.5 to 1.5
μm).

As shown in FIG. 12, for example, the polysilicon film 72 is patterned using a photolithography technique and an etching technique to form a buried gate electrode 74. The section of the buried gate electrode 74 is T-shaped. The upper portion of the buried gate electrode 74 (the so-called T-shaped bar) is on the single crystal silicon layer 54. The lower part of the buried gate electrode 74 (the so-called T-shaped vertical bar portion) is in the trench 68. Next, a gate oxide film 76 (0.05 to 0.2 μm in thickness) is formed on the upper surface of the buried gate electrode 74 by, for example, thermal oxidation.

As shown in FIG. 13, field oxide film 5
A resist 78 is formed so as to cover 6, 58, 60, 62 and the buried gate electrode 74. Using the resist 78 as a mask, the silicon oxide film on the single crystal silicon layer 54 (this silicon oxide film was formed when the gate oxide film was formed) is selectively etched away. Thus, an opening 80 exposing the single-crystal silicon layer 54 is formed next to the upper end of the buried gate electrode 74.

As shown in FIG. 14, field oxide films 56, 58, 60 and 62 are formed by solid phase epitaxial growth.
Then, an amorphous silicon film 82 is formed so as to cover the buried gate electrode 74.

As shown in FIG. 15, the amorphous silicon film 8
2 heat treatment (temperature about 650 ° C, time about 8 hours)
Then, the amorphous silicon film 82 is changed to a silicon single crystal film 84. Single crystal silicon layer 54 exposed at opening 80
Becomes a seed crystal.

As shown in FIG. 16, the silicon single crystal film 84 is patterned using, for example, a photolithography technique and an etching technique. The patterned silicon single crystal film 84 covers the buried gate electrode 74 and runs on the field oxide film. next,
For example, a gate oxide film 86 (0.05 to 0.2 μm in thickness) is formed on the surface of the silicon single crystal film 84 by thermal oxidation.

As shown in FIG. 17, the silicon single crystal film 8
4 so as to cover the single crystal silicon layer 54, for example,
Using a CVD method, a polysilicon film (having a thickness of 0.3 to 1.0 μm) is formed.
m). The polysilicon film becomes a surface gate electrode. A resist 88 is formed on the polysilicon film. Using the resist 88 as a mask, the polysilicon film is selectively etched away to form a surface gate electrode 90.

As shown in FIG. 18, the single crystal silicon layer 5
4 on the silicon oxide film 92 using, for example, a CVD method.
(With a thickness of 0.5 to 1.5 μm). A resist 94 is formed on the silicon oxide film 92. Using the resist 94 as a mask, the silicon oxide film 92 and the single crystal silicon layer 5
4 is selectively removed by etching. As a result, trenches 98 and 96 are formed between the field oxide film 56 and the field oxide film 58 and between the field oxide film 60 and the field oxide film 62. The trenches 98 and 96 reach the buried oxide film 52.

As shown in FIG. 19, trenches 96, 98
To fill the silicon oxide film 92 with, for example, C
Using the VD method, the polysilicon film 100 (having a thickness of 0.5 to 2.
0 μm).

As shown in FIG. 20, the polysilicon film 10
0 is etched back, and the polysilicon film 100 on the silicon oxide film 92 is removed. The etch back is continued, and the upper portion of the polysilicon film 100 in the trenches 96 and 98 (the polysilicon film 100 in the silicon oxide film 92) is removed. As a result, the lower portion of the polysilicon film 100 in the trenches 96 and 98 (the polysilicon film 100 in the single crystal silicon layer 54) remains. These are the source / drain region 102 buried in the trench 96, the trench 9
8 become the source / drain regions 104 buried inside.

As shown in FIG. 21, a silicon oxide film 92 is formed.
A resist 106 is formed thereon. Using the resist 106 as a mask, the silicon oxide film 92 is selectively etched away to expose the surface gate electrode 90. Then, the resist 106 is removed.

As shown in FIG. 22, an aluminum film 1 is formed on a silicon oxide film 92 by, for example, sputtering.
10 (thickness: 2 to 5 μm). Aluminum film 1
10 is buried in the upper part of the trench 96 (in the silicon oxide film 92) and is electrically connected to the source / drain region 102. The aluminum film 110 is embedded in the upper part of the trench 98 (in the silicon oxide film 92) and is electrically connected to the source / drain region 104.
The aluminum film 110 is embedded in the through hole 108 and is electrically connected to the surface gate electrode 90.

As shown in FIG. 23, the aluminum film 11
A resist 118 is formed on 0. Using the resist 118 as a mask, the aluminum film 110 is selectively etched away. Thereby, the source / drain regions 102
Wiring 112 electrically connected to the wiring, aluminum wiring 11 electrically connected to the source / drain region 104
4. An aluminum wiring 116 electrically connected to the surface gate electrode 90 is formed. Then, the resist 118 is removed. Through the above steps, a field effect transistor is completed as shown in FIG.

In the first to sixth embodiments, an n-type single-crystal silicon layer has been described on a p-type silicon substrate. However, a case where a p-type single-crystal silicon layer is formed on an n-type silicon substrate will be described. Even if there is, the present invention can be applied.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a diagram showing a simulation of an electron flow in the field-effect transistor of FIG.

FIG. 3 is a graph showing a relationship between a drain current and a drain voltage when the gate electrode (surface gate electrode 24, buried gate electrode 20) is p-type and the single-crystal silicon layer 22 is n-type. is there.

FIG. 4 is a graph showing the relationship between drain current and drain voltage when the gate electrode (surface gate electrode 24, buried gate electrode 20) is n-type and single-crystal silicon layer 22 is n-type when off. is there.

FIG. 5 is a sectional view of a second embodiment of the present invention.

FIG. 6 is a sectional view of a third embodiment of the present invention.

FIG. 7 is a sectional view of a fourth embodiment of the present invention.

FIG. 8 is a sectional view of a fifth embodiment of the present invention.

FIG. 9 is a sectional view of a first step of the sixth embodiment of the present invention.

FIG. 10 is a sectional view of a second step in the sixth embodiment of the present invention.

FIG. 11 is a sectional view of a third step in the sixth embodiment of the present invention.

FIG. 12 is a sectional view of a fourth step in the sixth embodiment of the present invention.

FIG. 13 is a sectional view of a fifth step according to the sixth embodiment of the present invention.

FIG. 14 is a sectional view of a sixth step of the sixth embodiment of the present invention.

FIG. 15 is a sectional view of a seventh step of the sixth embodiment of the present invention.

FIG. 16 is a sectional view of an eighth step of the sixth embodiment of the present invention.

FIG. 17 is a sectional view of a ninth step according to the sixth embodiment of the present invention.

FIG. 18 is a sectional view of a tenth step according to the sixth embodiment of the present invention.

FIG. 19 is a sectional view of an eleventh step according to the sixth embodiment of the present invention.

FIG. 20 is a sectional view of a twelfth step according to the sixth embodiment of the present invention.

FIG. 21 is a sectional view of a thirteenth step according to the sixth embodiment of the present invention.

FIG. 22 is a sectional view of a fourteenth step of the sixth embodiment of the present invention.

FIG. 23 is a sectional view of a fifteenth step according to the sixth embodiment of the present invention.

FIG. 24 is a sectional view of a sixteenth step according to the sixth embodiment of the present invention.

FIG. 25 is a partial cross-sectional view of a field effect transistor having a bidirectional current blocking function disclosed in Japanese Patent Application Laid-Open No. 8-213613.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Single crystal silicon layer 14 Single crystal silicon layer 16 Trench 18 Gate oxide film 20 Embedded gate electrode 22 Single crystal silicon layer 24 Surface gate electrode 26 Gate oxide film 28 Trench 30 Source / drain region 32 Trench 34 Source / drain region 36 accumulation layer 38 accumulation layer 40 accumulation layer 42 accumulation layer 44 buried oxide film 46 silicon oxide film 50 silicon substrate 52 buried oxide film 54 single crystal silicon layer 56 field oxide film 58 field oxide film 60 field oxide film 62 field oxide film 64 silicon Oxide film 68 trench 70 gate oxide film 72 polysilicon film 74 buried gate electrode 76 gate oxide film 78 resist 80 opening 82 amorphous silicon film 84 silicon single crystal film 86 gate acid Oxide film 88 resist 90 surface gate electrode 92 silicon oxide film 94 resist 96 trench 98 trench 100 polysilicon film 102 source / drain region 104 source / drain region 106 resist 108 through hole 110 aluminum film 112 aluminum wiring 114 aluminum wiring 116 aluminum wiring 118 Resist

Claims (5)

[Claims] 1. A field effect transistor in which a storage layer serves as a path through which carriers pass, wherein a first conductivity type first and second source / drain, a first source / drain, and a second source / drain are provided. A first semiconductor layer of a first conductivity type located between the first semiconductor layer and a gate electrode formed on at least one of the first semiconductor layer and the lower layer. A voltage is applied to the gate electrode. Thereby, the accumulation layer in which carriers flow along the gate electrode is formed in the first semiconductor layer, and a first conductivity type of the first conductivity type located between the first source / drain and the gate electrode is formed. A field effect transistor having a bidirectional current blocking function, comprising: a second semiconductor layer; and a third semiconductor layer of a first conductivity type located between the second source / drain and the gate electrode. 2. The semiconductor device according to claim 1, wherein the gate electrode is formed in a first trench located between the second semiconductor layer and the third semiconductor layer.
A field effect transistor having a bidirectional current blocking function. 3. The field effect transistor according to claim 1, wherein the gate electrode is of a second conductivity type and has a bidirectional current blocking function. 4. The bidirectional current blocking function according to claim 1, wherein the shape of the second semiconductor layer and the shape of the third semiconductor layer are symmetric with respect to the gate electrode. Field effect transistor. 5. A method for manufacturing a field effect transistor in which a storage layer serves as a path through which carriers pass, wherein a buried layer is provided between a second semiconductor layer of a first conductivity type and a third semiconductor layer of a first conductivity type. Forming a first conductive type first semiconductor layer on the buried layer, which is electrically connected to the second and third semiconductor layers and in which the storage layer is formed. Forming a gate electrode on at least one of above and below the first semiconductor layer; and so that the second and third semiconductor layers are located between
Forming a first and a second source / drain, a method for manufacturing a field-effect transistor having a bidirectional current blocking function.