JP2000260710A - Manufacture of semiconductor device and annealing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and an annealing apparatus, capable of forming a semiconductor element from a good quality semiconductor film by setting lamp annealing conditions to match changes in optical characteristics, during the crystallization of a non- crystalline semiconductor film. SOLUTION: After forming a semiconductor film 100 made of an amorphous silicon film on a substrate 50 formed of glass or the like with a low-temperature process (film-forming process), lamp annealing is performed to thereby make the film 100 polycrystalline (crystallization process). In the latter process the film 100 is irradiated with, a first lamp light L11 (whose energy is 1.6 eV or higher and whose wavelength is 700 nm or shorter), having optimal energy in terms of the band gap of the amorphous silicon (film 100), and thereafter it is irradiated with a second lamp light L12 (whose energy is 1.1-1.6 eV and wavelength of 700-1,130 nm or higher), having energy which can be absorbed by the film 100 in terms of the band gap of the amorphous silicon (film 100).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a polycrystalline semiconductor film obtained by subjecting an amorphous semiconductor film to a crystallization process, and an annealing method used for performing the method. It concerns the device. More specifically, the present invention relates to a lamp annealing technique performed as a crystallization process for an amorphous semiconductor film.

[0002]

2. Description of the Related Art Among various semiconductor devices, for example, when manufacturing a device using a thin film transistor (hereinafter referred to as a TFT) as an active element of an electro-optical device, an inexpensive glass substrate is used instead of a quartz substrate. Low-temperature processes are being adopted so that can be used. The low-temperature process generally means that the maximum temperature of the process (the maximum temperature at which the entire substrate simultaneously rises) is less than about 600 ° C. (preferably less than 500 ° C.), whereas the high-temperature process means the maximum temperature of the process (the substrate The maximum temperature at which the entire system rises simultaneously) is 8
The temperature is about 00 ° C. or higher, and a high-temperature step of 700 ° C. to 1200 ° C. such as thermal oxidation of silicon is performed.

However, in a low-temperature process, it is impossible to directly form a polycrystalline semiconductor film on a substrate. Therefore, an amorphous semiconductor film is formed using a plasma CVD method or a low-pressure CVD method. After this, it is necessary to crystallize this semiconductor film. As a method of this crystallization, for example, S
There are methods such as the PC method (Solid Phase Crystallization) and the RTA method (Rapid Thermal Annealing). However, lamp annealing, which irradiates the amorphous semiconductor film with lamp light, suppresses a rise in the temperature of the glass substrate and increases the temperature. Attention has been paid to a method for obtaining polycrystalline Si (silicon) having a particle size.

In the method of manufacturing a polycrystalline semiconductor film using the lamp annealing method, for example, as shown in FIG. 12, a base protective film 51 made of a silicon oxide film is formed on a whole surface of a substrate 50 made of glass or the like by plasma. It is formed by a CVD method. Next, an amorphous silicon (amorphous) semiconductor film 100 is formed on the entire surface of the substrate 50 by a method such as a plasma CVD method at a substrate temperature of about 150 ° C. to about 450 ° C. Next, lamp light is irradiated to the semiconductor film 100 to perform lamp annealing (crystallization step). In this crystallization step, for example, the semiconductor film 100 is irradiated with a beam in which the irradiation area L of the lamp light is long in the X direction.
Are shifted in the Y direction. As a result, the amorphous semiconductor film 100 is once melted and polycrystallized through a cooling and solidification process. In this case, since the irradiation time of the lamp light to each region is very short, and the irradiation region L is local to the entire substrate, the entire substrate 50 may be heated to a high temperature at the same time. Absent. Therefore, even if the temperature of the semiconductor film 100 locally exceeds about 800 ° C., a problem such as distortion of the substrate 50 does not occur.

[0005] When performing such lamp annealing, conventionally, an ultraviolet lamp is used as the light source 900, and light having an energy larger than the band gap of the amorphous silicon film (semiconductor film 100), for example, 1. The semiconductor film 100 is irradiated with light having an energy of 6 eV or more (light having a wavelength of 700 nm or less).

[0006]

However, the polycrystalline semiconductor film 100 obtained by performing lamp annealing under such conditions has a low degree of crystallization and still has dangling and distortion remaining. There is a problem that is. TFT using such a semiconductor film as an active layer
Is not preferable because the ON current level is still low and the ON current level varies widely. Such a problem cannot be solved by performing lamp annealing for a long time or repeatedly under the above-mentioned conditions.

[0007] Regarding such problems, the inventors of the present application have obtained the following knowledge from repeated experiments.
That is, as shown in FIG. 13, when the amorphous semiconductor film is subjected to furnace annealing to crystallize the semiconductor film, as the crystallization proceeds, the absorption coefficient for light having a wavelength of about 500 nm decreases. I got the knowledge. Therefore, no matter how long or repeatedly lamp annealing is performed, light having an energy of 1.6 eV or more (having a wavelength of 700 nm) is considered as light having the optimum energy in view of the band gap of the amorphous silicon film (semiconductor film 100). As long as the following light is used, such light is not absorbed to some extent by the crystallized semiconductor film, so that crystallization of the semiconductor film 100 or reduction of dangling bonds does not proceed.

Accordingly, an object of the present invention is to form a semiconductor element from a high-quality semiconductor film by setting lamp annealing conditions in accordance with a change in optical characteristics when an amorphous semiconductor film is crystallized. It is an object of the present invention to provide a semiconductor device manufacturing method capable of performing the method and an annealing apparatus suitable for performing the method.

[0009]

[Means for Solving the Problems] Under such a background,
As shown in FIG. 1, the inventor of the present application has found that, as shown in FIG. 1, when the amorphous semiconductor film is crystallized by lamp annealing, as the crystallization progresses, the energy of the lamp light and the absorption characteristics are reduced. Since the relationship changes, it is proposed to change the lamp annealing conditions in accordance with such optical characteristics. That is, the relationship between the energy of the lamp light and the absorption characteristics in the amorphous silicon film (semiconductor film) is shown by a solid line A1 in FIG. 1 is shown by a solid line A4 in FIG. 1, and the relationship between the energy of the lamp light and the absorption characteristics of the silicon film (semiconductor film) corresponding to the middle is shown by the solid lines A2 and A3 in FIG. Depending on the degree of crystallization, the silicon film has a band gap of about 1.6 eV, while the single crystal silicon film has a band gap of about 1.1 eV.
The band gap of the silicon film shifts.

In consideration of such a change in optical characteristics, the present invention provides a film forming step of forming an amorphous semiconductor film on a substrate, and a method of forming an amorphous semiconductor film formed by the film forming step. A crystallization step of crystallizing the semiconductor film by performing lamp annealing on the other hand, in the crystallization step, the crystallization step includes the step of forming the first semiconductor having energy larger than the band gap of the amorphous semiconductor film. A first lamp annealing treatment for irradiating the semiconductor film with light including lamp light,
After the first lamp annealing treatment, the semiconductor film is irradiated with light including second lamp light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film. A second lamp annealing process is performed.

That is, in this embodiment, the energy (wavelength) of the lamp light applied to the semiconductor film is changed in accordance with the shift of the band gap of the semiconductor film. Therefore, even after the crystallization of the semiconductor film has advanced, the annealing effect on the semiconductor film is large. Therefore, the polycrystalline semiconductor film obtained by the method according to the present invention has a high degree of crystallization and almost no dangling bonds or distortion remains. Therefore, when a TFT is formed from the semiconductor film subjected to the first lamp annealing and the second lamp annealing, a TFT having a high on-current level and a small variation in the on-current level can be formed.

In the present invention, in the crystallization step, the first lamp annealing and the second lamp annealing may be performed alternately. With such a structure, crystallization of the semiconductor film proceeds slowly, and a polycrystalline semiconductor film having a large crystal grain size can be obtained. Also, dangling bonds can be reliably removed. Therefore, when a TFT is formed from a semiconductor film that has been repeatedly subjected to the first lamp annealing process and the second lamp annealing process, a TFT having a high on-current level and a small variation in the on-current level can be formed. .

In the present invention, when the process shifts from the first lamp annealing process to the second lamp annealing process, light including the first lamp light and the second lamp light is applied to a semiconductor film. Irradiation may be performed.

In the present invention, in the second lamp annealing treatment, only the second lamp light may be irradiated, but light containing the first lamp light in addition to the second lamp light may be used. Irradiation may be performed.

In the present invention, when the semiconductor film is a silicon film, the first lamp light is 1.6 eV
It is light having the above energy. To irradiate such light, incandescent lamps, halogen lamps, fluorescent lamps,
Light emitted from a high-pressure mercury lamp, a metal halide lamp, a high-pressure sodium lamp, or an ultraviolet lamp may be used.

In the present invention, when the semiconductor film is a silicon film, the second lamp light is 1.1 eV
It is light having an energy of up to 1.6 eV. In order to irradiate such light, light emitted from an infrared lamp may be used.

In the polycrystalline semiconductor film obtained by the method according to the present invention, the degree of crystallization is high, and dangling bonds and distortion are scarcely left. Therefore, the first lamp annealing process and the second When a TFT is formed from a semiconductor film that has been subjected to a lamp annealing process, a thin film transistor having a high on-current level and a small variation in the on-current level can be formed.

In carrying out such a method, according to the present invention, in an annealing apparatus for performing lamp annealing on a semiconductor film formed on a substrate, an annealing apparatus having an energy larger than the band gap of the amorphous semiconductor film is used. A first light source that emits one lamp light, and a second light source that emits a second lamp light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film. Are provided.

In such an apparatus, for example, the first
And the second lamp light are irradiated alternately.

Here, the first light source is, for example, an incandescent lamp, a halogen lamp, a fluorescent lamp, a high-pressure mercury lamp, a metal halide lamp, a high-pressure sodium lamp, or an ultraviolet lamp. Further, the second light source includes:
For example, an infrared lamp.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, as an embodiment of the present invention, a P-type TFT for a drive circuit and an N-type TFT for a drive circuit are formed on an active matrix substrate of an electro-optical device. TFT and N-type T for pixel switching
An example of forming an FT will be described. Before describing each embodiment, contents common to each embodiment will be described.

[Overall Configuration] (Overall Configuration of Active Matrix Substrate) FIG.
FIG. 2B is a block diagram schematically illustrating a configuration of an active matrix substrate of the electro-optical device, and an equivalent circuit diagram of a COMS circuit forming a driving circuit thereof. FIG. 3 is a sectional view of three types of TFTs formed on the active matrix substrate shown in FIG.

As shown in FIG. 2A, in the active matrix substrate 200, in a transparent substrate made of glass or the like, in an image display area 81 corresponding to a substantially central area,
A pixel switching TFT 30 connected to a data line 90 and a scanning line 91 formed of a metal film such as aluminum, tantalum, molybdenum, titanium, or tungsten, a silicide film, or a conductive semiconductor film is formed for each pixel. Is formed with a liquid crystal capacitor 94 (liquid crystal cell) to which an image signal is input via the pixel switching TFT 30. For the data line 90, a data side drive circuit 60 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is configured. For the scanning line 91, the shift register 8
Scan-side drive circuit 70 including 8 and level shifter 89
Is configured. In each pixel, a storage capacitor 40 is formed between a scanning line 91 and a capacitor line 92 extending in parallel, and the storage capacitor 40 has a function of improving the charge holding characteristics of the liquid crystal capacitor 94. I have. This storage capacity 40
It may be formed between the scanning line 91 in the preceding stage.

(Basic Configuration of CMOS Circuit) In the driving circuits 60 and 70 on the data side and the scanning side, as shown in FIG. 2B, a CMOS circuit is constituted by the N-type TFT 10 and the P-type TFT 20. I have. Such CMOS
One or more stages of the driving circuits 60 and 70 constitute an inverter circuit.

(TFT on Active Matrix Substrate)
Therefore, as shown in FIG. 3, in the active matrix substrate 200, the surface side of the transparent substrate 50 made of glass is
N-type TFT 10 for drive circuit, P-type T for drive circuit
FT20 and N-type TFT3 for pixel switching
Three types of TFTs consisting of 0 are formed. In such an active matrix substrate 200, the substrate 50
Is formed on the underside protective film 51 made of a silicon oxide film, and a polycrystalline semiconductor film 100 patterned in an island shape is formed on the underside protective film 51. These semiconductor films 100 include an N-type TFT 10 for a driving circuit and a P-type TFT 2 for a driving circuit, respectively.
The gate insulating films 12, 22, and 32 are formed on the surface of each semiconductor film 100. The gate electrodes 1, 22, and 32 have a gate electrode 1 on their surfaces.
4, 24, and 34 are formed, and among these gate electrodes, the gate electrode of the N-type TFT 30 for pixel switching is a part of the scanning line 91 (see FIG. 1). Each semiconductor film 100 has a gate electrode 14, 2,
Channel regions 15 (not shown: 2) are formed in regions facing gate insulating films 4, 34 via gate insulating films 12, 22, 32.
5, 35) are formed. These channel regions 1
On both sides of 5, 25, 35, the gate electrodes 14, 24, 3
The low-concentration source / drain regions 17, 27, and 37 that face each other via the gate insulating films 12, 22, and 32 are formed, respectively. High-concentration source / drain regions 16, 26 and 36 are formed on both sides of the low-concentration source / drain regions 17, 27 and 37, respectively. The source electrode 4 through the contact hole of the insulating film 52
1, 43, a drain electrode 42, a source electrode 44 which is a part of the data line 90 (see FIG. 2), and a pixel electrode 4.
5 are electrically connected to each other.

As described above, in this embodiment, any TFT
Since 10, 20, and 30 also have the LDD structure, the off-leak current is small. For this reason, it is possible to prevent a reduction in contrast, display unevenness, flicker, malfunction of the driving circuit, and the like.
The display quality can be improved.

(Manufacturing Method of TFT) Among the manufacturing methods of the active matrix substrate 200 having such a configuration, the contents common to the respective embodiments described later will be described with reference to FIGS.

FIGS. 4 and 5 are process sectional views showing a method of manufacturing the active matrix substrate 200 of the present embodiment.

First, in FIG. 4A, after preparing a substrate 50 made of glass or the like cleaned by ultrasonic cleaning or the like,
When the substrate temperature is from about 150 ° C. to about 450 ° C.,
As shown in FIG. 4B, a thickness of 20
A base protective film 51 made of a silicon oxide film having a thickness of 00 Å to 5000 Å is formed by plasma CVD.
It is formed by a method. As the raw material gas at this time, for example, a mixed gas of monosilane and laughing gas, TEOS (tetraethoxysilane) and oxygen, or disilane and ammonia can be used.

Next, it is necessary to form a polycrystalline semiconductor film on the glass substrate 50 without thermally deforming the substrate 50. In order to form a polycrystalline semiconductor film under such restrictions, as shown in FIG.
A semiconductor film 100 made of an amorphous silicon film having a thickness of 300 Å to 700 Å is formed on the entire surface of the substrate 50 at a temperature of 50 ° C. to about 450 ° C. by a plasma CVD method. As the source gas at this time, for example, disilane or monosilane can be used (film formation step). Note that as a method for forming the amorphous semiconductor film 100 over the substrate 50 under a low-temperature condition, a low-pressure CVD method, an EB evaporation method, a sputtering method, or the like may be used instead of the plasma CVD method.

Next, as shown in FIG. 4C, the semiconductor film 100 is irradiated with lamp light to perform lamp annealing (crystallization step). The details of the conditions and the like performed here will be described later for each embodiment, but in each case, the lamp light emitted from the light source is irradiated toward the semiconductor film 100 on the substrate 50. As a result, the amorphous semiconductor film 100 is once melted and polycrystallized through a cooling and solidification process. In this case, the irradiation time of the lamp light to each region is very short, and the irradiation region is local to the entire substrate, so that the entire substrate 50 is not heated to a high temperature at the same time. . Therefore, the glass substrate used as the substrate 50 is inferior in heat resistance as compared with the quartz substrate, but is not deformed or cracked by heat. In this embodiment, the crystallization step is performed in a non-oxidizing atmosphere such as a nitrogen gas atmosphere, an argon gas atmosphere, a helium gas atmosphere, a hydrogen gas atmosphere, or a mixed gas atmosphere of these gases. For this reason, it is possible to prevent an oxide film having an unfavorable film quality as a gate insulating film from being formed on the surface of the semiconductor film 100.

After the semiconductor film 100 is thus polycrystallized, a TFT is formed using the semiconductor film 100 (transistor forming step).

First, as shown in FIG. 5A,
After patterning the polycrystalline semiconductor film 100 into an island shape,
A gate insulating film 1 made of a silicon oxide film having a thickness of 600 Å to 1500 Å by plasma CVD using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas on the surface side.
2, 22, and 32 are formed (gate insulating film forming step).

Next, a conductive film containing aluminum, tantalum, molybdenum, titanium, tungsten, or the like is formed by a sputtering method.
The T gate electrodes 14, 24, 34 are formed (gate electrode forming step).

Next, as shown in FIG. 5B, the formation regions of the N-type TFT 10 for the driving circuit and the N-type TFT 30 for the pixel switching are formed by a resist mask 61.
Cover with. In this state, when boron ions are implanted at a dose of about 10 ¹³ cm ⁻² , the impurity concentration in the semiconductor film 100 is about 10 ¹⁸ cm ^{−3 in a} self-aligned manner with respect to the gate electrode 24.
Is formed. Note that a portion where the impurity is not introduced becomes the channel region 25.

If this low concentration impurity implantation step is not performed, the P-type driving circuit TFT 20 has an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 5C, the formation region of the P-type TFT 20 for the driving circuit is
Cover with. In this state, when phosphorus ions are implanted at a dose of about 10 ¹³ cm ⁻² , the gate electrode 1
The impurity concentration is about 10 ¹⁸ c in a self-aligned manner with respect to 4, 34.
m ⁻³ low concentration N-type regions 13 and 33 are formed. In addition,
The portions where the impurities are not introduced are the channel regions 15, 3
It becomes 5.

If the low concentration impurity implantation step is not performed, the N-type drive circuit TFT 10 and the N-type pixel TFT 30 have an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 5D, in addition to the formation regions of the N-type TFT 10 for the driving circuit and the N-type pixel TFT 30 for the pixel switching, the gate electrode 2 is formed.
Then, a resist mask 63 is formed to cover 4 in a wider manner. In this state, boron ions are implanted into the low-concentration P-type region 23 at a dose of about 10 ¹⁵ cm ⁻² to reduce the impurity concentration to about 10 ^20.
A high concentration source / drain region 26 of cm ^-3 is formed.
The portion of the low-concentration P-type region 23 covered with the resist mask 63 is left as it is in the low-concentration source / drain region
Remains as 7. Thus, the P-type TF for the driving circuit
Form T20.

Next, as shown in FIG. 5E, a resist mask 64 is formed to cover the gate electrodes 14 and 34 in addition to the formation region of the P-type TFT 20 for the drive circuit. In this state, the low-concentration N-type regions 13 and 23 have about 10 ¹⁵
A high concentration source / drain region 1 with an impurity concentration of about 10 ²⁰ cm ⁻³ is implanted by implanting phosphorus ions at a dose amount of cm ^−2.
6 and 36 are formed. Portions of the low-concentration N-type regions 13 and 23 covered with the resist mask 64 remain as low-concentration source / drain regions 17 and 37 having an impurity concentration of about 10 ¹⁸ cm ⁻³ . Thus, the N-type TFT 10 for the driving circuit and the N-type TFT
The pixel TFT 30 is formed.

Thereafter, as shown in FIG.
Is formed, annealing for activation is performed, and then a contact hole is formed.
3. If the drain electrode 42 and the pixel electrode 45 are formed, the active matrix substrate 200 can be manufactured.

It is to be noted that a high concentration impurity is implanted using the gate electrodes 14, 24, 34 as a mask without introducing a low concentration impurity, and the source regions and the drains are self-aligned into the gate electrodes 14, 24, 34. A region may be formed.

[Embodiment 1] FIGS. 6 (A) and 6 (B) show how a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 1 of the present invention, respectively. FIG. 4 is an explanatory diagram and an explanatory diagram showing changes in lamp light received by the semiconductor film when lamp annealing is performed by this method.

As shown in FIG. 6A, in the present embodiment, when the crystallization step described with reference to FIG. 4C is performed, a beam whose irradiation area is long in the X direction is applied to the semiconductor. By irradiating the film 100 and shifting the irradiation area or the substrate 50, the irradiation area on the substrate 50 is shifted in the Y direction.

In the annealing apparatus for performing this step,
Light having an optimum energy in view of the band gap of the amorphous silicon film (semiconductor film 100), that is, the first lamp light L having an energy larger than this band gap.
11 (light / wavelength of energy of 1.6 eV or more is 700
In view of the band gap of the first light source 910 that irradiates the semiconductor film 100 with light, the second lamp light L12 (1. A second light source 920 for irradiating light having an energy of 1 eV to 1.6 eV / light having a wavelength of 700 nm to 1130 nm) is arranged in the direction of arrow Y. In this embodiment, light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film is used as the second lamp light L12. Here, the first light source 910 is, for example, an incandescent lamp, a halogen lamp, a fluorescent lamp, a high-pressure mercury lamp, a metal halide lamp, a high-pressure sodium lamp, or an ultraviolet lamp. The second light source 920 is an infrared lamp.

The light sources 910 and 920 are provided with reflectors 911 and 921 for reflecting light emitted from each light source toward the substrate 50. Therefore, the substrate 50
On the semiconductor film 100 formed on the surface of the first light source 910, the irradiation area L1 of the first lamp light L11 emitted from the first light source 910 and the second light emitted from the second light source 920 in the direction of the arrow Y. And the irradiation area L2 of the lamp light L12 are aligned without overlapping.

In the annealing apparatus configured as described above, when the irradiation regions L1 and L2 of the lamp light are shifted in the Y direction with respect to the amorphous semiconductor film 100, from one point of the semiconductor film 100, As shown in FIG. 6B, first, the first lamp light L11 (the light / wavelength of the energy of 1.6 eV or more) having the optimal energy is considered from the band gap of the amorphous silicon film (semiconductor film 100). 7
After the first lamp annealing process ST1 of irradiating the semiconductor film 1 (light of not more than 00 nm) is performed, the semiconductor film 1 is viewed from the band gap of the crystalline silicon film (semiconductor film 100).
The second lamp light L12 having energy that can be absorbed at 00
(Light / wavelength of energy of 1.1 eV to 1.6 eV is 7
(Light of 00 nm to 1130 nm) is irradiated with the second lamp annealing process ST2.

As described above, in the present embodiment, as described with reference to FIG.
As the band gap of the (silicon film) shifts, the energy (wavelength) of the lamp light applied to the semiconductor film 100 also changes. Therefore, even after the crystallization of the semiconductor film 100 has progressed, the annealing effect on the semiconductor film 100 is large. Therefore, in the polycrystalline semiconductor film 100 obtained by the method according to the present embodiment, the degree of crystallization is high, and dangling bonds and distortion are scarcely left. Therefore, the first lamp annealing ST1 and the second lamp annealing When a TFT is formed from the semiconductor film 100 that has been subjected to the lamp annealing process ST2, a TFT having a high on-current level and a small variation in the on-current level can be formed.

[Embodiment 2] FIGS. 7A and 7B respectively show a state in which a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 2 of the present invention. FIG. 4 is an explanatory diagram and an explanatory diagram showing changes in lamp light received by the semiconductor film when lamp annealing is performed by this method.

As shown in FIG. 7A, also in this embodiment, when the crystallization step described with reference to FIG.
The semiconductor film 1 emits a beam whose irradiation area is long in the X direction.
The irradiation area on the substrate 50 is shifted in the Y direction by irradiating the substrate with the light beam 00 and shifting the irradiation area or the substrate 50. In the annealing apparatus for performing this step, the first lamp light L1 having energy larger than the band gap of the amorphous silicon film (semiconductor film 100) is used.
1 (light / wavelength of energy of 1.6 eV or more is 700 n
m or less) and the band gap of the crystalline silicon film (semiconductor film 100) and the second energy of energy that can be absorbed by the semiconductor film 100.
And two second light sources 920 for irradiating the lamp light L12 (light having an energy of 1.1 eV to 1.6 eV / light having a wavelength of 700 nm to 1130 nm) are alternately arranged two by two along the direction of the arrow Y. . Again, the first light source 910 is
For example, incandescent lamps, halogen lamps, fluorescent lamps,
High pressure mercury lamp, metal halide lamp, high pressure sodium lamp, or ultraviolet lamp. Second light source 92
0 is an infrared lamp. In addition, each light source 910, 920
Are provided with reflectors 911 and 921 that reflect light emitted from each light source toward the substrate 50. Therefore, on the semiconductor film 100 formed on the surface of the substrate 50, in the direction of the arrow Y, the irradiation area L1 of the first lamp light L11 emitted from the first light source 910 and the emission area L1 emitted from the second light source 920 The irradiation area L2 of the first lamp light L12 is alternately arranged.

In the annealing apparatus configured as described above, when the irradiation regions L1 and L2 of the lamp light are shifted in the Y direction, when viewed from a certain point of the semiconductor film 100, as shown in FIG. First, the first lamp light L11 (light having an energy of 1.6 eV or more / light having a wavelength of 700 nm or less) having an optimum energy in view of the band gap of the amorphous silicon film (semiconductor film 100) is irradiated. After the first lamp annealing ST1, the second energy of the energy that can be absorbed by the semiconductor film 100 is considered in view of the band gap of the crystalline silicon film (semiconductor film 100).
(Light having an energy of 1.1 eV to 1.6 eV / light having a wavelength of 700 nm to 1130 nm) is irradiated with a second lamp annealing process ST2. Thereafter, the second lamp light L11 (the light / wavelength of the energy of 1.6 eV or more) having the optimum energy in view of the band gap of the amorphous silicon film (semiconductor film 100) is 70%.
0 nm or less) (the first lamp annealing process ST1), the semiconductor film 10 is viewed from the band gap of the crystalline silicon film (semiconductor film 100).
The second lamp light L12 having energy absorbable to zero
(Light / wavelength of energy of 1.1 eV to 1.6 eV is 7
(Light of 00 nm to 1130 nm) (second lamp annealing process ST2).

As described above, in the present embodiment, as described with reference to FIG.
As the band gap of the (silicon film) shifts, the energy (wavelength) of the lamp light applied to the semiconductor film 100 is changed, and light having different wavelengths is alternately applied. Therefore, even after the crystallization of the semiconductor film 100 has progressed, the annealing effect on the semiconductor film 100 is large.
In the semiconductor film 100, a crystal having a large grain size grows as the crystallization proceeds slowly. Therefore, in the polycrystalline semiconductor film 100 obtained by the method according to the present embodiment, the degree of crystallization is high, and dangling bonds and distortion are scarcely left. Therefore, the first lamp annealing ST1 and the second lamp annealing When a TFT is formed from the semiconductor film 100 that has been subjected to the lamp annealing process ST2 repeatedly, the ON current level is high and the variation of the ON current level is small.
An FT can be formed.

[Third Embodiment] In the first embodiment described with reference to FIG. 6, on the semiconductor film 100 formed on the surface of the substrate 50, the first light source 91
Irradiation area L1 of the first lamp light L11 emitted from 0
And the first lamp light L emitted from the second light source 920
In the configuration shown in FIG. 8A, on the semiconductor film 100 formed on the surface of the substrate 50, the irradiation regions L2 of the twelve irradiation regions L2 are arranged without overlapping. The first lamp light L emitted from the first light source 910
The eleventh irradiation area L1 and the irradiation area L2 of the first lamp light L12 emitted from the second light source 920 may be arranged in a partially overlapping state.

Under these conditions, when the irradiation areas L1 and L2 of the lamp light are shifted in the Y direction, the semiconductor film 1
From one point of 00, as shown in FIG.
First, the first lamp light L1 having energy larger than the band gap of the amorphous silicon film (semiconductor film 100) is used.
1 (light / wavelength of energy of 1.6 eV or more is 700 n
m of light or less)
After the application of T1, the first lamp light L11 and the second lamp light L12 (1) having an energy that can be absorbed by the semiconductor film 100 in view of the band gap of the crystalline silicon film (semiconductor film 100). (E.g., light having an energy of 0.1 eV to 1.6 eV / light having a wavelength of 700 nm to 1130 nm), and then undergoes a second lamp annealing process ST2 using the second lamp light L12.

Also in this case, the energy (wavelength) of the lamp light applied to the semiconductor film 100 is changed according to the shift of the band gap of the semiconductor film 100 (silicon film) depending on the degree of crystallization. Therefore, even after crystallization proceeds in the semiconductor film 100, the annealing effect on the semiconductor film 100 is large. Therefore, in the polycrystalline semiconductor film 100 obtained by the method according to this embodiment, the degree of crystallization is high, and dangling bonds and distortion are scarcely left. Therefore, the first lamp annealing process and the second lamp Annealed semiconductor film 10
When a TFT is formed from 0, a TFT having a high on-current level and a small variation in the on-current level can be formed.

Fourth Embodiment In the first embodiment described with reference to FIG. 6, on the semiconductor film 100 formed on the surface of the substrate 50, the first light source 91
Irradiation area L1 of the first lamp light L11 emitted from 0
And the first lamp light L emitted from the second light source 920
Since the 12 irradiation regions L2 are arranged side by side without overlapping, only the first lamp light L11 is irradiated in the first lamp annealing process ST1, and the second lamp annealing process S1 is performed.
At T2, only the second lamp light L12 was irradiated. However, as shown in FIG. 9A, on the semiconductor film 100 formed on the surface of the substrate 50, The first lamp light L emitted from the first light source 910
11 and the first light source 9 in the irradiation region L2 of the first lamp light L12 emitted from the second light source 920.
Irradiation area L of first lamp light L11 emitted from 10
A configuration in which the regions where 1 overlaps may be arranged.

When the irradiation areas L1 and L2 of the lamp light are shifted in the Y direction under the conditions configured as described above, as seen from a certain point of the semiconductor film 100, as shown in FIG. First, an amorphous silicon film (semiconductor film 100)
After the first lamp annealing treatment ST1 in which the first lamp light L11 (light having an energy of 1.6 eV or more / light having a wavelength of 700 nm or less) having an energy larger than the band gap of the first lamp annealing is performed, the crystallinity is increased. In view of the band gap of the silicon film (semiconductor film 100), the second lamp light L12 having energy that can be absorbed by the semiconductor film 100 is used.
(Light / wavelength of energy of 1.1 eV to 1.6 eV is 7
The second lamp annealing process ST2 is performed by light having a wavelength of 00 nm to 1130 nm. When the second lamp annealing process ST2 is performed, the first lamp light L11 is also irradiated.

Also in this case, the energy (wavelength) of the lamp light applied to the semiconductor film 100 is changed according to the shift of the band gap of the semiconductor film 100 (silicon film) depending on the degree of crystallization. Therefore, even after crystallization proceeds in the semiconductor film 100, the annealing effect on the semiconductor film 100 is large. Therefore, in the polycrystalline semiconductor film 100 obtained by the method according to this embodiment, the degree of crystallization is high, and dangling bonds and distortion are scarcely left. Therefore, the first lamp annealing process and the second lamp Annealed semiconductor film 10
When a TFT is formed from 0, a TFT having a high on-current level and a small variation in the on-current level can be formed.

[Other Embodiments] Embodiments 3 and 4
As described in the first embodiment, the first lamp light L11 and the second lamp light L2 are simultaneously irradiated to the same region of the semiconductor film 100 in the first lamp annealing process ST1 as in the second embodiment. And second lamp annealing process ST3
May be applied repeatedly.

In any of the above embodiments, the substrate 50
After forming a base protective film 51 on the surface of the semiconductor film 100,
However, the second lamp light L12 irradiated in the second lamp annealing process ST2 also has an annealing effect on the glass substrate (substrate 50).
Even when the semiconductor film 100 is formed directly on the surface of
The adhesion between the substrate 50 and the semiconductor film 100 can be improved.

Further, in any of the above embodiments, the substrate 5
After the semiconductor film 100 is formed on the surface of the semiconductor film 100, the crystallization process is performed before the gate insulating films 12, 22, and 32 are formed.
If the crystallization step is performed after the formation of the layers 2, 22, and 32, the crystallization step can increase the adhesion between the semiconductor film 100 and the gate insulating films 12, 22, and 32.

[Structure of Electro-Optical Device] FIG. 10 shows an example in which a liquid crystal panel used in an electro-optical device is formed by using the active matrix substrate 200 formed by such a method.
This will be described with reference to FIG.

FIGS. 10 and 11 are a plan view of the liquid crystal panel used in the electro-optical device according to the present embodiment, as viewed from the side of the counter substrate, and a cross-sectional view taken along line HH 'in FIG. is there.

10 and 11, the liquid crystal panel 1 used in the electro-optical device has an active matrix substrate 200 on which pixel electrodes 45 are formed in a matrix.
And an opposing substrate 400 on which an opposing electrode 532 and a light-shielding film 531 are formed, and a liquid crystal 539 as an electro-optical material sealed and sandwiched between these substrates. Active matrix substrate 200 and counter substrate 4
“00” is attached via a predetermined gap by a sealing material 552 including a gap material formed along the outer peripheral edge of the counter substrate 400. Further, a sealing material 5 is provided between the active matrix substrate 200 and the counter substrate 400.
A liquid crystal enclosing area 540 is defined by the partition 52, and a liquid crystal 539 is sealed in the liquid crystal enclosing area 540.
In the liquid crystal sealing region 540, a spacer 53 is provided between the active matrix substrate 200 and the counter substrate 400.
7 may be interposed. As the sealing material 552,
Epoxy resins and various ultraviolet curable resins can be used. In addition, as a gap material mixed in the sealing material 552, an inorganic or organic fiber or sphere having a size of about 2 μm to about 10 μm is used.

The counter substrate 400 is smaller than the active matrix substrate 200,
The peripheral portion of 0 is bonded so as to protrude from the outer peripheral edge of the counter substrate 400. Accordingly, the driving circuits (the scanning line driving circuit 70 and the data line driving circuit 60) and the input / output terminals 545 of the active matrix substrate 200 are in a state of being exposed from the counter substrate 400. Here, since the sealant 552 is partially interrupted, the liquid crystal injection port 541 is formed by the interrupted portion. Therefore, the opposing substrate 4
00 and the active matrix substrate 200 are bonded to each other, and then the inside area of the sealing material 552 is depressurized,
The liquid crystal 539 can be injected under reduced pressure from the liquid crystal injection port 541. After the liquid crystal 539 is sealed, the liquid crystal injection port 541 is sealed with the sealing agent 542.
It should be closed with. The counter substrate 400 has a sealing material 5
A light-shielding film 555 for cutting off the image display area 81 inside the area 52 is also formed. Also, the counter substrate 40
A vertical conductive material 556 for establishing electrical conduction between the active matrix substrate 200 and the counter substrate 400 is formed at any of the 0 corners. Instead of forming the data line driving circuit 60 and the scanning line driving circuit 70 on the active matrix substrate 200, for example, a TAB (tape automated, bonding) substrate on which a driving LSI is mounted is mounted on the active matrix substrate 200. The terminal group formed in the peripheral portion may be electrically and mechanically connected via an anisotropic conductive film. The type of liquid crystal 539 used, that is, TN (twisted nematic) mode, STN (super T
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an N) mode, a D-STN (double-STN) mode, and a normal white mode / a normally black mode. You. Although no color filter is formed on the liquid crystal panel 1 of the present embodiment, an RGB color filter may be formed in a region of the counter substrate 400 facing each pixel electrode 45 together with its protective film. Furthermore, by stacking a number of interference layers having different refractive indexes on the counter substrate 400,
In some cases, a dichroic filter that creates RGB colors by utilizing the interference of light is formed.

[0066]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor film is irradiated with light including the first lamp light having energy larger than the band gap of the amorphous semiconductor film. A first lamp annealing treatment and a second step of irradiating the semiconductor film with light including second lamp light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film. Lamp annealing treatment. That is, the energy (wavelength) of the lamp light applied to the semiconductor film is changed in accordance with the shift of the band gap of the semiconductor film. Therefore,
Even after the crystallization of the semiconductor film has advanced, the annealing effect on the semiconductor film is large. Therefore, the polycrystalline semiconductor film obtained by the method according to the present invention has a high degree of crystallization and almost no dangling bonds or distortion remains. Therefore, when a TFT is formed from the semiconductor film subjected to the first lamp annealing and the second lamp annealing, a TFT having a high on-current level and a small variation in the on-current level can be formed.

[Brief description of the drawings]

FIG. 1 is a graph showing how optical characteristics (the relationship between light energy and absorption coefficient) change as an amorphous silicon film (semiconductor film) crystallizes.

FIG. 2A is a block diagram of an active matrix substrate for an electro-optical device, and FIG. 2B is an equivalent circuit diagram of a CMOS circuit forming a driving circuit thereof.

FIG. 3 is a cross-sectional view of three types of TFTs formed on the active matrix substrate shown in FIG.

FIGS. 4A to 4C are cross-sectional views showing the steps of a method for manufacturing the active matrix substrate shown in FIG.

FIGS. 5A to 5E are cross-sectional views showing the steps performed after the step shown in FIG. 4 in the method for manufacturing the active matrix substrate shown in FIG. 3;

FIGS. 6A and 6B are explanatory views showing a state in which a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 1 of the present invention, and FIGS. FIG. 4 is an explanatory diagram showing a change in lamp light received by a semiconductor film when lamp annealing is performed.

FIGS. 7A and 7B are explanatory views showing a state in which a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 2 of the present invention, and FIGS. FIG. 4 is an explanatory diagram showing a change in lamp light received by a semiconductor film when lamp annealing is performed.

FIGS. 8A and 8B are explanatory views showing a state in which a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 3 of the present invention, and FIGS. FIG. 4 is an explanatory diagram showing a change in lamp light received by a semiconductor film when lamp annealing is performed.

FIGS. 9A and 9B are explanatory diagrams showing a state in which a semiconductor film is irradiated with lamp light in a crystallization step (lamp annealing step) according to Embodiment 4 of the present invention, and FIGS. FIG. 4 is an explanatory diagram showing a change in lamp light received by a semiconductor film when lamp annealing is performed.

FIG. 10 is a plan view of a liquid crystal panel for an active matrix type electro-optical device.

FIG. 11 is a sectional view taken along line HH ′ of FIG. 10;

FIG. 12 is an explanatory diagram of a crystallization step performed by a conventional method for manufacturing an active matrix substrate.

FIG. 13 is a graph showing how optical characteristics change as an amorphous silicon film (semiconductor film) is crystallized.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal panel 10 N-type TFT for drive circuit 20 P-type TFT for drive circuit 12, 22, 32 Gate insulating film 14, 24, 34 Gate electrode 15, 25, 35 Channel region 16, 26, 36 High concentration Source / drain region 17, 27, 37 Low-concentration source / drain region 30 TFT for pixel switching 50 Substrate 51 Underlayer protective film 52 Interlayer insulating film 100 Semiconductor film 200 Active matrix substrate (semiconductor device) 400 Counter substrate 531 Counter electrode 910 1st light source 920 2nd light source L1 Irradiation area of 1st lamp light L2 Irradiation area of 2nd lamp light L11 1st lamp light L12 2nd lamp light ST1 1st lamp annealing process ST2 2nd lamp Annealing treatment

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA25 JA36 JA44 JB44 JB56 KA04 KA07 KA12 KA18 MA04 MA05 MA07 MA12 MA27 MA29 MA35 MA41 NA22 PA13 QA07 QA10 5F052 AA24 CA01 CA03 DA02 DB03 EA11 HA01 JA04 5F110 AA03 DD02 EE04 EE44 FF02 FF30 GG02 GG13 GG25 GG43 GG45 GG47 HJ01 HJ04 HJ13 HJ23 HM15 PP02 PP13 PP29

Claims (14)

[Claims] 1. A semiconductor comprising at least a film forming step of forming a semiconductor film on a substrate, and a crystallization step of performing lamp annealing on the semiconductor film formed by the film forming step to crystallize the semiconductor film. In the method for manufacturing a device, in the crystallization step, a first lamp annealing process of irradiating the semiconductor film with light including a first lamp light having an energy larger than a band gap of the amorphous semiconductor film;
A second lamp annealing process of irradiating the semiconductor film with light including a second lamp light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film. A method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein in the crystallization step, the first lamp annealing and the second lamp annealing are performed alternately. 3. The method according to claim 1, wherein when the process shifts from the first lamp annealing process to the second lamp annealing process, both the first lamp light and the second lamp light are included. A method for manufacturing a semiconductor device, comprising irradiating a semiconductor film with light. 4. The method according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein in the second lamp annealing treatment, only the second lamp light is irradiated. 5. The method according to claim 1, wherein
In the second lamp annealing process, a method of manufacturing a semiconductor device, comprising irradiating light including the first lamp light in addition to the second lamp light. 6. The method according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the first lamp light is light having an energy of 1.6 eV or more. 7. The light according to claim 6, wherein the first lamp light is emitted from any one of an incandescent lamp, a halogen lamp, a fluorescent lamp, a high-pressure mercury lamp, a metal halide lamp, a high-pressure sodium lamp, and an ultraviolet lamp. A method for manufacturing a semiconductor device. 8. The method according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the second lamp light is light having an energy of 1.1 eV to 1.6 eV. 9. The method according to claim 8, wherein the second lamp light is light emitted from an infrared lamp. 10. A method for manufacturing a semiconductor device according to claim 1, wherein a thin film transistor is formed from the semiconductor film subjected to the first lamp annealing and the second lamp annealing. . 11. An annealing apparatus for performing lamp annealing on a semiconductor film formed on a substrate, wherein the first light source emits first lamp light having energy larger than the band gap of the amorphous semiconductor film. And a second light source that emits a second lamp light having an energy larger than the band gap of the single crystal semiconductor film and smaller than the band gap of the amorphous semiconductor film. Annealing equipment. 12. The annealing apparatus according to claim 11, wherein the annealing apparatus is configured to irradiate the first lamp light and the second lamp light alternately. 13. The method according to claim 11, wherein the first light source is any one of an incandescent lamp, a halogen lamp, a fluorescent lamp, a high-pressure mercury lamp, a metal halide lamp, a high-pressure sodium lamp, and an ultraviolet lamp. Annealing equipment. 14. The annealing apparatus according to claim 11, wherein the second light source is an infrared lamp.