JP2000252202A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve overlay accuracy of a circuit pattern by sharply reducing friction of a stage drive system generated at acceleration/deceleration of a stage. SOLUTION: When a circuit pattern is directly drawn on a semiconductor wafer 9 with an electron beam lithography equipment, a dummy pattern is also drawn on a scribe area SA of the semiconductor wafer 9. The dummy pattern is a through hole, etc., and drawn with light exposure of an extent where resist is not exposed. Since the dummy pattern is not patterned in the scribe area SA, high-speed movement of a stage on which the semiconductor wafer 9 is mounted is prevented without having a bad influence upon a semiconductor chip region CR, so that friction of a stage drive part driving the stage is sharply reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure technique using an electron beam, and more particularly to a technique effective when applied to direct writing of an electron beam.

[0002]

2. Description of the Related Art In recent years, a direct drawing technique for drawing a circuit pattern directly on a semiconductor wafer has become effective as a technique to supplement optical lithography approaching the resolution limit.
As an apparatus used for this direct writing technique, there is an electron beam apparatus for direct writing on a wafer.

This electron beam apparatus for direct writing on a wafer is
CAD (Computer Aided Design)
The circuit pattern of the semiconductor integrated circuit device prepared in n) is directly drawn on a semiconductor wafer by using an electron beam.

According to studies made by the present inventors, in an electron beam apparatus for direct writing on a wafer, an electron beam is irradiated onto a semiconductor wafer, and a stage on which the semiconductor wafer is mounted in accordance with a circuit pattern to be drawn. Are drawn two-dimensionally to directly draw on a semiconductor wafer.

In the electron beam apparatus for directly writing a wafer, there is a so-called stage moving variable speed drawing as a technique for shortening the drawing time. In this stage movement variable speed writing, control is performed to reduce the stage movement speed for drawing data having a complicated circuit pattern and to increase the stage movement speed for drawing data having a simple circuit pattern.

As an example describing this type of drawing apparatus in detail, see, for example, "Masashi Oshima (ed.)," Published by the Industrial Research Institute on November 22, 1996,
Test Equipment Guidebook <1997 Version> ”P83-P8
This document describes an electron beam drawing technique in an electron beam exposure apparatus.

[0007]

However, it has been found by the present inventors that the following problems occur in the above-described circuit pattern drawing technique.

That is, in a scribing area for dividing a semiconductor wafer into individual semiconductor chips, the moving speed of the stage is set to the highest speed because no circuit pattern is formed.

Therefore, the speed of the stage moving in the scribe area and the speed of the stage moving in the semiconductor chip area where the circuit pattern is formed are significantly different, so that the friction of the stage drive system due to the acceleration / deceleration of the stage is reduced. This causes a problem that the circuit pattern overlay accuracy deteriorates.

An object of the present invention is to significantly reduce the friction of a stage drive system generated when the stage is accelerated or decelerated,
It is an object of the present invention to provide a method for manufacturing a semiconductor device which can improve the overlay accuracy of circuit patterns.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor device of the present invention, when a circuit pattern is directly drawn on a semiconductor chip region formed on a semiconductor wafer by an electron beam, the semiconductor chip region is divided into individual semiconductor chips. A dummy pattern is drawn with an exposure amount that does not expose the resist to a certain scribe area.

Further, a method of manufacturing a semiconductor device according to the present invention
The dummy pattern is drawn only in a scribe area orthogonal to the direction in which the semiconductor wafer moves when the circuit pattern is drawn.

Further, in the method of manufacturing a semiconductor device according to the present invention, the dummy pattern drawn in the scribe area is formed of a through hole.

As described above, the high-speed movement of the stage on which the semiconductor wafer is mounted can be prevented by drawing the dummy pattern also in the scribe area of the semiconductor wafer, so that the friction of the stage drive section for driving the stage is greatly reduced. It is possible to reduce the number and perform high-accuracy overlay drawing.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an electron beam writing apparatus according to one embodiment of the present invention. FIG. 2A is an explanatory diagram of a circuit pattern drawn on a semiconductor wafer according to one embodiment of the present invention. FIG. 3B is an explanatory diagram of a moving speed of the stage of the electron beam writing apparatus, FIG.
FIG. 4 is a flowchart showing a circuit pattern drawing process by the electron beam drawing apparatus according to one embodiment of the present invention.

In the present embodiment, the electron beam drawing apparatus 1 draws a circuit pattern directly on a semiconductor wafer.
The electron beam drawing apparatus 1 includes a control computer 2, an electron optical system control unit 3, a drawing control unit 4, a stage control unit 5, a stage driving unit 6, a stage 7, and a drawing unit body 8.

The control computer 2 controls the high-speed transfer of the drawing data transferred from the CAD and controls the electron beam drawing apparatus 1. The electron optical system control unit 3 adjusts the electron beam by electrostatic deflection or electromagnetic deflection.

The drawing control unit 4 divides the drawing data transferred via the control computer 2 into shot data, performs inversion, scaling, and sorting as needed, and writes the processed drawing data and the stage 7 And ON / OFF control of the electron beam based on the position information.

The stage controller 5 controls the movement of the stage 7 using, for example, a laser interferometer.
The stage driving section 6 drives the stage 7 two-dimensionally (X direction, Y direction) based on a control signal from the stage control section 5. On the stage 7, a semiconductor wafer 9 on which a circuit pattern is drawn is placed.

Next, a circuit pattern drawn on the semiconductor wafer 9 will be described with reference to FIG.

Semiconductor wafer 9 serving as a substrate for semiconductor elements
Is a thin plate of single crystal such as silicon. This semiconductor wafer 9 has a semiconductor chip region CR
And a scribe area SA are formed.

The semiconductor chip region CR is a region where an integrated circuit is formed, and the scribe area SA is a region that divides the semiconductor chip region CR into individual semiconductor chips. The scribe area SA includes the semiconductor wafer 9
Are formed in a lattice pattern in the plane direction of the semiconductor chip, and a semiconductor chip region CR is formed surrounded by the scribe area SA.

In the semiconductor chip area CR, a circuit pattern is drawn by the electron beam drawing apparatus 1 to form an integrated circuit, and the scribe area SA is cut into a dice pattern by, for example, a dicing apparatus to form individual semiconductors. Divided as chips.

The circuit pattern is drawn from the lower left portion of the semiconductor chip region CH of the semiconductor wafer 9 to the semiconductor chip region CR located at the uppermost portion of the semiconductor wafer 9 in FIG. The area to be drawn at this time has a drawing width BH.

Thereafter, a circuit pattern is drawn from the lowermost semiconductor chip region CR to the uppermost semiconductor chip region CR of the semiconductor wafer 9 in the region immediately to the right of the region where the circuit pattern has been previously drawn. By repeating these processes, all the semiconductor chip regions CR
The circuit pattern is drawn by the electron beam drawing apparatus 1.

Next, the manufacturing process of the semiconductor device will be described with reference to the flowchart of FIG.

First, a resist is applied to the surface of the semiconductor wafer 9 by a resist coating device (step S10).
1). The semiconductor wafer 9 having a surface coated with a resist,
A circuit pattern is drawn by the electron beam drawing apparatus 1 (step S102).

Semiconductor wafer 9 on which circuit pattern is drawn
After the development of the resist by the developing device (Step S103), the portion not covered with the resist is removed by the etching device (Step S104).
A desired circuit pattern is formed by repeating the processing of steps S101 to S104.

FIGS. 1 and 2 (a) show a drawing technique of a circuit pattern by the electron beam drawing apparatus 1. FIG.
This will be described with reference to (b) and the flowchart of FIG.

First, the drawing data created by the designer is transferred from the CAD or the like to the electron beam drawing apparatus 1 (step S201). The semiconductor wafer 9 coated with the resist in the process of step S101 (FIG. 3) is placed on the stage 7 of the electron beam drawing apparatus 1 (step S202), and drawing of a circuit pattern on the semiconductor wafer 9 by the electron beam is started. Is performed (step S203).

In the second and subsequent circuit pattern writing, it is necessary to detect an alignment mark formed at the time of writing the first circuit pattern.

Here, a method of detecting an alignment mark indicating the position of a base pattern will be described.

First, the alignment mark formed on the semiconductor wafer 9 is scanned with an electron beam to detect a signal of the alignment mark.

The drawing control unit 4 processes the detected signal to obtain the mark coordinates, and outputs the result to the control computer 2. The control computer 2 calculates a correction coefficient based on all mark coordinate data and performs a correction operation. This matching coefficient is a coefficient for correcting the amount of deflection of the electron beam, and the electron beam is deflected according to the underlying pattern.

In the process of step S203, drawing on the semiconductor wafer 9 is performed based on the drawing data transferred from the CAD. The drawing data is designed so that a dummy pattern is arranged in a scribe area SA (area indicated by hatching) in the X direction.

The drawing of a circuit pattern by the electron beam drawing apparatus 1 is performed by first setting the semiconductor chip area C
Starting from the lower left portion of R, the stage 7 is sequentially moved in the Y direction, and a circuit pattern of the scribe area SA is drawn on the semiconductor chip region CR and the scribe area SA, respectively. Also,
At this time, the range in the X direction to be drawn is the drawing width BH as described above.

After drawing to the uppermost semiconductor chip region CR, the stage 7 is moved in the X direction and the Y direction, and at the lowermost portion of the semiconductor chip region CR, to the right of the previously drawn drawing width BH. The circuit pattern is drawn again from the area. By repeating these,
A circuit pattern is drawn in all the semiconductor chip regions CR and the scribe area SA in the X direction.

In drawing a circuit pattern, the X
The scribe area SA in the direction, that is, the dummy pattern drawn in the area in the direction orthogonal to the direction in which the stage 7 moves at the time of pattern drawing is data-designed so that a low-dose dummy pattern is arranged.

The low dose is an exposure amount that does not expose the resist. Since the dummy pattern is not patterned in the scribe area SA by drawing the dummy pattern with the low dose, there is no influence on the actual device formed in the semiconductor chip region CH.

Further, by drawing the dummy pattern in the scribe area SA, it is possible to prevent the stage 7 from suddenly moving, so that the friction of the stage driving unit 6 for driving the stage 7 can be greatly reduced.

The moving speed of the stage 7 in the scribe area SA is such that the stage driver 6 is not affected by friction, for example, as shown in FIG. By setting the speed slightly higher than the minimum moving speed of the stage 7, the friction of the stage driving unit 6 can be effectively reduced without drastically decreasing the throughput.

In FIG. 2B, the vertical axis corresponds to FIG.
(A) Semiconductor chip area CR, scribe area S
The horizontal axis indicates a change in the moving speed of the stage 7. Further, in FIG. 2B, the moving speed of the stage 7 in the semiconductor chip area CR is shown uniformly, but actually, the moving speed of the stage 7 changes due to the density of the circuit pattern in the semiconductor chip area CR. ing.

Further, the dummy pattern drawn on the scribe area SA of the semiconductor wafer 9 is a pattern in which through holes are arranged at regular intervals. The moving speed of the stage 7 can be effectively controlled with simple drawing data.

For example, if the moving speed of the scribe area SA on the stage 7 is to be increased, the interval between the through holes is increased, and if the moving speed of the stage 7 is to be decreased, the interval between the through holes is reduced.

Thus, in the present embodiment, it is possible to prevent a rapid change in the speed of the stage 7 in the scribe area SA, so that the friction of the stage drive unit 6 can be significantly reduced, and highly accurate overlay drawing can be realized. Can be.

In the present embodiment, the moving speed of the stage 7 in the scribe area SA is slightly faster than the lowest moving speed of the stage 7 when drawing the semiconductor chip area CH.
The moving speed of the stage 7 in A may be, for example, about the same as the lowest moving speed of the stage 7 when drawing the semiconductor chip area CH.

As a result, the acceleration and deceleration of the stage 7 in the scribe area SA and the semiconductor chip region CR can be made much smaller, so that the friction of the stage drive unit 6 can be reduced more effectively.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, according to the above embodiment, a low-dose dummy pattern is arranged in a scribe area in a direction orthogonal to the direction in which the stage moves at the time of writing. The electron beam lithography system controls the moving speed of the stage so that it becomes the same as or slightly slower than the lowest moving speed of the stage when drawing the semiconductor chip area when the area is not drawn (scribe area). You may.

This also effectively reduces the friction of the stage driving section, and realizes highly accurate overlay drawing.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, when a circuit pattern is directly drawn on a semiconductor wafer by an electron beam, a dummy pattern is drawn on the scribe area with an exposure amount that does not expose the resist to the semiconductor wafer, thereby mounting the semiconductor wafer. Since the stage to be placed is prevented from moving at high speed in the scribe area, the friction of the stage driving unit that drives the stage can be significantly reduced, and highly accurate overlay drawing can be performed.

(2) Further, according to the present invention, the moving speed of the stage can be effectively controlled with simple drawing data by making the dummy pattern drawn in the scribe area a through hole.

(3) Further, in the present invention, the reliability of the semiconductor device can be greatly improved by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a block diagram of an electron beam writing apparatus according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram of a circuit pattern drawn on a semiconductor wafer according to an embodiment of the present invention, and FIG.
FIG. 4 is an explanatory diagram of a moving speed on a stage of the electron beam writing apparatus.

FIG. 3 is a flowchart showing the manufacture of the semiconductor device according to one embodiment of the present invention.

FIG. 4 is a flowchart showing a circuit pattern drawing process by the electron beam drawing apparatus according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electron beam drawing apparatus 2 Control computer 3 Electro-optical system control part 4 Drawing control part 5 Stage control part 6 Stage drive part 7 Stage 8 Drawing part main body 9 Semiconductor wafer CR Semiconductor chip area SA Scribe area

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideki Sekine 3-3-2 Fujibashi, Ome-shi, Tokyo Within Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Hajime Hayakawa 6-16, Shinmachi, Ome-shi, Tokyo 3 shares Hitachi, Ltd. Device Development Center (72) Inventor ▲ Takashi Manabu 3-3-2 Fujibashi, Ome-shi, Tokyo F-term (reference) 5F046 AA28 BA07 DA02 in Hitachi Tokyo Electronics Co., Ltd.

Claims (3)

[Claims] When a circuit pattern is directly drawn on a semiconductor chip region formed on a semiconductor wafer by an electron beam, a resist is also exposed to a scribe area which is a region for dividing the semiconductor chip region into individual semiconductor chips. A method of manufacturing a semiconductor device, wherein a dummy pattern is drawn with an exposure amount that is not performed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said dummy pattern is drawn only in a scribe area perpendicular to a direction in which said semiconductor wafer moves when a circuit pattern is drawn. Semiconductor device manufacturing method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein said dummy pattern is a through hole.