JP2000251474A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a sufficient data holding time by shortening a period in which a bit line BL and a reference bit line ZBL are kept at a L level in a semiconductor memory provided with a memory cell storing data. SOLUTION: This device is provided with a memory cell outputting a data signal to a bit line (BL or ZBL) by activating a word line (WL) while specifying a row address (ZRAS). Data outputted to BL or ZBL is amplified by a sense amplifier. A signal amplified by a sense amplifier is latched by a latch circuit (SBL and ZSBL). After latch of data the sense amplifier and the latch circuit are cut off at a gate A, the sense amplifier is made a non-operation state, also, BL and ZBL are made a reference potential VBL. The latch circuit continues latch of data until a next time row address is specified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory cell for storing data.

[0002]

2. Description of the Related Art Conventionally, for example, a DRAM is known as a semiconductor memory device having a memory cell. FIG. 5 shows a partial circuit diagram of a conventional DRAM. As shown in FIG.
A conventional DRAM includes a bit line BL and a reference bit line ZBL. Each of the bit line BL and the reference bit line ZBL has a plurality of memory cells 1
0 is connected.

A memory cell 10 includes a capacitor 12 arranged in series between a power supply potential Vcp and a bit line BL or between a power supply potential Vcp and a reference bit line ZBLt.
And a transistor 14. The gate terminal of the transistor 14 is connected to the word line WL. The memory cell 10 is in a state where data can be read and written by activating the word line WL.

[0006] The bit line BL is connected to an input / output line (I / O line) 18 via an input / output gate (I / O gate) 16. On the other hand, the reference bit line ZBL
It is connected to the ZI / O line 20 via the O gate 16. Also, the bit line BL and the reference bit line ZBL
A sense amplifier 22 is connected between the first and second amplifiers together with an equalizer (not shown).

The equalizer is a circuit for selectively realizing a state in which the potential of the bit line BL and the potential of the reference bit line ZBL are both equal to the reference potential _VBL and a state in which different potentials can be introduced to both. Note that the reference potential V _BL is a potential corresponding to an intermediate value between the H potential and the L potential.

The sense amplifier 22 has an S2P signal and an S2P signal.
2N signal is supplied. S2P signal is maintained at the reference potential V _BL upon deactivation of the sense amplifier 22 is a signal which becomes H potential when the activity of the sense amplifier 22. on the other hand,
S2N signal is maintained at the reference potential V _BL upon deactivation of the sense amplifier 22 is a signal which becomes L potential when the activity of the sense amplifier 22. When the sense amplifier 22 is activated, the bit line BL and the reference bit line ZBL are activated.
Can be amplified.

Hereinafter, the operation of the conventional DRAM will be described. Until data writing or reading is requested from the DRAM, the bit line B
L potential, and the potential of the reference bit line ZBL are both maintained at the reference potential V _BL. When, for example, data reading is requested from the DRAM, the row address of the memory cell 10 from which data is read is specified.
As a result, the word line corresponding to the designated row address is activated, and all the memory cells conducting to the word line are activated.

Before the memory cell is activated, the equalizer is deactivated so that BL and ZBL are deactivated.
A state that can lead to a different potential is formed. In this state, for example, the bit line B
If H signal is outputted to the L (ZBL remains the reference potential V _BL) potential difference ΔV is generated in the BL and ZBL.

After the equalizer is deactivated, the S2P signal and the S2N signal change to a potential for activating the sense amplifier 22. When the sense amplifier 22 is activated under the condition that the potential difference ΔV (BL is high potential) is generated between BL and ZBL, the potential of BL rises to H level and the potential of ZBL falls to L level. Descend. These potentials are supplied to the I / O line 1 via the I / O gate 16.
8 and ZI / O line 20. In this case, I /
A potential difference corresponding to the signal output from the memory cell 10 appears on the O line 18 and the ZI / O line 20.

In the conventional DRAM, the L signal is output to the I / O line 18 and the ZI / O line 20 from the memory cell 10 to the bit line BL, or the memory cell 1
Even when signals output from 0 are guided to the reference bit line ZBL, a potential difference corresponding to those output signals appears. Therefore, according to the conventional DRAM, the data stored in the memory cell 10 can be appropriately read.

[0011]

In a conventional DRAM, the potential of a bit line BL and a reference bit line Z
The potential of BL is maintained at the L or H level for a long time when, for example, a known page mode is used. Bit line BL and reference bit line ZBL
The plurality of memory cells 10 are connected as described above. Therefore, the L-level potential guided to BL and ZBL is supplied to the memory cells 10 in the active state and also to the memory cells 10 in the inactive state.

When an L-level potential is supplied from BL or ZBL to an inactive memory cell 10 storing H-level data, the memory cell 10 is supplied with carriers by a subthreshold leak of transistor 14. An electron flows in. Therefore, H-level data stored in the inactive memory cell 10 changes toward L-level data after the BL or ZBL connected to that cell goes to L-level. Therefore, the data retention time of the memory cell 10 is greatly affected by the amount of charge flowing into the cell due to the subthreshold leak.

The current value due to the threshold leak is suppressed as the substrate potential V _BB (negative potential) decreases. However, when the substrate potential V _BB is lowered, the amount of junction leakage of the transistor 14 increases, and the data retention time is shortened.
For this reason, it is difficult to improve the data retention time only by adjusting the substrate potential V _BB .

The present invention has been made to solve the above-described problem, and suppresses the influence of sub-threshold leak by shortening the period in which bit line BL and reference bit line ZBL are maintained at L level. It is another object of the present invention to provide a semiconductor memory device which secures a sufficient data retention time.

[0015]

According to the first aspect of the present invention,
A semiconductor memory device, comprising: a memory cell that outputs a data signal to a bit line when a word line is activated in accordance with designation of a row address; and a sense amplifier that amplifies data output to the bit line. An amplifier, a latch circuit for latching a signal amplified by the sense amplifier, and a gate disposed between the sense amplifier and the latch circuit, wherein after the latch circuit latches data, the gate is The state is cut off, the sense amplifier is deactivated, the potential of the bit line is set to the reference potential, and the latch circuit continues to latch data until the next row address is specified. It is characterized by the following.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, when a row address designated for reading data is the same as a previously designated row address, The latch circuit outputs data latched in the latch circuit.

The third aspect of the present invention is the first or second aspect.
In the semiconductor memory device according to the above, after the data is latched by the latch circuit, the word line is changed from an active state to an inactive state, and at the time when data is to be written to the memory cell, the word line is The active state is activated again, and the sense amplifier is activated again.

The invention according to claim 4 is the semiconductor memory device according to claim 3, wherein the word line is activated when data of the bit line is amplified to a value that can be latched by the latch circuit. From an inactive state.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the third aspect, the word line has the data of the bit line amplified to a value capable of completing the rewriting of data to the memory cell. At this point, the active state is changed from the active state to the inactive state, and during the data reading process, the reactivation of the word line and the reactivation of the sense amplifier are prohibited until a row address is newly specified. It is a feature.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals, and redundant description will be omitted.

Embodiment 1 FIG. 1 is a circuit diagram of a main part of the semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device of the present embodiment has a bit line BL
And a reference bit line ZBL. A plurality of memory cells 10 are connected to each of the bit line BL and the reference bit line ZBL.

The memory cell 10 includes a capacitor 12 arranged in series between the power supply potential Vcp and the bit line BL or between the power supply potential Vcp and the reference bit line ZBLt.
And a transistor 14. The gate terminal of the transistor 14 is connected to the word line WL. The memory cell 10 is in a state where data can be read and written by activating the word line WL.

The bit line BL is connected to a sub bit line SBL via a gate A24. Sub bit line SB
L is connected to an I / O line 18 via an I / O gate 16. On the other hand, the reference bit line ZBL is connected to the sub-reference bit line ZSBL via the gate A24. Sub-reference bit line ZSBL
Are connected to a ZI / O line 20 via an I / O gate 16.

Bit line BL and reference bit line ZB
A sense amplifier 22 is connected between the L and L together with an equalizer (not shown). On the other hand, the sub bit line SBL
A latch circuit 26 is connected between the sub-reference bit line ZSBL and a sub-equalizer (not shown).

The equalizer is a circuit for selectively realizing a state in which the potential of the bit line BL and the potential of the reference bit line ZBL are both at the reference potential _VBL and a state in which different potentials can be introduced to both. The sub-equalizer is a circuit that selectively realizes a state in which the potential of the sub-bit line SBL and the potential of the sub-reference bit line SBL are both equal to the reference potential _VBL and a state in which different potentials can be introduced to both.

The sense amplifier 22 includes two P-ch transistors 28 and 30 and two N-ch transistors 3
2 and 34. The P-ch transistor 28 and the N-ch transistor 32 are connected in series.
On the other hand, the P-ch transistor 30 and the N-ch transistor 34 are connected in series.

The gate terminal of the P-ch transistor 28,
And the gate terminal of the N-ch transistor 32 is P-
The common terminal of the channel transistor 30 and the N-channel transistor 34 is connected to ZBL. Also, P-ch
The gate terminal of the transistor 30 and the gate terminal of the N-ch transistor 34
And the common terminal of the N-ch transistor 32 and BL.

Further, P-ch transistors 28, 30,
And the N-ch transistors 32 and 34 are supplied with the S2P signal or the S2N signal, respectively. S2P
The signal is a signal that is set to the reference potential _VBL when the sense amplifier 22 is deactivated, and is set to the H potential when the sense amplifier 22 is activated. On the other hand, S2N signal is the reference potential V _BL when the sense amplifier 22 to the inactive state, a signal that is L potential when the sense amplifier 22 to the active state.

When the sense amplifier 22 is maintained in the inactive state, the bit line BL and the reference bit line Z
Even if a potential difference occurs between BL and BL, those potentials are stably maintained at reference potential _VBL . Also, the sense amplifier 22
In the activated state, when a potential difference occurs between the bit line BL and the reference bit line ZBL, the potential difference can be amplified.

The latch circuit 26 includes two P-ch transistors 36 and 38 and two N-ch transistors 40 and 42, like the sense amplifier 22. These transistors are connected as in the case of the sense amplifier 22. In the latch circuit 26, P-ch
Transistors 36 and 38 and N-ch transistors 32 and 34 have an SS2P signal and an SS2N signal, respectively.
A signal is being supplied. The SS2P signal is output from the latch circuit 2
6 is set to the reference potential _VBL when the latch circuit 6 is set to the non-latched state, and is set to the H potential when the latch circuit 26 is set to the latched state. On the other hand, SS2N signal is the reference potential V _BL when the latch circuit 26 inactive, the latch circuit 26
Is a signal that is set to the L potential when the latched state is set.

The latch circuit 26, when it is maintained in a non-latching state, the potential of the sub-bit line SBL, and the potential of the sub reference bit line ZSBL, maintaining the stable reference potential V _BL. In addition, latch circuit 26 can be stably latched by being brought into a latch state under a situation where a predetermined potential difference is introduced between sub bit line SBL and sub reference bit line ZSBL.

Next, the operation of the semiconductor memory device of this embodiment will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device of the present embodiment. FIG. 2A shows a waveform of a row address signal (ZRAS) input from outside the device when writing or reading of data is requested to the semiconductor memory device. FIG. 2B shows a waveform of an equalizer activation signal (BLEQ) arranged between BL and ZBL. When the BLEQ is at the H level,
The potential of L and the potential of ZBL are equalized. Fig. 2 (J)
Shows the waveform of the activation signal (SBLEQ) of the sub-equalizer arranged between SBL and ZSBL. The sub-equalizer equalizes the potential of SBL and the potential of ZSBL when SBLEQ is at the H level.

When data read / write is requested from the semiconductor memory device, first, the ZRAS signal changes from H to L to specify the row address of the memory cell 10 to be processed (FIG. 2A). . When the ZRAS signal changes to the L signal, BLEQ changes from H to L and the equalizer is deactivated (FIG. 2B), and SBLEQ changes from L to H and the sub equalizer is activated (FIG. 2B). FIG.
(J)).

When the equalizer is deactivated as described above, a state is formed in which a potential difference can be induced between the bit line BL and the reference bit line ZBL. On the other hand, when the sub-equalizer is activated as described above, the sub-bit line S
Potentials of and sub reference bit line ZSBL of BL are reset together with the reference potential V _BL (FIG. 2
(K) and (L)).

When a predetermined delay time elapses after the ZRAS signal changes to L level, the potential of the word line WL corresponding to the designated row address changes from L to H (FIG. 2).
(C)). As a result, all the memory cells 10 connected to the word line WL are activated.

As described above, the semiconductor memory device has a set of B
One sense amplifier 22 is provided corresponding to L and ZBL. That is, in the semiconductor memory device, one sense amplifier 22 is shared by BL and ZBL. The semiconductor memory device includes a memory cell 10 connected to one of two signal lines (BL and ZBL) sharing a single sense amplifier 22, and a memory cell 10 connected to the other signal line. Are provided so as not to be activated simultaneously. Therefore, a data signal is not output to two signal lines (BL and ZBL) sharing the sense amplifier 22 at the same time.

Hereinafter, a case will be described in which the word line WL shown on the leftmost side in FIG. 1 is activated, and as a result, an H level data signal is output from the memory cell 10 to the shown BL, as an example. The operation of the storage device will be described.

When the word line WL is activated, the equalizer is inactive. Therefore, WL from the memory cell 10 to BL the H level signal is outputted by being activated, becomes higher than the potential of the BL is the reference potential V _BL, the potential difference between the BL and ZBL appear.

After the word line WL is activated, the S2P signal and S2N signal supplied to the sense amplifier 22 are
The potential is gradually changed to the H-level potential or the L-level potential, respectively (FIGS. 2F and 2G). As a result, the sense amplifier 22 is activated, and the potential of BL is amplified to H level and the potential of ZBL is amplified to L level, respectively (FIGS. 2D and 2E).

FIG. 2H shows a waveform of the ZCE signal which changes from H to L when the potential difference between BL and ZBL is properly amplified. More specifically, the ZCE signal changes from BL and ZBL to SBL and ZBL after WL is activated.
This signal changes from H to L when a state in which a potential difference signal can be supplied to the SBL is formed.

When the ZCE signal changes from H to L, a pulse signal is supplied to the gate A24 after a predetermined delay time (FIG. 2 (I)). The gate A24 becomes conductive only while the pulse signal is supplied, and supplies the potential of BL and the potential of ZBL to SBL and ZSBL.

SBLEQ changes from H to L in synchronization with the timing when the gate A24 changes from the non-conductive state to the conductive state. As a result, the sub equalizer is deactivated,
The potential of SBL and the potential of ZSBL are BL
Potential (H level) and ZBL potential (L level)
Begin to change towards.

After SBLEQ changes from H to L, the S2P signal and S2N signal supplied to latch circuit 26 are gradually changed to H level potential or L level potential, respectively (FIG. 2 (M) and (M)). N)). as a result,
The latch circuit 26 enters the latch state, and the potential of SBL becomes H
Level, and the potential of ZSBL is latched at L level, respectively (FIGS. 2K and 2L).

In the semiconductor memory device of this embodiment, when data is latched by the latch circuit 26 as described above, the BLEQ
Signal is changed from L to H to the equalizer and the operating state with (FIG. 2 (B)), both S2P signal and S2N signal and reference potential V _BL (FIG. 2 (F) and (G)). At this point, the gate A24 is already cut off, the equalizer by the above process is again actuated state, the potential of the potential and ZBL of BL are both controlled to the reference potential V _BL (FIG. 2 ( D) and (E)). Thereafter, the potential of BL and the potential of ZBL are rewritten (rewritten) in the memory cell 10.
It is maintained at the reference potential V _BL up should do the time.

As described above, according to the semiconductor memory device of the present embodiment, after the ZRAS signal changes from H to L, desired data is stored in the latch circuit 26, and BL and ZB are stored.
The potential of L can be used as the reference potential _VBL . That is, according to the semiconductor memory device of the present embodiment, it is possible to prevent the L-level potential from being supplied from the BL or ZBL to the inactive memory cell 10 for a long time. Therefore, according to the semiconductor memory device of the present embodiment, it is possible to secure a sufficiently long data holding time even when operating in a mode in which the ZRAS signal is maintained at the L level for a long time, such as the page mode. it can.

When data reading is requested from the semiconductor memory device, the I / O gate 16 is turned on at a predetermined timing, and the data latched by the latch circuit 26 as described above is transferred to the I / O line. 18 and ZI / O line 2
Output to 0. In the present embodiment, the latch circuit 26
Is maintained after the data output is completed.

The I / O lines 18 and Z
After the data is output to the I / O line 20, when the ZRAS signal changes from the L level to the H level (FIG. 2A), B
LEQ becomes L again, and the equalizer is deactivated (FIG. 2B). Next, a pulse signal is again supplied to the gate A24 (FIG. 2 (I)), and the S2P
The signal and the S2N signal are changed to H level and L level, respectively. As a result, the potential of BL is set to the same H level as the potential of SBL, and the potential of ZBL is set to ZSB.
The potential changes to the same L level as the L potential (FIG. 2).
(D) and (E)).

When the data of latch circuit 26 is transmitted to BL and ZBL as described above, word line WL is maintained in the active state. Therefore, the data of BL or ZBL is rewritten to the memory cell 10 connected to the active WL. According to the above processing, the same data as the read data can be rewritten to the memory cell 10 from which the data has been read.

When data writing is requested to the semiconductor memory device, after a potential difference between BL and ZBL is latched by latch circuit 26, I / O is performed at a predetermined timing.
Gate 16 is rendered conductive, and write data is supplied from I / O line 18 and ZI / O line 20 to SBL and ZSBL. The waveforms indicated by broken lines in FIGS. 2K and 2L indicate a state in which the potentials of SBL and ZSBL have been inverted by the data writing process.

When data writing is requested to the semiconductor memory device, I / O line 18 and ZI
After the write data is supplied from the / O line 20, the latch circuit 26 latches the write data. Z
After the RAS signal changes from L to H, the write data latched in the latch circuit 26 is written to the memory cell 10 by the same processing as when reading data. The latch state of the latch circuit 26 is maintained even after the data writing is completed.

The data latched in the latch circuit 26 after reading or writing of data is completed is latched in the next and subsequent processing cycles until the sub-equalizer is activated. The semiconductor memory device of the present embodiment can use the data thus latched by the latch circuit 26 as a cache.

More specifically, the semiconductor memory device according to the present embodiment is arranged such that the row address accessed for reading data in a certain processing cycle is the same as the row address accessed in the previous processing cycle. Omits the process of reading data from the memory cell 10 and uses the data latched in the latch circuit 26 as read data. The data latched by the latch circuit 26 is the same as the data of the memory cell 10 at the row address accessed in the previous processing cycle. Therefore, by using the latch data as read data, it is possible to perform appropriate data read processing at high speed.

As described above, according to the semiconductor memory device of the present embodiment, it is possible to secure a sufficient data holding time regardless of the operation mode of the device, and to use the latch data as a cache to perform data processing. Higher speed can be realized.

In the above embodiment, the bit line BL and the reference bit line ZBL are provided in the first embodiment.
This corresponds to the “bit line” described.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG. The semiconductor memory device of the present embodiment has the same configuration as the device of the first embodiment, that is, the configuration shown in FIG. 1 around the memory cell 10 and the sense amplifier 22.

FIG. 3 is a timing chart for explaining the operation of the semiconductor memory device of this embodiment. The semiconductor memory device of the present embodiment is characterized in that the control of the word line WL (FIG. 3B) is different from that of the first embodiment.

The semiconductor memory device of the present embodiment outputs data of the memory cell 10 to the BL or ZBL by operating in the same manner as the device of the first embodiment after a request to read or write data is issued (FIG. 3). (D)). And BL and ZB
When the potential difference from L is amplified to a value that can be latched, the gate A24 opens at that point and data is latched in the latch circuit 26 (FIGS. 3K and 3L).

In the semiconductor memory device of this embodiment,
After the data is latched in the latch circuit 26, the potentials of BL and ZBL are changed to the reference potential V, as in the first embodiment.
_It is controlled to _BL (FIGS. _3D and _3E ). Therefore,
According to the semiconductor memory device of the present embodiment, the first embodiment
As in the device described above, a sufficiently long data retention time can be secured.

Further, in the semiconductor memory device of this embodiment, after the data is latched by the latch circuit 26, the potential of the word line WL is switched from H to L (FIG. 3).
(C)). The potential of the word line WL changes when the BLEQ changes from H to L after the potential of the ZRAS signal changes from L level to H level, that is, a process of writing the data of the latch circuit 26 to the memory cell 10 (after data reading). Is changed from L to H again. When the potential of the word line WL is changed from L to H at the above timing, the signals supplied from the latch circuit 26 to BL and ZBL can be appropriately written to the memory cell 10.

In the case where a leak occurs in the word line WL, the potential of the word line WL is raised to the H level and then decreases with time. Therefore, when the potential of WL is maintained at the H level for a long time as in the device of the first embodiment, a situation may occur in which the potential of the word line WL cannot be properly maintained at the H level due to a leak abnormality or the like. obtain.

On the other hand, in the semiconductor memory device of the present embodiment, when the latch data of the latch circuit 26 is written into the memory cell 10, the potential of the word line WL is changed from L to H again. In this case, even if a leak abnormality occurs in the word line WL, the latch data can be appropriately written into the memory cell 10. Therefore, according to the semiconductor memory device of the present embodiment, in addition to the effect of the device of the first embodiment, it is possible to obtain an effect that more excellent operation stability can be realized.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to FIG. The semiconductor memory device of the present embodiment has the same configuration as the device of the first embodiment, that is, the configuration shown in FIG. 1 around the memory cell 10 and the sense amplifier 22.

FIG. 4 is a timing chart for explaining the operation of the semiconductor memory device of this embodiment. In the semiconductor memory device of the present embodiment, the control of the word line WL (FIG. 4B), the control of the S2P signal (FIG. 4F), and the control of the S2N signal (FIG. 4G) are implemented. It is characterized in that it differs from the first and second embodiments.

After the data read / write is requested, the semiconductor memory device of the present embodiment operates in the same manner as the devices of the first and second embodiments so that the data of the memory cell 10 is stored in the B memory.
Output to L or ZBL (FIG. 4 (D)). And B
When the potential difference between L and ZBL is amplified to a value that can be latched, gate A24 opens at that point and data is latched in latch circuit 26 (FIGS. 4 (L) and (M)).

The semiconductor device of this embodiment maintains the sense amplifier 22 in the active state for a predetermined period after latching data. After the data is output from memory cell 10 to BL or ZBL, if sense amplifier 22 is maintained in the active state for a sufficiently long time, the potentials of BL and ZBL approach convergence values (H or L), and consequently Memory cell 1
Data can be rewritten to 0.

In the present embodiment, the active state of the sense amplifier 22 is maintained until the rewriting of data to the memory cell 10 is completed. As described above, Embodiment 2
Of the semiconductor memory device of the first embodiment, when the state where data can be latched in the latch circuit 26 is realized, the sense amplifier 22
Is returned to the inactive state. The semiconductor memory device according to the present embodiment is different from the device according to the second embodiment in this point.

FIG. 4 (J) shows the waveform of the ZCE2 signal which switches from H to L when the potential difference between BL and ZBL is amplified to a value that can complete the data rewriting. In the present embodiment, when a predetermined delay time elapses after the ZCE2 signal changes to the L level, the BLEQ changes from L to H (FIG. 4B), and the S2P signal and the S2N signal are used as a reference. The potential changes to the potential V _BL (FIGS. _4F and 4G). According to the above processing, it is possible to prevent an L-level signal from being guided to the inactive memory cell 10 after the data rewrite to the memory cell 10 is completed. Therefore, according to the semiconductor memory device of the present embodiment, similarly to the first and second embodiments, a sufficiently long data holding time can be secured regardless of the operation mode of the device.

The semiconductor memory device of this embodiment further includes
When a predetermined delay time elapses after the CE2 signal changes to the L level, the potential of the word line WL is switched from H to L (FIG. 4C). When it becomes necessary to write the data of the latch circuit 26 to the memory cell 10, the potential of the word line WL is changed from L to H again at that time as described later. According to the above-described processing, as in the case of the second embodiment, it is possible to obtain stable operation characteristics without being affected by the leakage abnormality of the word line WL.

When data writing is requested to the semiconductor memory device, the same operation as in the device of the first or second embodiment is executed after the potential of word line WL is switched from H to L. Thus, the I / O lines 18 and Z
The data supplied from the I / O line 20 is latched by the latch circuit 26. The semiconductor memory device 26 of the present embodiment writes the data latched by the latch circuit 26 into the memory cell 10 after the ZRAS signal changes to H by the same processing as in the second embodiment. In this case, FIG.
4 (G) and FIG. 4 (I) change as shown by broken lines in the figure.

When data reading is requested from the semiconductor memory device, after the potential of the word line WL is switched from H to L, the latch circuit 26 operates in the same manner as the device of the second embodiment. I / O line 18 and ZI / O
Data is output on line 20.

In the semiconductor memory device of the present embodiment, data rewriting to the memory cell 10 is executed immediately after reading of data from the memory cell 10 is completed, as described above. Therefore, if the request to the semiconductor memory device is to read data, the I / O line 18
After the data is output to the ZI / O line 20, there is no need to rewrite the data again.

Therefore, after the ZRAS signal changes from L to H, the semiconductor memory device of the present embodiment operates as shown in FIG.
The signals shown in (B) to FIG. 4 (G) and FIG. 4 (I) are maintained at constant values as shown by the solid lines in the figure. More specifically, the equalizer is maintained in the operating state (FIG. 4B), and the potential of the word line WL is maintained at the L level (FIG. 4).
(C)), the sense amplifier 22 is kept in a non-operation state (FIGS. 4 (F) and 4 (G)), and the gate A24 is kept in a cut-off state (FIG. 4 (I)).

When the data rewrite is not necessary, as described above, after the ZRAS signal changes to the H level,
And ZBL can be maintained at a reference potential V _BL to.
Therefore, according to the semiconductor memory device of the present embodiment, the period during which an L-level potential is introduced to BL or ZBL can be further reduced as compared with the device of the second embodiment. Therefore, according to the semiconductor memory device of the present embodiment, the sub-threshold leak can be sufficiently suppressed, and the data retention period can be further extended as compared with the device of the second embodiment.

In the first to third embodiments, the processing for minimizing the period during which the L potential is led to BL or ZBL to secure a sufficient data holding time, Although the process is performed in combination with the process of using data as a cache, the present invention is not limited to this, and only the process for securing the data holding time may be performed.

In the first to third embodiments, the L-level potential guided to BL or ZBL is not limited to the ground potential, but may be a predetermined potential higher than the ground potential. When the L-level potential is higher than the ground potential, the current value due to sub-threshold leakage can be reduced. Therefore, by setting the L-level potential to a value higher than the ground potential, the data retention time can be made longer.

In the first to third embodiments, the bit line BL and the reference bit line ZBL correspond to the “bit line” in the first aspect.

[0077]

Since the present invention is configured as described above, it has the following effects. Claim 1
According to the invention described above, the potential of the bit line can be set to the reference potential after the data output from the memory cell is latched by the latch circuit. Therefore, according to the present invention, the period during which the amplified data potential is applied to the inactive memory cells can be sufficiently reduced. Therefore, according to the present invention, it is possible to suppress the influence of the sub-threshold leak in the memory cell and secure a sufficiently long data retention period. According to the present invention,
The data output from the memory cell or the data to be written to the memory cell is latched by the latch circuit, and the latched data can be stored until a row address is newly specified. Therefore, according to the present invention, the data latched in the latch circuit can be easily used as a cache.

According to the second aspect of the present invention, the data latched in the latch circuit is used as a cache. Therefore, according to the present invention, the data read processing can be speeded up.

According to the third aspect of the present invention, the word line is deactivated after the data of the memory cell is latched by the latch circuit, and then the word line is activated again at the time when data is to be written. it can. For this reason,
According to the present invention, data can be reliably written to a memory cell even when a leak abnormality occurs in a word line.

According to the fourth aspect of the present invention, the word line is maintained in the active state only for a minimum necessary for latching the data of the memory cell in the latch circuit. Therefore, according to the present invention, it is possible to speed up processing while reliably latching data.

According to the fifth aspect of the invention, before the word line changes from the active state to the inactive state, rewriting of data to the memory cell can be completed. According to the present invention, when it is not necessary to write new data to the memory cell thereafter, that is, when a data read process is required, activation of the word line and restart of the sense amplifier are omitted. can do. In this case, the period during which the amplified data is guided to the bit line is further reduced, so that the data holding period is further improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a timing chart for explaining an operation of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a timing chart for explaining an operation of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 4 is a timing chart for explaining an operation of the semiconductor memory device according to the third embodiment of the present invention;

FIG. 5 is a circuit diagram of a main part of a conventional semiconductor memory device.

[Explanation of symbols]

10 memory cells, 12 capacitors, 14
Transistors, 16 input / output gates (I / O gates), 18 input / output lines (I / O lines), 20 reference input / output lines (ZI / O lines), 22 sense amplifiers, and 26 latch circuits.

Claims (5)

[Claims] 1. A memory cell for outputting a data signal to a bit line when a word line is activated in accordance with designation of a row address, and a sense amplifier for amplifying data output to the bit line. A latch circuit for latching a signal amplified by the sense amplifier; and a gate disposed between the sense amplifier and the latch circuit, wherein the gate is in a cutoff state after the latch circuit latches data. The sense amplifier is deactivated, the potential of the bit line is set to the reference potential, and the latch circuit continues latching data until the next row address is designated. A semiconductor memory device characterized by the following. 2. The data latched in the latch circuit is output when a row address designated for reading data is the same as a previously designated row address. 2. The semiconductor memory device according to 1. 3. After the data is latched by the latch circuit, the word line is changed from an active state to an inactive state, and at a point in time when data is to be written to the memory cell, the word line is changed to an active state again. 3. The semiconductor memory device according to claim 1, wherein said sense amplifier is activated again. 4. The semiconductor device according to claim 3, wherein said word line is changed from an active state to an inactive state when data of said bit line is amplified to a value that can be latched by said latch circuit. Storage device. 5. The word line is changed from an active state to an inactive state when data on the bit line is amplified to a value that can complete rewriting of data to the memory cell. 4. The semiconductor memory device according to claim 3, wherein reactivation of said word line and reactivation of said sense amplifier are inhibited until a row address is newly designated.