JP2000244032A - Conductive film on piezoelectric element and its manufacture - Google Patents

Conductive film on piezoelectric element and its manufacture

Info

Publication number
JP2000244032A
JP2000244032A JP33940599A JP33940599A JP2000244032A JP 2000244032 A JP2000244032 A JP 2000244032A JP 33940599 A JP33940599 A JP 33940599A JP 33940599 A JP33940599 A JP 33940599A JP 2000244032 A JP2000244032 A JP 2000244032A
Authority
JP
Japan
Prior art keywords
film
piezoelectric element
conductive film
resist
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33940599A
Other languages
Japanese (ja)
Inventor
Akinori Kosaka
小阪彰伯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Crystal Device Corp
Original Assignee
Kyocera Crystal Device Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Crystal Device Corp filed Critical Kyocera Crystal Device Corp
Priority to JP33940599A priority Critical patent/JP2000244032A/en
Publication of JP2000244032A publication Critical patent/JP2000244032A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To stabilize the continuity between the faces of a piezoelectric element by integrally forming a conductive film having a uniform thickness and containing no junction in its structure. SOLUTION: A method for manufacturing a conductive film having a uniform thickness and containing no junction in its structure on a piezoelectric element includes a step of forming a metallic film in a uniform thickness on the whole surface of the piezoelectric element, a step of forming a resist film in a uniform thickness on the metallic film, and a step of arranging a mask on the main surface of the resist film. The method also includes a step of exposing the resist film at an upward angle of 50 deg.-70 deg. from the mask and developing the exposed resist film, a step of etching the exposed part of the metallic film after development, and a step of removing the resist film left on the metallic film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】 本発明は、振動子やセンサ
ー素子等に使用される圧電素子上に形成した導電膜及び
その製造方法に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to a conductive film formed on a piezoelectric element used for a vibrator, a sensor element, and the like, and a method for manufacturing the conductive film.

【0002】[0002]

【従来の技術】 近年電子部品の小型化は急速に進んで
いる。それに伴い部品パッケージ内に収納する素子自体
も小型化をしなければならない。中でも水晶や他の圧電
材料を用いた圧電素子を搭載した圧電部品の小型化は著
しいものがある。そこで部品内に収める圧電素子も小型
化精密化が必須となったため、圧電素子の製造方法とし
て、圧電素子自体の外形製造や、その圧電素子の複数の
面上にまたがるように作成された電極膜又は圧電素子各
面上に形成した電極膜を電気的に接続するように作成さ
れた配線等の導電膜の製造にフォトリソグラフィ法が用
いられている。
2. Description of the Related Art In recent years, miniaturization of electronic components has been rapidly progressing. Accordingly, the elements housed in the component package must also be reduced in size. Above all, there is a remarkable reduction in size of a piezoelectric component equipped with a piezoelectric element using quartz or another piezoelectric material. Therefore, the miniaturization and precision of the piezoelectric element to be housed in the component became necessary, so the method of manufacturing the piezoelectric element was to manufacture the outer shape of the piezoelectric element itself and to form an electrode film that was formed so as to extend over multiple surfaces of the piezoelectric element. Alternatively, a photolithography method is used for manufacturing a conductive film such as a wiring formed so as to electrically connect an electrode film formed on each surface of a piezoelectric element.

【0003】[0003]

【発明が解決しようとする課題】 しかし、圧電素子上
に形成する導電膜を、フォトリソグラフィ法を用いて形
成する場合、その形成過程において次のような課題が生
じている。まず、圧電素子全面に金,銀または合金など
の金属を膜厚均一に蒸着し、その上にレジスト膜を塗布
するが、圧電素子のエッジ部分におけるレジスト膜の膜
厚が他の部分のレジスト膜に比べ薄くなってしまうとい
う課題がある。この状態を図3に示す。
However, when a conductive film to be formed on a piezoelectric element is formed by photolithography, the following problems occur in the formation process. First, a metal such as gold, silver or an alloy is vapor-deposited uniformly on the entire surface of the piezoelectric element, and a resist film is applied thereon. There is a problem that it becomes thinner than that. This state is shown in FIG.

【0004】これは従来、多層金属膜を蒸着した圧電素
子をレジスト液内に浸漬し、その後余分なレジスト液を
除去することでレジスト膜を多層金属膜上全面に塗布し
ていたためである。この方法は非常に簡易であるが、レ
ジスト膜厚が圧電素子のエッジ部分で、レジスト液の表
面張力のために他の部分より薄くなり膜全体で厚みが均
一でなくなるために、後工程におけるエッチングの際
に、圧電素子エッジ部分のレジスト膜下の金属膜を完全
にエッチング液より保護できず、エッジ部分で金属膜が
切れてしまい圧電素子各面間の導通が得られない、又は
導通があったとしても非常に不安定な導通状態になって
しまう。
[0004] This is because conventionally, a piezoelectric element having a multi-layered metal film deposited thereon is immersed in a resist solution, and then the excess resist solution is removed to apply the resist film over the entire surface of the multi-layer metal film. This method is very simple, but the resist thickness at the edge of the piezoelectric element is thinner than the other parts due to the surface tension of the resist solution, and the thickness is not uniform throughout the film. In this case, the metal film under the resist film at the edge portion of the piezoelectric element cannot be completely protected by the etching solution, and the metal film is cut at the edge portion, so that conduction between the respective surfaces of the piezoelectric element cannot be obtained or there is no conduction. Even so, the conductive state becomes very unstable.

【0005】従来はこのエッジ部分の絶縁や不安定状態
を回避するため、導電膜をフォトリソグラフィ法で形成
後、圧電素子各面間で導通が必要なエッジ部分に、各面
上に形成した導電膜を接続するような形状の金属膜を蒸
着法で形成し導通を確実にする工程が必要となってい
る。尚、このような形状の金属膜を形成した場合、圧電
素子の振動状態に少なからず影響を与えることが考えら
れる。この状態を図4に示す。
Conventionally, in order to avoid insulation or an unstable state at the edge portion, after forming a conductive film by photolithography, the conductive portion formed on each surface is placed at the edge portion where conduction is required between the piezoelectric element surfaces. There is a need for a process of forming a metal film having such a shape as to connect the films by a vapor deposition method to ensure conduction. In addition, when the metal film having such a shape is formed, it is considered that the vibration state of the piezoelectric element is affected to a considerable extent. This state is shown in FIG.

【0006】つぎにレジスト膜を塗布後、その主面上に
マスクを配置し、そのマスク上方より主面及び側面を露
光するが、露光する角度はマスクに対し90°に近い角
度のため側面部分の露光が良好ではなく、高精度の露光
を行わない限り、現像後に残る側面のレジスト膜は所望
の形状と差異が生じてしまう可能性があり、エッチング
後の導電膜の形状に狂いが生じることもある。
Next, after applying a resist film, a mask is arranged on the main surface, and the main surface and the side surface are exposed from above the mask. Unless exposure is not good and high-precision exposure is not performed, there is a possibility that the resist film on the side surface remaining after development may have a difference from the desired shape, and the shape of the conductive film after etching may be irregular. There is also.

【0007】[0007]

【課題を解決するための手段】本発明は前記課題を解決
するもので、まずフォトリソグラフィ法により圧電素子
の複数の面上にまたがるように作成された導電膜におい
て、圧電素子の一面上から他面上へ至るよう形成された
導電膜が、すべての箇所において均一の膜厚であり、且
つ導電膜の構造中に接合部分がなく一体形成であること
を特徴とする圧電素子上の導電膜である。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems. First, in a conductive film formed over a plurality of surfaces of a piezoelectric element by a photolithography method, another conductive film is formed on one side of the piezoelectric element. A conductive film formed on the piezoelectric element, wherein the conductive film formed so as to reach the surface has a uniform thickness at all locations, and has no joint in the structure of the conductive film and is integrally formed. is there.

【0008】また、その製造方法は、所望の外形に加工
した圧電素子全面に、導電膜の材料となる多層金属膜を
均一な膜厚で形成する工程と、この多層金属膜上にレジ
スト膜を均一な膜厚で形成する工程と、このレジスト膜
の主面上に、主面及び側面に形成する所望の導電膜パタ
ーンを形成したマスクを配置する工程と、このマスクに
対し上方50°〜70°の角度で、主面及び側面のレジ
スト膜を同時に露光し現像する工程と、現像後にレジス
ト膜が除かれて露出した部分の金属膜をエッチングによ
り除去する工程と、残った多層金属膜上のレジスト膜を
除去する工程からなる。
[0008] Further, the manufacturing method includes a step of forming a multilayer metal film as a material of a conductive film to a uniform thickness on the entire surface of the piezoelectric element processed into a desired outer shape, and a step of forming a resist film on the multilayer metal film. A step of forming a film having a uniform thickness, a step of arranging a mask on which a desired conductive film pattern to be formed on the main surface and side surfaces is formed on the main surface of the resist film, At the angle of °, the step of simultaneously exposing and developing the resist film on the main surface and the side surface, the step of removing the exposed part of the metal film by removing the resist film after the development, and the step of etching the remaining multi-layered metal film And removing the resist film.

【0009】本発明により、従来行っていた、圧電素子
各面間で導通が必要なエッジ部分に、各面上に形成した
導電膜を接続するような形状の金属膜を蒸着法で形成し
導通を確実にする工程が必要なくなり、且つ導電膜の構
造中に接合部分がなく一体形成であることにより圧電素
子の振動を阻害するような因子がなくなり安定する。
According to the present invention, a metal film having such a shape as to connect a conductive film formed on each surface is formed by vapor deposition on an edge portion where conduction is required between each surface of the piezoelectric element. Is eliminated, and since there is no joint portion in the structure of the conductive film and it is integrally formed, there is no factor that hinders the vibration of the piezoelectric element, and the structure is stabilized.

【0010】また、マスクに対し上方50°〜70°の
角度で露光することにより、主面と側面に形成するレジ
ストマスクの形状を同時に、且つ所望の形状に正確に形
成することができ、後のエッチングの際に所望の導電膜
の形状を得ることができる。
Further, by exposing the mask at an angle of 50 ° to 70 ° above, the resist masks formed on the main surface and the side surfaces can be simultaneously and accurately formed into a desired shape. A desired conductive film shape can be obtained at the time of etching.

【0011】[0011]

【実施例】以下に、添付図面に従って本発明の実施例を
説明する。なお、各図において同一の符号は同じ対象を
示すものとする。
Embodiments of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same reference numeral indicates the same object.

【0012】図1には本発明における導電膜2を形成後
の圧電素子1のエッジ部分を示す。実際は一枚の圧電素
板中に複数の圧電素子をフォトリソグラフィ法で外形形
成し、且つその複数個の圧電素子の対し同時に導電膜等
を形成しているが、図ではそのうち一つの圧電素子のエ
ッジ部分を含む一部分を、膜形状などを簡略化した形
で、拡大して示している。尚、本発明における導電膜と
は、圧電素子の単一面上や複数の面上にまたがるように
作成された電極膜、又は圧電素子各面上に形成した電極
膜を電気的に接続するように作成された配線等のことで
ある。さらに、本発明ではフォトリソグラフィ法で外形
形成した圧電素子を使用しているが、他の方法で外形形
成した圧電素子上に形成する導電膜にも本発明は利用可
能である。
FIG. 1 shows an edge portion of a piezoelectric element 1 after forming a conductive film 2 in the present invention. Actually, a plurality of piezoelectric elements are formed on a single piezoelectric element by photolithography, and a conductive film or the like is simultaneously formed on the plurality of piezoelectric elements. A portion including the edge portion is enlarged and shown in a simplified form of the film shape and the like. Note that the conductive film in the present invention is an electrode film formed so as to extend over a single surface or a plurality of surfaces of a piezoelectric element, or an electrode film formed on each surface of a piezoelectric element so as to be electrically connected. This refers to the created wiring and the like. Further, in the present invention, a piezoelectric element whose outer shape is formed by a photolithography method is used, but the present invention is also applicable to a conductive film formed on a piezoelectric element whose outer shape is formed by another method.

【0013】本発明における導電膜2では、圧電素子1
の一面から他の一面へ至る導電膜2の構造を、均一の膜
厚であり且つ構造上どこにも接続箇所のない一体型の構
造としている。このような構造により、エッジ部分にお
いての導電膜2の不導通の危険がなくなり、且つ圧電素
子1表面に余分な質量体がないため、圧電素子1の振動
特性に与えるストレスも最小限にすることができる。
In the conductive film 2 of the present invention, the piezoelectric element 1
The structure of the conductive film 2 from one surface to the other surface is an integrated structure having a uniform film thickness and no structural connection anywhere. With such a structure, the risk of non-conduction of the conductive film 2 at the edge portion is eliminated, and since there is no extra mass on the surface of the piezoelectric element 1, stress applied to the vibration characteristics of the piezoelectric element 1 is minimized. Can be.

【0014】図2には本発明における導電膜2の製造方
法を示す。図2は導電膜2の形成過程が明瞭となるよ
う、圧電素子の一部分の断面用い、且つ膜などの形状を
簡略化した形で図示した。
FIG. 2 shows a method of manufacturing the conductive film 2 according to the present invention. FIG. 2 shows a cross section of a part of the piezoelectric element and simplifies the shape of the film and the like so that the process of forming the conductive film 2 is clear.

【0015】まず、洗浄を行った圧電素子1全面に金、
銀又は合金を多層構造ですべての面で均一の膜厚に蒸着
し多層金属膜2aを形成する。
First, gold is applied to the entire surface of the cleaned piezoelectric element 1.
Silver or an alloy is deposited in a multilayer structure to a uniform thickness on all surfaces to form a multilayer metal film 2a.

【0016】次に、多層金属膜2a全面上に、レジスト
を全面均一の厚みで形成しレジスト膜3を得る。本発明
ではレジストを膜厚均一に形成するための方法として、
電着法を用いてレジスト膜3を形成する方法又はスプレ
ーを用いてレジストを塗布しレジスト膜3を形成する方
法を使用している。この方法により多層金属膜のすべて
の面上にレジスト膜3を膜厚均一に形成できる。
Next, a resist is formed with a uniform thickness on the entire surface of the multilayer metal film 2a to obtain a resist film 3. In the present invention, as a method for forming a uniform thickness of the resist,
A method of forming the resist film 3 using an electrodeposition method or a method of forming a resist film 3 by applying a resist using a spray is used. By this method, the resist film 3 can be formed uniformly on all surfaces of the multilayer metal film.

【0017】次に、多層金属膜2a及びレジスト膜3を
形成した圧電素子1の各面のうち、主面となる面上に、
主面及び主面と連続してなる側面に形成する導電膜2の
パターンを形成したガラスマスク4を配置する。
Next, among the respective surfaces of the piezoelectric element 1 on which the multilayer metal film 2a and the resist film 3 are formed,
A glass mask 4 on which a pattern of a conductive film 2 to be formed on the main surface and a side surface continuous with the main surface is arranged.

【0018】次に、配置したガラスマスク4上方より5
0°〜70°の角度で、主面及び側面に形成したレジス
ト膜3を露光する。露光角度が従来と比べ50°〜70
°と傾いているため、主面及び側面のマスクパターンを
従来に比べ正確にレジスト膜3に露光することができ
る。尚、本実施例では紫外線領域の波長を有する電磁波
を照射して露光を行っているが、レジスト膜を露光でき
るものならば可視光線等の他の波長領域の電磁波でも良
い。この露光後に現像を行う。
Next, 5 mm from above the placed glass mask 4.
The resist film 3 formed on the main surface and the side surface is exposed at an angle of 0 ° to 70 °. Exposure angle is 50 ° -70 compared to conventional
°, the mask pattern on the main surface and the side surface can be exposed to the resist film 3 more accurately than in the past. In this embodiment, exposure is performed by irradiating an electromagnetic wave having a wavelength in the ultraviolet region. However, an electromagnetic wave in another wavelength region such as visible light may be used as long as the resist film can be exposed. After this exposure, development is performed.

【0019】次に、導電膜2の所望パターンで多層金属
膜2a上に残ったレジスト膜3(金属膜に対するレジス
トのマスク)を有する圧電素子1をエッチングし、レジ
スト膜3がなく露出した多層金属膜部分を除去する。
Next, the piezoelectric element 1 having the resist film 3 (resist mask for the metal film) remaining on the multilayer metal film 2a in a desired pattern of the conductive film 2 is etched to expose the multilayer metal film without the resist film 3. The film part is removed.

【0020】次に、圧電素子1面上に残っている多層金
属膜2a上にあるレジスト膜3を除去し、圧電素子1上
に所望の導電膜2を形成する。
Next, the resist film 3 on the multilayer metal film 2a remaining on the surface of the piezoelectric element 1 is removed, and a desired conductive film 2 is formed on the piezoelectric element 1.

【0021】[0021]

【発明の効果】本発明により、圧電素子各面間で導通が
必要なエッジ部分に、各面上に形成した導電膜を接続す
るような形状の金属膜を蒸着法で形成し導通を確実にす
る工程が不要となり工数を削減できる。また、導電膜の
構造中に接合部分がなく一体形成であることにより圧電
素子の特性を悪化させるような因子がなくなり特性の安
定化が図れる。さらに、露光角度をマスクに対し上方5
0°〜70°の角度にすることにより、主面と側面に形
成するレジストマスクの形状を同時に、且つ所望の形状
に正確に形成することができ、後のエッチングの際に所
望の導電膜の形状を確実に得ることができる。
According to the present invention, a metal film having such a shape as to connect a conductive film formed on each surface is formed by an evaporation method at an edge portion where conduction is required between each surface of the piezoelectric element, thereby ensuring conduction. This eliminates the need for a step to perform, thus reducing man-hours. In addition, since there is no bonding portion in the structure of the conductive film and it is formed integrally, there is no factor that deteriorates the characteristics of the piezoelectric element, and the characteristics can be stabilized. Further, the exposure angle is set to 5
By setting the angle to 0 ° to 70 °, the shapes of the resist masks formed on the main surface and the side surfaces can be formed simultaneously and accurately to a desired shape, and a desired conductive film can be formed at a later etching time. The shape can be reliably obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1には本発明の膜形状を示す。FIG. 1 shows a film shape of the present invention.

【図2】図2には本発明の導電膜の形成工程図を示す。FIG. 2 shows a process chart for forming a conductive film of the present invention.

【図3】図3には従来のレジスト膜塗布時におけるレジ
スト膜形状を示す。
FIG. 3 shows a conventional resist film shape when a resist film is applied.

【図4】図4には従来の膜形状を示す。FIG. 4 shows a conventional film shape.

【符号の説明】[Explanation of symbols]

1 圧電素子 2 導電膜 2a 多層金属膜 3 レジスト膜 4 マスク DESCRIPTION OF SYMBOLS 1 Piezoelectric element 2 Conductive film 2a Multilayer metal film 3 Resist film 4 Mask

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H03H 9/13 H01L 41/22 Z ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H03H 9/13 H01L 41/22 Z

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 フォトリソグラフィ法により圧電素子の
複数の面上にまたがるように作成された導電膜におい
て、該圧電素子の一面上から他面上へ至るよう形成され
た該導電膜が、すべての箇所において均一の膜厚であ
り、且つ該導電膜の構造中に接合部分がなく一体形成で
あることを特徴とする圧電素子上の導電膜。
1. A conductive film formed over a plurality of surfaces of a piezoelectric element by a photolithography method, wherein the conductive film formed from one surface of the piezoelectric element to the other surface includes all the conductive films. A conductive film on a piezoelectric element, wherein the conductive film has a uniform thickness at a portion and has no joint portion in the structure of the conductive film and is integrally formed.
【請求項2】 所望の外形に加工した圧電素子全面に、
導電膜の材料となる多層金属膜を均一な膜厚で形成する
工程と、該多層金属膜上にレジスト膜を均一な膜厚で形
成する工程と、該レジスト膜の主面に、該主面を含む複
数の側面に形成する所望の導電膜パターンを形成したマ
スクを配置する工程と、該マスクに対し上方50°〜7
0°の角度で、該圧電素子の該主面及び該側面にある該
レジスト膜を同時に露光し現像する工程と、該レジスト
膜が除かれて露出した部分の該多層金属膜をエッチング
により除去する工程と、残った多層金属膜上の該レジス
ト膜を剥離する工程からなる圧電素子上の導電膜の製造
方法。
2. The entire surface of a piezoelectric element processed into a desired outer shape,
A step of forming a multilayer metal film as a material of the conductive film with a uniform film thickness; a step of forming a resist film with a uniform film thickness on the multilayer metal film; Arranging a mask on which a desired conductive film pattern to be formed on a plurality of side surfaces is formed;
Simultaneously exposing and developing the resist film on the main surface and the side surface of the piezoelectric element at an angle of 0 °, and removing the resist film by removing the exposed portion of the multilayer metal film by etching; A method for producing a conductive film on a piezoelectric element, comprising: a step of removing the resist film on the remaining multilayer metal film.
JP33940599A 1998-12-25 1999-11-30 Conductive film on piezoelectric element and its manufacture Pending JP2000244032A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP36874698 1998-12-25
JP10-368746 1998-12-25
JP33940599A JP2000244032A (en) 1998-12-25 1999-11-30 Conductive film on piezoelectric element and its manufacture

Publications (1)

Publication Number Publication Date
JP2000244032A true JP2000244032A (en) 2000-09-08

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030025204A (en) * 2001-09-19 2003-03-28 가부시키가이샤 무라타 세이사쿠쇼 Method of forming electrode pattern of surface acoustic wave device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030025204A (en) * 2001-09-19 2003-03-28 가부시키가이샤 무라타 세이사쿠쇼 Method of forming electrode pattern of surface acoustic wave device

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