JP2000242488A - Memory reloading method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten download time or verify time while keeping the degree of freedom in the layout of a control board. SOLUTION: In the case of verify processing, the addresses of verify data are divided into first half and latter half, and a CPU 20 of a first control board 12 sequentially reads the address data of the first half from an IC card 50 and transmits than through a universal asynchronous receiver and transmitter(UART) 18 and a serial line 60 to a second control board 32. Parallel with this transmission, a CPU 40 of the second control board 32 sequentially reads the address data of the latter half from a flash memory 36 and transmits them through a UART 38 and the serial line 60 to the first control board 12. The first control board 12 performs verify for comparing the received data of the latter half with the data of the latter half of the IC card 50 and comparing the data of the first half received by the second control board 32 with the data of the first half in the flash memory 38.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory rewriting method, and more particularly, to a memory rewriting method for rewriting and verifying program data of a control device using a rewritable memory.

[0002]

2. Description of the Related Art Conventionally, in various information processing apparatuses such as a personal computer, a control program for controlling the apparatus is stored in a memory or the like in advance, and the information processing operation is performed according to the control program.

In this type of information processing apparatus, for example, a plurality of control boards (first control board, second control board, etc.) are provided as control boards constituting the apparatus. The first control board and the second control board are, for example, an asynchronous serial transmission LSI (LargeScale Integrated Circuit).
UART (Universal Asynchronous Receiv)
The first control board is provided with a memory card connector, and a memory card (IC card) or the like is inserted from the outside of the device to program data and the like. Can be exchanged, and the other second control plate is mounted inside the device where it is difficult to mount a connector or the like.

Further, the first control plate and the second control plate include:
As a rewritable memory for storing program data, for example, a flash memory or the like is adopted,
To upgrade the version of program data,
The so-called program download, in which the version-up program stored in the C card is copied to the flash memory side, has been performed.

[0005] As a procedure for downloading a program using the above configuration, for example, when rewriting the contents of the flash memory of the second control board, first, the contents of the flash memory of the second control board are erased (chip erase).
Read data from IC card with 1st control board,
The address and data are serially communicated to the second control board. The second control board writes the received data to the flash memory corresponding to the received address. These operations are performed for all target addresses.

Further, as a method of confirming whether or not the program has been successfully downloaded, a data comparison between a download source (IC card side) and a download destination (flash memory side) is performed for all addresses of a program to be downloaded. So-called verify, which is to confirm that all the data match. This verification is used when confirming success after downloading a program or when confirming what the current program is.

As a procedure for performing verification using the above configuration, a first control board reads program data and the like from an IC card (hereinafter referred to as a read), and the first control board serially reads the read address and data. The signal is transmitted to the second control board via the line. The second control board compares the content of the flash memory at the received address with the received data.

On the contrary, the data stored in the flash memory of the second control board is read, and the second control board transmits the read address and data to the first control board via a serial line. Send to the board. The first control board may compare the contents of the IC card at the received address with the received data.

As described above, even when any of the above methods is performed, the verification is performed for all the target addresses. Japanese Patent Application Laid-Open Nos. Hei 5-81012, Hei 6-47996, and Hei 7-64952 disclose data rewriting and verifying.

[0010]

However, in such a memory rewriting method for performing download and verification, a plurality of control boards are connected by a bidirectional communication line because download data is not transmitted. It can be used not only when transmitting and receiving, but also when it is necessary to communicate with each other in order to download the downloaded data accurately and reliably (during verification).

As described above, a plurality of control boards are provided, and the control board is divided into a control board that handles a user interface and a board that handles an engine sequence. For example, one control board can be easily inserted into an IC card from outside the apparatus. If mounted in a place, other control boards do not necessarily need to be mounted in such a place, so that the layout of the control board becomes free.

However, if verification is performed in such a situation, it is necessary to perform serial communication from the first control board to the second control board or from the second control board to the first control board. In addition to the time, there is a problem that extra communication time is required. Therefore, if the flash memory is mounted on the control board to which the IC card is directly connected without dividing the control board into a plurality, the verification time can be shortened by the time that the communication time is unnecessary, but the layout of the control board is more flexible. Is lost.

When a program is downloaded to rewrite the program, the flash memory of the second control board is once completely erased (chip erase),
Since it was necessary to transmit data and address serially from the first control board to the second control board and write the transmitted program data to the flash memory, there was a problem that it took a long time to download.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to efficiently download and verify a program or the like while maintaining the degree of freedom in the layout of a control board, thereby rewriting time of a program or the like and verifying the time. It is an object of the present invention to provide a memory rewriting method capable of shortening the time.

[0015]

According to a first aspect of the present invention, a first control board and a second control board are connected to each other by a bidirectional communication line, and the second control board has a rewritable memory. In the memory rewriting method, the first control board has an interface for taking in rewrite data for rewriting the contents of the rewritable memory of the second control board, wherein the rewrite data taken into the first control board via the interface is provided. And verifying the data after rewriting of the rewritable memory of the second control board, the verifying data is divided into at least two address groups, and the one of the first control board is transmitted from the first control board via the communication line. Rewriting data for each address belonging to the address group is transmitted to the second control board, and rewriting of the second control board after rewriting is performed. And comparing the contents of the rewritable memory for each address belonging to the other address group from the second control board to the first control board via the communication line. The processing for comparing with rewrite data taken in from the interface of the first control board is performed in parallel.

According to this, when verifying the rewrite data taken into the first control board via the interface and the rewritten data of the rewritable memory of the second control board, the verify data is transferred to at least two addresses. And rewriting data for each address belonging to one of the address groups is transmitted from the first control board to the second control board via a communication line, and the rewritten second data is transmitted to the second control board.
A process of comparing with the contents of the rewritable memory of the control board;
A process of transmitting the contents of the rewritable memory for each address belonging to the other address group from the second control board to the first control board via a communication line, and comparing the rewritable data with rewrite data taken in from the interface of the first control board. And were processed in parallel. For this reason, even if a plurality of control boards are provided and connected to each other via a communication line so that the layout of the control boards has a degree of freedom, the verification time can be greatly reduced.

According to a second aspect of the present invention, the first control board and the second control board are connected to each other by a two-way communication line, the second control board has a flash memory, and the first control board has a flash memory. Is a memory rewriting method having an interface for taking in rewriting data for rewriting the content of the flash memory of the second control board, wherein the content of the flash memory is written using the rewriting data taken into the first control board via the interface. In rewriting, the memory erasure of the flash memory in the second control plate is performed in units of a predetermined unit, and the rewrite data captured by the first control plate via the interface during the erasure of the memory in the predetermined unit is performed. The first
The data is transmitted from the control board to the second control board, and the data is rewritten for each unit of the flash memory in which the memory erasure is completed.

According to this, when rewriting the contents of the flash memory using the rewriting data taken into the first control board via the interface, the memory erasure of the flash memory in the second control board is performed for each predetermined unit. The first control board transmits the rewrite data fetched via the interface from the first control board to the second control board during the memory erasing of the predetermined unit, and the memory is erased for each unit of the flash memory. To rewrite data. For this reason, even if a plurality of control boards are provided and connected to each other by a communication line, and the configuration of the control boards is configured to have a degree of freedom, it is possible to rewrite a program with high time efficiency.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
1 is a block diagram illustrating a schematic configuration of an information processing apparatus 10 according to the first embodiment. The information processing apparatus 10 shown in FIG.
The second control board 32 and the second control board 32 are separately arranged and connected to each other by a serial line 60 as a communication line.
, And a connector (not shown) as an interface capable of taking in program data and the like. The second control plate 32 is provided inside the device where it is difficult to attach a connector or the like here.

The configuration of the first control plate 12 and the second control plate 32 described above both
AM 14, 34, flash memory 16, 36, and UART (Universal Asynchronous Receiver and
Transmitters 18 and 38 are mutually connected by a CPU bus. Further, in the first control plate 12,
The CPU 20 and the IC card 50 are connected via a CPU bus via an interface (not shown).

The R of the first control plate 12 and the second control plate 32
The AMs 14 and 34 are rewritable memories for stacks and other works necessary for execution instructions of the CPUs 20 and 40, respectively. In particular, in the RAM 34 of the second control board 32, a rewriting execution program for rewriting the program data is temporarily written and executed there, or the rewriting data received by the second control board 32 is temporarily written until it is written into the flash memory 36. Or holding.

The flash memories (FLASH MEMORY) 16 and 36 of the first control board 12 and the second control board 32 have a CPU
It is a rewritable nonvolatile memory that stores 20, 40 execution instructions and data necessary for the instructions.

U of the first control plate 12 and the second control plate 32
Each of the ARTs 18 and 38 is a transceiver device using an asynchronous serial transmission LSI, and has a communication speed of 9600 bps here and a data length of 8 bits, 1 stop bit, and 1 parity bit.
Character = 10 bits, and required time per character = approximately 1.04 ms.

The serial line (communication line) 60 is connected to the UART 18 of the first control board 12 and the UART 3 of the second control board 32.
8 are mutually connected, and the upper line in the figure is the first control board 12 to the second control board 32.
Is a line for transmitting data to the second control board 3
2 is a line for transmitting data to the first control board 12.

An operation panel for downloading, monitoring the process and progress of the download, verifying the process, and monitoring the process and the result is connected to the first control board 12, Both the case where it is connected to the 2 control board 32 is considered. In the first embodiment,
Description will be given assuming that the above-described operation panel is connected to the first control plate 12 (not shown in FIG. 1).

Although not the configuration of the information processing apparatus 10, the following two methods are available for storing the download program of the IC card 50 connected to the first control board 12.

The programs to be stored in the flash memories 16 and 36 of the first control board 12 and the second control board 32 are stored in a single IC card having a reproducible capacity (for the first control board). And the storage address of the program for the second control board is divided in advance).

An IC card storing a program for the first control board and an IC card storing a program for the second control board are prepared, and which program is stored is determined by the IC card. The identifier is stored in advance at the fixed address, or the I / O
There may be a method specified by the operator who inserted the C card.

Although the first embodiment shows an example in which the download source data stored in the IC card is uncompressed, the case where the source data is compressed can be handled in the same manner.

The difference between the address space of the first control board 12 of the IC card 50 as viewed from the CPU 20 and the address space of the flash memory as viewed from the second control board 32 is converted on the data transmitting side. Alternatively, the conversion may be performed on the receiving side, or a method may be used in which each of the transmitting and receiving sides handles the address as a relative address from the head address of the flash memory.

Further, the transmission method of the address and the data includes a method of transmitting the address with the data every time as a set, and a method of transmitting the data only in a predetermined order after the address is previously agreed. In the first embodiment, transmission is performed using the latter method.
Data is transmitted incrementally in ascending order of addresses from a predetermined address.

Using the information processing apparatus 10 configured as described above, whether the data downloaded from the IC card 50 to the flash memory 36 of the second control board matches the data in the flash memory 36 after the download. Will be described below to verify whether or not the program data is correctly downloaded.

FIGS. 2 to 6 are flowcharts for explaining the operation relating to the verify processing according to the first embodiment. First, when the information processing apparatus 10 enters the verify mode, the first control board 12 through the serial line 60 in FIG.
The second control board 32 can recognize that the mode is the verify mode. The selection of the verify mode is performed on an operation panel (not shown). When the operation panel is connected to the first control board 12 as in the first embodiment, the first control board 12 notifies the second control board 32 that the verify mode has been set.

Next, when a verify key on the operation panel is operated, a verify operation starts. FIG. 2 is a flowchart illustrating an IC card data transmission process of the first control board 12. As shown in FIG. 2, the first control board 12 reads the program data from the IC card 50 and transmits the data to the second control board 32 in order for the second control board 32 to perform the verification. Done.

First, the pointer 1 for accessing the IC card is initialized to the head of the flash memory address of the second control board 32 (step S1). Embodiment 1
In the first embodiment, the first half in the ascending order of the verify address range is subjected to the verifying process by the second control board 32, and the second half is verified by the first control board 12.
It is preferable that the unit of the division is arbitrary, and in consideration of the processing capability of the CPU, it is preferable to allocate the verify times to be exactly the same in both cases. In this case, the processing time is the shortest.

Next, the CPU 20 reads the data at the address indicated by the pointer 1 (step S2), and transmits the obtained data to the second control board 32 (step S2).
3).

Then, the pointer is incremented so that the next data is used as an index (step S).
4). Next, the pointer 1 is compared with the end address to determine whether or not half of the space for the flash memory of the second control board 32 has been completed (step S5). The data transmission process is repeated, and if the transmission of the determined data has been completed, the flow of FIG. 2 ends.

In step S3 of FIG. 2, the first
When the read data is transmitted from the control board 12 to the second control board 32, the queuing control is performed according to the readyness of the transmission buffer of the UART 18 and the transmission condition on the communication protocol to be adopted. It is assumed that the same control is performed in the UARTs 18 and 38 also when data is transmitted in the following description of the flowchart.

Next, the verifying process on the second control plate 32 side in FIG. 3 will be described. FIG. 3 is a flowchart of the verifying process of the second control board. The second control board compares the data received from the first control board with the flash memory by the processing of FIG.

As shown in FIG. 3, the read pointer 4 for accessing the flash memory is initialized to the head address of the flash memory (step S11), and data waiting from the first control board 12 is waited (step S12). ,
When the data is received, the data at the address indicated by the pointer 4 is read and temporarily stored in the RAM 34 as data in the flash memory 36 (hereinafter, referred to as FDATA) (step S13).

The received data is stored in the RAM 34 as comparison data (hereinafter referred to as CDATA) of the IC card.
Is stored temporarily. The CPU 40 determines F in step S14.
If DATA and CDATA match, the pointer is incremented for the next address (step S
15). Then, in step S16, the pointer 4 is compared with the end address to determine whether or not half of the space for the flash memory 36 of the second control board 32 has been completed (step S16). S12
And the comparison operation is repeated. Step S1
If the comparison of the data determined in step 6 has been completed, a successful completion of the verification is transmitted to the first control board 12 (step S17), and this flowchart ends.

On the other hand, if the compared data do not match in step S14, a verification failure end is transmitted to the first control board 12 (step S18), and the mismatch address indicated by the pointer 4 and the flash memory Data (FDATA) and IC card comparison data (CD
ATA) to the first control board 12 (step S1).
9). That is, when the above-described verify error occurs, the comparison operation is terminated at that time.

Although not described in the flowchart, when the first control board 12 receives a verify error from the second control board 32, it prevents the untransmitted CDATA from being transmitted.

Next, the verifying operation in the latter half will be described. FIG. 4 is a flowchart of the IC card data transmission process of the second control board 32. In FIG. 4, the second
Data is read from the flash memory 36 of the control board 32 and the data is sequentially transmitted to the first control board 12 so that the first control board 12 performs the verifying process.

First, the pointer 3 for accessing the flash memory 36 is initialized to the head of the latter half of the flash memory (step S21). Next, pointer 3
Is read (step S).
22), and transmits the obtained data to the first control board 12 (step S23). Then, the pointer 3 is incremented to index the next data (step S24).

Next, by comparing the pointer 3 with the end address, it is determined whether or not the end of the space for the flash memory 36 of the second control board 32 has been completed (Step S).
25) If not completed, the flow returns to step S22 to transmit the data of the flash memory to the first control board 12, and if the transmission of the determined data has been completed, this flowchart ends.

Next, using the flowchart of FIG.
Processing on the control plate 12 side will be described. FIG. 5 is a flowchart of the verifying process of the first control board 12, which is a process of comparing the data of the flash memory received by the first control board 12 from the second control board 32 with the data of the IC card in FIG. is there.

First, the read pointer 2 for accessing the IC card 50 is initialized to the latter half of the address for the flash memory of the second control board of the IC card 50 (step S31). CPU of first control board 12
20 waits for the comparison data to be received from the second control board 32 (3-2), and upon receiving the data, reads the IC card 50 data indicated by the pointer 2 to read the CDATA.
Is temporarily stored in the RAM 14 (step S33).
The received data is stored in RAM1 as FDATA.
4 is temporarily stored.

In step S34, FDATA and C
If DATA matches, the pointer 2 is incremented for the next address (step S3).
5). Then, by comparing the pointer 2 with the end address, it is determined whether the end of the space for the flash memory 36 of the second control board 32 has been completed (step S3).
6). If not, the process returns to step S32 to repeat the comparison process between FDATA and CDATA. If the comparison of the determined data has been completed, this flowchart ends.

On the other hand, if the comparison data does not match in step S34, the mismatch address of the pointer 2, the data in the flash memory (FDATA), and the comparison data in the IC card (CDATA) are displayed on an operation panel (not shown). (Step S37). That is, when a verify error occurs, the comparison ends at that point.

Although not described in the flowchart of FIG. 5, when a verify error is transmitted from the first control board 12 to the second control board 32 and the second control board 32 receives the verify error, 2 Untransmitted F of control board 32
Do not transmit about DATA.

Next, the end processing of the verification will be described with reference to FIG.
This will be described with reference to FIG. FIG. 6 is a flowchart of the verify end processing of the first control board, but also explains the end of the verify processing of the second control board. First, the process waits for the end of the verification process in the second control board 32 (step S41), and when the verification process of the second control board 32 ends, checks whether the verification process is successful (step S42). If the verification process of the second control board 32 is successful, the process waits for the completion of the verification process of the first control board 12 (step S4).
3), when the verification process of the first control plate 12 is completed,
It is checked whether or not the verification process has succeeded (step S44). If the verification process of the first control board 12 is also successful, a message indicating that all the verification processes have been successfully completed is displayed on the operation panel (step S45).

If the verification processing of the second control board 32 fails in step S42, it means that there is a mismatch in the first half of the address, and only that the verification processing of the first control board 12 is completed. (Step S46), an error address and data (FDATA and CDATA) are displayed on the operation panel (step S47), and a message indicating that the verification has failed is displayed (step S47).

If an error has occurred in the verifying process of the first control board 12, the error address and data (FDATA and CDA) have already been set in step S37 of FIG.
TA) is displayed on the operation panel.

If the verification processing of the second control board 32 is successful (YES in step S42) and the verification processing of the first control board 12 fails (step S4).
No at step 4), meaning that there is a mismatch in the latter half of the address, and the fact that verification has failed is displayed on the operation panel (step S49). The error address and data (FDATA and CDATA) have already been displayed on the operation panel in step S37 in FIG.

As described above, in the first embodiment, one address is provided for each of the first half and the second half, and display for two addresses is possible.

Next, the first embodiment will be described with reference to FIGS.
The difference in the verify processing time between the present embodiment and the comparative example will be described. FIG. 7 is a diagram of a comparative example showing the transmission time and the verify processing time when all programs are transmitted from the flash memory of the second control board to the first control board and the first control board performs the verify processing; FIG. 8 shows the IC of the first control board.
FIG. 11 is a diagram of a comparative example showing a transmission time and a verification processing time when all programs are transmitted from a card to a second control board and the second control board performs a verification process. FIG. 9 shows the transmission time and the verify processing time when the verify data is divided into two parts (the first half and the latter half) and the first control board side and the second control board side perform the verify processing simultaneously and in parallel. FIG.

In the comparative examples shown in FIGS. 7 and 8, the entire program of the flash memory is serially transmitted from the second control board to the first control board, such as the second control board → the first control board. If the panel is attached to the first control plate), the first
In the case where the entire program of the IC card is serially transmitted from the first control board to the second control board as in the case of the control board → the second control board (when the operation panel is attached to the second control board), the verification is performed. Since all the data to be compared are transmitted from one side to the other side, and the verifying process is performed at the destination, most of the verifying process time is occupied by the serial transmission time. The verification processing time is shorter than the serial transmission time, so the actual occupation ratio of the verification processing is small. However, the comparison processing must be performed using the transmitted program data. The transfer and verify processing periods are the same, and a long time is required (the length of the rectangular cell in the right column of FIGS. 7 and 8 is proportional to the processing time).

On the other hand, the first embodiment shown in FIG.
In the case of, the verification data is divided into the first half and the second half,
Using a bidirectional serial communication line at the same time, transmitting to the second control board → the first control board and the first control board → the second control board, respectively, and simultaneously performing both the first control board and the second control board at the same time Since the verification processing is performed in a specific manner, the serial transmission time, which occupies most of the verification processing time, is halved, and accordingly, the verification processing time can be significantly reduced. It is about half in comparison).

As described above, according to the first embodiment, a plurality of control boards can be provided and connected to each other via a communication line, so that the layout of the control boards can be made more flexible. Even with this configuration, the verification time can be significantly reduced.

(Embodiment 2) Next, using the information processing apparatus 10 configured as shown in FIG.
A download process for transmitting the program data stored in the flash memory 36 from the first control board 12 to the second control board 32 to rewrite the program data in the flash memory 36 will be described below.

In general, flash memory erasing methods include chip erasing in which the entire chip is erased at once, and sector erasing in which the entire chip is divided into several sectors and erased in units of sectors. The relationship between the chip erase time and the sector erase time is (sector erase time × the total number of sectors) (here, the preprogramming is excluded).

When the second control board 32 receives a notification from the first control board 12 that the download mode has been entered, the program necessary for the download process is copied from the flash memory 36 to the RAM 34, and then the program counter is reset. The program is switched to the copied program on the RAM 34 (the process of shifting the second control board 32 to the download mode is completed). Before performing this transition process,
It is necessary to include a process for completing other controls (for example, an OFF process such as a load control). As a result, the process of the second control board 32 only needs to be downloaded, and the capacity of the RAM 34 can be reduced when copying a program necessary for this process.
At the time of downloading, the contents of the flash memory 36 are erased, so that the program using the flash memory 36 cannot be executed. Also, by suppressing the capacity of the RAM 34, as described later, when write data to the corresponding sector during the sector erase of the flash memory is transmitted in advance, the RAM 34 is used as a reception buffer.
It is possible to allocate a large capacity when using the C.34.

When this method is performed, compatibility between at least the download program of the second control board 32 before rewriting (the program executed on the RAM 34) and the download program of the first control board 12 must be compatible. Need to be kept.

FIG. 10 is a flow chart for explaining the operation relating to the rewriting processing of the first control board according to the second embodiment, and the subsequent processing will be described with reference to FIG. In FIG. 10, the processing in the second control plate 32 (not shown) is also described.

First, the sector number is initialized (step S51). Then, from the first control plate 12 to the second
The "sector number" is transmitted to the control board 32 as an erase sector number (step S52), and upon receiving this, the second control board 32 writes the corresponding sector erase command to the flash memory 36. After issuing the sector erase command, the end is monitored by polling. When the end of the erasure is recognized, the fact is transmitted to the first control board 12.

Next, the pointer 5 for reading the download data from the IC card 50 is initialized to the head address of the corresponding sector (step S53). The relationship between the sector number and the start address and end address is determined by the flash memory 16 of the first control board 12 or the IC card 5
0 is stored in the form of a data table.

In step S54, the data of the address of the IC card 50 indicated by the pointer 5 is read, and it is determined whether or not the RAM 34 of the second control board 36 is full. The read data is transmitted to the second control board 36 (step S56).

Next, the pointer 5 is incremented (step S57), and it is checked whether or not the current sector number of the incremented pointer 5 is the last address (step S58). If not, the above operation is repeated.

Since the capacity of the reception buffer (RAM 34) for temporarily storing the reception data of the second control board 36 has an upper limit, the transmission is temporarily stopped when the reception buffer becomes full (step S55). The timing at which this transmission is temporarily stopped includes the sector erase time,
It differs depending on the serial transmission rate, sector capacity, and the like.

If the data transfer for one sector has been completed, the process waits for the end of the sector erase and the end of the writing of the sector (step S59). In the second control plate 32,
When the sector erase is completed, a process of writing the received download data to the sequentially erased sector is performed. When a space is left in the reception buffer due to the writing operation, the reception buffer ready is transmitted to the first control board 12.
This affects step S55. When the writing to the corresponding sector is completed, the first control board 12
Send to

In step S58, if the writing to the sector is completed and the answer is YES, it is determined whether or not the last sector has been completed (step S60). If completed, the flowchart ends, but if not, the flowchart ends. For example, after the sector number is incremented (step S61), the process returns to step S52, and is repeated until the writing to the last sector is completed.

Next, the difference in the download processing time between the second embodiment and the comparative example will be described with reference to FIGS. FIG. 11 is a diagram of a comparative example showing a flash memory access time and a serial transmission time when rewriting program data by serially transmitting download data by performing chip erase of the flash memory. FIG. 12 is a diagram of the second embodiment showing the flash memory access time and the serial transmission time when all data in the sector cannot be sent during the erase period by erasing the sector of the flash memory. FIG.
FIG. 8 is a diagram of the second embodiment showing a flash memory access time and a serial transmission time when a flash memory is sector erased and all data in the sector can be sent during the erase period.

In the comparative example shown in FIG. 11, the chip erase of the flash memory 36 is performed during the period E, and the data is not written into the flash memory 36 while serially transmitting the download data after the erase is completed (S in the figure). (W in the figure), the serial data transmission time (S), which takes the longest time, and the erase period (E) cannot be processed in parallel, so that the download time is extremely long. Although the write time (W) to the flash memory and the serial data transmission time (S) are indicated by the same time, they are for writing the transmitted data, and are compared with the actual write time (W). Then, the transmission time of serial data per byte is much longer.

On the other hand, looking at the download time according to the second embodiment, as shown in FIG. 12, the sector capacity of the flash memory is large, the serial communication rate is slow, When the reception buffer is small, all data in the corresponding sector cannot be serially transmitted (S1, S2, S3) during the erase period (E1, E2, E3). However, compared with the case of FIG. It can be seen that the download time has been significantly reduced.
This employs a sector erase, and the write time (W1, W2, W3) and the erase time (E) are processed in parallel with the time-consuming serial data transmission time (S1, S2, S3). It depends.

Also, in the case of FIG. 13, contrary to FIG.
If the sector capacity of the flash memory is small, the serial communication rate is high, or the reception buffer of the second control board is large, all data in the sector is serially transmitted during the erase period (E1, E2, E3). (S1, S
2, S3), and the serial transmission time and the writing time (W1, W2,
W3) is no longer affected. For this reason, more efficient download can be performed, and the download time can be further reduced.

In the case of FIG. 13, the first control plate 12
There is no time difference from the case where the C card 50 is downloaded in a configuration directly connected via the CPU bus. This is because the breakdown of the download time is occupied only by the erase (E) and write time (W) of the flash memory.

As described above, according to the second embodiment, a plurality of control boards can be provided and connected to each other via a communication line, so that the layout of the control boards can be made more flexible. Even with the configuration, it is possible to rewrite (download, etc.) a program with a time efficiency.

[0080]

As described above, according to the first aspect of the present invention, a plurality of control boards can be provided and connected to each other by a communication line, so that the layout of the control boards can be made more flexible. Even with the above configuration, the verification time can be greatly reduced.

Further, according to the second aspect of the present invention, a plurality of control boards can be provided and connected to each other by a communication line, so that the layout of the control boards can be given a degree of freedom. Even in this case, it is possible to rewrite (download, etc.) the program with a time efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an information processing apparatus according to a first embodiment.

FIG. 2 is a flowchart illustrating an IC card data transmission process of a first control board.

FIG. 3 is a flowchart of a verifying process of a second control board.

FIG. 4 is a flowchart of an IC card data transmission process of a second control board.

FIG. 5 is a flowchart of a verifying process of a first control board.

FIG. 6 is a flowchart of a verify end process of a first control board.

FIG. 7 is a diagram of a comparative example showing a transmission time and a verify processing time when all programs are transmitted from the flash memory of the second control board to the first control board and the first control board performs a verify process;

FIG. 8 is a diagram of a comparative example showing a transmission time and a verification processing time when all programs are transmitted from the IC card of the first control panel to the second control panel and the second control panel performs a verify process.

FIG. 9 is a diagram of the first embodiment showing a transmission time and a verify processing time when verify data is divided into two and verify processing is simultaneously and concurrently performed on a first control board side and a second control board side;

FIG. 10 is a flowchart illustrating an operation related to a rewriting process of a first control board according to the second embodiment.

FIG. 11 is a diagram of a comparative example showing a flash memory access time and a serial transmission time when rewriting program data by serially transmitting download data by performing chip erase of the flash memory.

FIG. 12 is a diagram illustrating a flash memory access time and a serial transmission time when a flash memory is sector erased and all data in the sector cannot be transmitted during an erase period according to the second embodiment.

FIG. 13 is a diagram illustrating a flash memory access time and a serial transmission time in a case where the flash memory is sector-erased and all data in the sector can be transmitted during the erase period according to the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Information processing apparatus 12 1st control board 14,34 RAM 16,36 Flash memory 18,38 UART 20,40 CPU 32 2nd control board 60 Serial line 50 IC card

Claims (2)

[Claims] 1. A first control board and a second control board are connected to each other by a bidirectional communication line, the second control board has a rewritable memory, and the first control board is the second control board. A memory rewriting method having an interface for taking in rewriting data for rewriting the contents of a rewritable memory, wherein the rewriting data taken into the first control board via the interface and the rewritable memory of the second control board are rewritten. In performing verification with the subsequent data, the verification data is divided into at least two address groups, and the rewrite data for each address belonging to the one address group is transmitted from the first control board to the second address group via the communication line. Transmitting to the control board and comparing with the contents of the rewritable memory of the second control board after rewriting; Rewriting data that is transmitted from the second control board to the first control board for each address belonging to the other address group from the second control board to the first control board via a communication line; A memory rewriting method, wherein a process of comparing with a process is performed in parallel. 2. A first control board and a second control board are connected to each other by a bidirectional communication line, the second control board has a flash memory, and the first control board is a flash memory of the second control board. In a memory rewriting method having an interface for taking in rewriting data for rewriting the contents of a flash memory, when rewriting contents of the flash memory using rewriting data taken into the first control board through the interface, Erasing the memory of the flash memory in the control board is performed in units of a predetermined unit, and the first operation is performed during the erasing of the memory in the predetermined unit.
Transmitting rewriting data taken by the control board through the interface from the first control board to the second control board;
A memory rewriting method, wherein data is rewritten for each unit of a flash memory for which memory erasure has been completed.