JP2000241797A - Active matrix type liquid crystal display device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an effect due dispersion in an offset voltage of an amplifier of a data driver circuit and to simplify circuit constitution. SOLUTION: Two pixel TXTs Mpa, Mpb are provided on each pixel PIX of this device, and two pieces of data signal lines DBA, DBB are provided at every pixel column, and these two pieces of data signal lines DBA, DBB are connected to respective the pixel TFTs Mpa, Mpb. One horizontal interval inputted with a video signal by one pixel row id bisected, and in one period, a reference voltage is applied to both of two pieces of data signal lines DBA, DBB at every pixel column, and in the other period, the video signal is applied to only either one side of two pieces of data signal lines DBA, DBB, and in one horizontal period, the potential of a gate signal line GA of a pixel row to be displayed is made the potential that the pixel TFTs Mpa, Mpb connected to the gate signal line GA become in a conductive state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art A TN (Twisted Nematic) mode active matrix type liquid crystal display device has a higher contrast ratio than a liquid crystal display device using other modes, so that a direct-view type liquid crystal display such as a notebook PC display can be obtained. It is widely used for display devices and projection type liquid crystal display devices such as light valves of projectors.

In addition, an active element, a TFT (Thin Fi
When a poly-Si (polysilicon) TFT is used as an lm transistor, a data driver circuit and a gate driver circuit for driving a data line and a gate line of a pixel matrix can be manufactured on the same substrate as a pixel. In particular, those with built-in sample holder and amplifier as data driver circuit
Active research has been actively conducted since an external circuit for driving a liquid crystal display device can be simplified, and a high-definition, large-area liquid crystal display device can be driven at high speed.

A conventional example of such a liquid crystal display device is shown in FIG.
Shown in This is the pixel TFT Mp, pixel capacitance Clc, storage capacitance Cst
Pixel matrix 1 in which pixels PIX are arranged vertically and horizontally
And a data driver circuit 2 for driving the data lines DB of the pixel matrix 1 and a gate driver circuit 3 for driving the gate lines GA are manufactured on the same TFT substrate as the pixel matrix 1. A counter electrode common to all pixels is formed on a counter substrate facing the TFT substrate with the liquid crystal interposed therebetween, and a potential called Vcom is supplied to the counter electrode from the outside (both are not shown). ).

A data driver circuit 2 formed on a TFT substrate includes a scanning circuit, a TFT Msp, and a capacitor Csp. The sample driver circuit 2 sequentially samples the voltage of the video signal line SIG at an output SMP of the scanning circuit. TFT Mtr that transfers the voltage of the hold circuit to the storage capacitor Ctr, the storage capacitor
A holding unit composed of TFT Mrs that resets Ctr, an amplifier Amp that writes the voltage held in this holding unit to a data line
It is composed of

A method of driving the liquid crystal display device will be described with reference to a timing chart shown in FIG. The video signal input to the liquid crystal is sequentially applied in synchronization with the reference clock Cdot every horizontal period for each row of the liquid crystal display device. The scanning circuit uses a sampling pulse in synchronization with the clock Cdot.
Output SMP sequentially. Then, the video signal wiring SIG
Are sequentially sampled by the sample and hold circuit.

After the video signal for one row is sampled, the TFT Mtr is turned on, so that the video signals sampled by all the sample and hold circuits are simultaneously transferred to the holding unit. Here, immediately before this transfer is performed, the storage capacitor Ctr is reset by the TFT Mrs. Then, the amplifier simultaneously writes the video signals transferred to the holding units to all the data lines DB.

At this time, the gate line GAn is connected to the pixel TFT M
Assuming that the voltage is such that p is turned on, the video signal written to the data line DB is supplied to the pixel capacitance through the pixel TFT Mp.
It is written to Clc and the storage capacity Cst. By performing such an operation for all the pixel rows, a two-dimensional image can be displayed.

[0009]

However, the conventional liquid crystal display device has the following problems. First, the number of amplifiers Amp in the data driver circuit is required to be equal to or greater than the number of data lines. However, if offset variations occur in these amplifiers, the variation component is added to the video signal applied to the pixel and the correct voltage is written. The problem is that it is no longer possible. The permissible value of the variation of the video signal voltage input to the liquid crystal pixels is said to be several tens mV or less,
-It is extremely difficult to suppress the variation to less than tens of mV with the amplifier using the Si TFT due to the variation in the threshold voltage of the TFT.

Secondly, in a liquid crystal display device, it is necessary to perform an alternating-current drive for driving the polarity of the voltage applied to the liquid crystal to change for each frame. It is necessary to generate a signal having a negative polarity and a signal having a negative polarity.

FIG. 16 shows a video signal when a certain pixel displays black on frame n-1, white on n, and white on n + 1. As described above, even when displaying the same white, different voltages must be applied between the frames n and n + 1 so that the polarity is inverted with respect to the potential Vcom of the counter electrode. As described above, there is a problem that an external circuit is complicated to generate a video signal having two polarities.

The present invention has been made in view of the above problems, and has as its object to suppress the influence of variations in offset voltage of an amplifier of a data driver circuit and to simplify the circuit configuration. An object of the present invention is to provide an active matrix type liquid crystal display device which can be achieved and a driving method thereof.

[0013]

Means for Solving the Problems In order to solve the above problems, the present invention has the following constitution. The gist of the invention described in claim 1 is that a plurality of data signal lines, a plurality of gate signal lines provided to intersect these data signal lines, and a vicinity of an intersection of the data signal lines and the gate signal lines are provided. ,
In an active matrix liquid crystal display device including pixels arranged in a matrix, each pixel includes a plurality of sub-pixels, and each sub-pixel is connected to a different data signal line,
Further, there is an active matrix liquid crystal display device characterized in that different signals are supplied to the sub-pixels within one horizontal period in which a video signal for one pixel row is input. The gist of the invention according to claim 2 is that a plurality of data signal lines, a plurality of gate signal lines provided to intersect with the data signal lines, and a plurality of data signal lines are provided near an intersection of the data signal lines and the gate signal lines. , An active matrix type liquid crystal display device having pixels arranged in a matrix, the pixel has two pixel transistors and has two data signal lines for each pixel column, and these two data signal lines Is connected to each of the pixel transistors,
An active matrix liquid crystal display device is characterized in that either a reference voltage or a video signal is supplied to two data signal lines for each pixel column. The gist of the invention described in claim 8 is a method for driving an active matrix type liquid crystal display device having the configuration described in claim 2, wherein one horizontal period in which a video signal for one pixel row is input is divided into two. Then, in one period, a reference voltage is applied to both of the two data signal lines for each pixel column, and in the other period, a video signal is applied to only one of the two data signal lines. During the period, the potential of a gate signal line of a pixel row to be displayed is set to a potential at which a pixel transistor connected to the gate signal line is turned on. Exist.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration diagram of an active matrix type liquid crystal display device and a data driver circuit of the present embodiment.

Each pixel PIX constituting the pixel matrix 10 of the liquid crystal display device of the present embodiment has two pixels TFT Mpa, Mp
b, two pixel capacitances Clca and Clcb composed of two pixel electrodes and a counter electrode, and two storage capacitances Csa and Csb. This liquid crystal display device has two data lines for each pixel column.
The pixel TFT Mpa of each pixel has a drain terminal connected to the data line DBA, and a pixel TFT Mpb has a drain terminal connected to the data line DBB. In addition, pixel TFT Mpa,
The gate terminal of Mpb is connected to a gate line GA provided for each pixel row. Capacitance Cp connected to data lines DBA, DBB
“a” and “Cpb” indicate parasitic capacitances due to the overlap between the data lines DBA and DBB and the gate lines GA and the like, respectively.

FIG. 2 schematically shows a layout for one pixel of the liquid crystal display device. Pixel capacitance Cpa, Cpb
Are respectively formed by the overlap between the TFT substrate pixel electrode A and the counter substrate pixel electrode and the overlap between the TFT substrate pixel electrode B and the counter substrate pixel electrode.

FIG. 3 shows a cross section taken along the dotted line in FIG. The opposing substrate pixel electrode is separated for each pixel and is electrically separated from the surrounding opposing substrate pixel electrode. In such a configuration,
The pixel capacitors Clca and Clbc are connected in series by a counter substrate pixel electrode, and both ends thereof are driven by the pixels TFTMpa and Mpb. That is, the equivalent circuit for one pixel is configured as shown in FIG.

The data lines DBA and DBB and the gate line GA of the liquid crystal display are driven by a data driver circuit 11 and a gate driver circuit 12, respectively. The data driver circuit 11 includes a sample holder capable of sampling and holding a video signal for one row, an amplifier Amp equal to or more than the number of pixel columns of the liquid crystal panel, and a switch for switching the input of the amplifier between the reference voltage Vref and the output of the sample holder. SWin is composed of switches SWda and SWdb which divide the output of the amplifier into two and control the conduction between the respective output terminals and the amplifier. The switch SWin is controlled by a signal SLI, and SWda and SWdb are controlled by signals SLDA and SLDB, respectively.

Next, the liquid crystal display device and the data driver circuit 1 of the present embodiment will be described with reference to the timing charts of FIGS.
The operation method 1 will be described.

FIG. 5 is a timing chart for writing a video signal to the pixel column of the n-th row of the odd-numbered frame, and FIG. 6 is a timing chart for writing the video signal to the pixel column of the n-th row of the even-number frame. The chart is shown. The sample holder outputs the video signal held at each output terminal in synchronization with the horizontal synchronization signal Hsync.

In this embodiment, the horizontal synchronization signal Hsync
Period TH (the period of the nth row is represented as THn) for two periods
Divide into Tref and Tsig. In the period Tref, the switch SWin is switched by the control signal SLI, and the reference voltage supplied from the wiring REF is input to the amplifier. In the period Tsig, the output of the sample holder is input to the amplifier.

As shown in FIG. 5, in the odd frame, the period
At Tref, switches SWda and SWdb are both conductive, and
In Tsig, only the switch SWda is made conductive. Then
The data line DBA supplies the reference voltage Vre to the amplifier during the period Tref.
The amplifier output voltage when f is input is applied, and the period Tsig
In, the amplifier output voltage when the video signal Vsig output from the sample holder is input to the amplifier is applied. On the other hand, the amplifier output voltage when the reference voltage Vref is input to the amplifier during the period Tref is applied to the data line DBB,
In the period Tsig, since the switch SWdb is in a non-conductive state, the period
The amplifier output voltage written in Tref is held.

At this time, assuming that the gate line GAn of the n-th pixel row is at a potential that turns on the pixel TFTs Mpa and Mpb,
The pixel TFTs Mpa and Mpb are turned on, and the voltages of the data lines DBA and DBB are applied to the nodes a and b at both ends of the pixel capacitors Clca and Clcb.

Here, assuming that the output voltages when Vref and Vsig are input to the amplifier are V'ref and V'sig, respectively, the voltages Vlca and Vlcb across the pixel capacitors Clca and Clcb are expressed as follows. . At this time, the voltage is a potential on the TFT substrate side viewed from the counter substrate side.

(Equation 1)

When the areas of the TFT substrate pixel electrodes A and B are equal, Clca = Clcb, and the voltages Vlca and Vlcb are as follows.

Vlca = 1/2 (V'sig-V'ref) (3) Vlcb = -1 / 2 (V'sig-V'ref) (4) Therefore, each of the two divided pixels Then, a voltage that is half the difference voltage between the video signal and the reference signal is written.

On the other hand, as shown in FIG. 6, in an even-numbered frame, both switches SWda and SWdb are turned on during a period Tref, and only the switch SWdb is turned on during a period Tsig. Then, the output voltage when the reference voltage Vref is input to the amplifier in the period Tref is applied to the data line DBA, but in the period Tsig, SWda is turned off so that the period Tref
Is held. On the other hand, the data line DBB
During the period Tref, the output voltage when the reference voltage Vref is input to the amplifier is applied, and during the period Tsig, the amplifier output voltage when the video signal Vsig, which is the output of the sample holder, is input to the amplifier.

At this time, the gate lines GAn are connected to the pixel TFTs Mpa and Mpb.
Is at the potential to turn ON the pixel TFT Mpa, M
pb is turned ON, and the voltage of the data lines DBA and DBB is
The voltage is applied to both ends of Clca and Clcb, and the applied voltage is expressed as follows as in the odd frame.

## EQU3 ## Vlca = -1 / 2 (V'sig-V'ref) (5) Vlcb = 1/2 (V'sig-V'ref) (6) It has been done.

Here, when the gain of the amplifier is 1, the voltage shown in FIG. 7 is applied as the video signal Vsig. This means that a pixel is black at frame n-1, white at n, n + 1
5 shows a video signal when displaying white at the time of.

Assuming that the voltage required for displaying black on the liquid crystal pixels is Vblack, and the voltage required for displaying white is Vwhite, 2Vblack + Vref for frame n-1 and 2Vblack for frame n
2Vwhite + Vref, 2Vwhite + Vref for frame n + 1
Give as g. Then, as is apparent from substituting these values into Equations (3) to (5), when displaying black, Vblack
However, when displaying white, Vwhite is written. In addition, driving in which the polarity of the voltage applied to the pixel capacitance is inverted between the odd frame and the even frame can be realized.

Since the liquid crystal display device of the present embodiment is operated by the driving method shown in FIGS. 5 to 7 using the data driver circuit of the present embodiment, the following effects can be obtained.

First, even when offset variations occur in the output of the amplifier, the voltage written to the liquid crystal pixels is not affected by the variations. The data driver circuit 11 has the same number or more amplifiers as the number of data lines of the liquid crystal display device, but it is assumed that the offset voltage varies between the amplifiers. The output of the amplifier is
It can be expressed as (7).

Vout = α × Vin + Vof (7) where Vout is the output voltage of the amplifier, α is the gain of the amplifier, Vin is the input voltage of the amplifier, and Vof is the offset voltage of the amplifier. By performing the operation described above, the voltages applied to the pixels in the even-numbered frame and the odd-numbered frame are obtained by substituting equation (7) into equations (3), (4), (5), and (6). And is described as follows:

(Equation 5)

Therefore, even if the offset voltage Vof of the amplifier varies, the offset voltage is canceled by the voltage applied to the liquid crystal layer, so that a correct voltage can always be applied. Therefore, even when an offset voltage error occurs in the amplifier, it is possible to apply a correct voltage to the liquid crystal, and it is possible to easily design the amplifier circuit and reduce the cost.

Second, the liquid crystal can be AC driven without generating a video signal voltage having a positive polarity and a video signal voltage having a negative polarity with respect to the potential of the counter electrode. This is apparent from the fact that, as described in the description of the operation, the polarity of the applied voltage of the pixel divided into two in the odd frame and the even frame is different. As a result, AC driving can be realized without generating a positive / negative video signal by an external circuit or a data driver circuit, thereby simplifying the circuit. The AC driving method realized at this time is equivalent to the frame inversion driving. Therefore, in the present invention, in order to drive the liquid crystal by alternating current, a video signal having a positive polarity / negative polarity with respect to the counter electrode potential is generated by an external drive circuit or a data driver circuit. Since AC driving can be realized without generating a video signal, simplification of an external circuit or a data driver circuit can be realized, and the cost of a liquid crystal display device can be reduced.

Next, another operation method of the liquid crystal display device and the data driver circuit of the present embodiment will be described with reference to the timing chart of FIG.

As in the case of the previous operation method shown in FIGS. 5 to 7, it is assumed that the sample holder outputs the video signal held at each output terminal in synchronization with the horizontal synchronization signal Hsync.
Here, the period TH of the horizontal synchronization signal is defined as two periods Tref and
Divide into Tsig. In the period Tref, the switch SWin is switched by the control signal SLI, and the reference voltage supplied from the wiring REF is input to the amplifier.
Enter the output of the holder.

In the horizontal period THn during which the video signal is written to the pixels in the n-th row, both the switches SWda and SWdb are turned on during the period Tref, and only the switch SWda is turned on during the period Tsig. Then, the amplifier output voltage when the reference voltage Vref is input to the amplifier during the period Tref is applied to the data line DBA, and the amplifier output voltage when the video signal Vsig that is the output of the sample holder is input to the amplifier during the period Tsig Is applied. On the other hand, the output voltage when the reference voltage Vref is input to the amplifier in the period Tref is applied to the data line DBB, but the amplifier output voltage written in the period Tref is written in the period Tref because the switch SWdb is turned off in the period Tsig. Will be retained.

At this time, assuming that the gate line GAn of the n-th pixel row is at a potential that turns on the pixel TFTs Mpa and Mpb,
The pixel TFTs Mpa and Mpb are turned on, and the voltages of the data lines DBA and DBB are applied to both ends of the pixel capacitors Clca and Clcb. Here, assuming that the output voltages when Vref and Vsig are input to the amplifier are V'ref and V'sig, respectively, the voltages Vlca and Vlcb across the pixel capacitors Clca and Clcb are equal to the equations (3) and (4). Become.

In the horizontal period THn + 1 in which the video signal is written to the pixels in the (n + 1) th row, the switches SWda and SWdb are provided in the period Tref.
Are turned on, and only the switch SWdb is turned on during the period Tsig. Then, the output voltage when the reference voltage Vref is input to the amplifier is applied to the data line DBA during the period Tref.
The output voltage written to Tref is held. On the other hand, the amplifier output voltage when the reference voltage Vref is input to the amplifier during the period Tref is applied to the data line DBB, and the amplifier output voltage when the video signal Vsig output from the sample holder is input to the amplifier during the period Tsig. Is applied.

At this time, the gate line GAn + 1 of the (n + 1) th pixel row
Is at a potential that turns on the pixel TFTs Mpa and Mpb, the pixel TFTs Mpa and Mpb are turned on, and the data lines DBA and D
The voltage of BB is applied to both ends of the pixel capacitors Clca and Clcb, and the applied voltage is equal to the expressions (5) and (6). By performing such an operation on all the pixel rows, a two-dimensional image can be obtained. Here, the value of the voltage Vsig applied as a video signal is the same as the value shown in the operation description of FIGS. Alternately, the timing at which SWda and SWdb are made conductive between successive frames is alternately switched, so that AC driving can be realized.

Therefore, since the liquid crystal display device of this embodiment is operated by the driving method shown in FIG. 8 using the data driver circuit of this embodiment, the following effects can be obtained.

First, as in the case of the driving methods shown in FIGS. 5 to 7, even when offset variation occurs in the output of the amplifier, the voltage written to the liquid crystal pixels is not affected by the variation.

Second, as in the case of the driving methods shown in FIGS. 5 to 7, the liquid crystal is driven without generating a video signal voltage having a positive polarity and a video signal voltage having a negative polarity with respect to the counter electrode potential. AC drive is possible.

Further, in this driving method, since the data line to which the reference voltage is applied changes every horizontal period,
The voltage applied to the data line in the frame period is constantly fluctuated, and the same effect as the gate line inversion driving which is said to be resistant to vertical crosstalk can be obtained.

(Second Embodiment) FIG. 9 shows a configuration diagram of an active matrix type liquid crystal display device according to the present invention. This is one in which the pixel matrix 10, the data driver circuit 11, and the gate driver circuit 12 for driving the gate lines of the pixel matrix shown in the first embodiment are formed on the same substrate.

FIG. 10 shows a specific embodiment of the data driver circuit 21. This is the scanning circuit, TFT Msp and capacitance Csp
Sample and hold circuit, an N-type TFT Mtr that transfers the voltage of the sample and hold circuit to the storage capacitor Ctr, and a TFT Mrs that resets the storage capacitor Ctr.
It is composed of a holder, a switch composed of TFT Msig and Mref for switching the input of the amplifier, and TFT Mda and Mdb for dividing the output of the amplifier into two and controlling the conduction. The TFT Msp of the sample and hold circuit is driven by the output SMP of the scanning circuit,
TFT Mtr and Mrs are controlled by control lines TRF and RST. Also, TF
T Msig and Mref are controlled by control lines SLSIG and SLREF, and the drain terminal of Mref is connected to the wiring REF. TFT Mda, Md
b is controlled by control lines SLDA and SLDB, and its source terminal is connected to the data lines DBA and DBB of the pixel matrix, respectively.

The gate driver circuit 22 in FIG. 9 has the same number or more output terminals as the number of pixel rows of the pixel matrix 20, is connected to the gate line GA, and is arranged on one side or both sides of the pixel matrix 20.

Here, in FIG. 10, the TFTs Msp, Mtr, Mrs, Msig, and Mref constituting the data driver circuit are represented by N-type TFTs, but may be P-type TFTs or CMOS switches.

Next, an operation method of the liquid crystal display device of this embodiment will be described with reference to timing charts shown in FIGS.

First, the operation of the sample holder will be described. This is regardless of whether the frame is odd or even.
The same operation is performed in all horizontal periods. Cdot is a clock signal synchronized with the timing at which the video signal for one pixel is written to the video signal wiring SIG, and Hsync is a horizontal synchronization signal synchronized with the timing at which the video signal for one row is written to the video signal wiring. The scanning circuit sequentially outputs the sampling pulse SMP in synchronization with the clock Cdot. Then, the video signal is sampled to the capacitor Csp through the TFT Msp. After the video signals for one row have been sampled by all the capacitors Csp, the control signal TRF turns on Mtr, and the voltage of the capacitor Csp is transferred to the capacitors Ctr. At this time, Mt
Immediately before r becomes conductive, Mrs is made conductive by the control signal RST to reset the voltage of the capacitor Ctr. Here, if the capacity is determined so that Csp >> Ctr, Cs
The voltage sampled at p is transferred to Ctr almost as it is.

Next, the operation of the odd frame will be described with reference to FIG. This shows a timing chart when a video signal is written in the pixel column of the n-th row.

As described above, the sample holder simultaneously outputs a video signal sampled every horizontal period by the control signal TRF. The horizontal period synchronized with the control signal TRF is divided into two periods Tref and Tsig.

In the period Tref, the control signals SLSIG and SLREF
Msig is turned off and Mref is turned on. Then, the reference voltage Vref applied to the wiring REF is input to the amplifier.
At the same time, both Mda and Mdb are turned on by the control signals SLDA and SLDB. Then, the output voltage V′ref when the reference voltage Vref is input to the amplifier is written to the data lines DBA and DBB. In the period Tsig, Msig is turned on, Mref is turned off, and Mda is turned on, and Mdb is turned off.
Then, the output voltage V'sig when the video signal Vsig is input to the amplifier is written only to the data line DBA.

Here, the potential of the gate line GAn in the n-th row is
When a voltage is applied from Tref to a period Tsig so that the pixel TFT is turned on, V'sig,
V'ref is written. Then, the voltage between both ends of the pixel capacitances Cla and Clb is calculated by the equation as described in the operation description of the first embodiment.
(3), (4).

Further, the operation of the even-numbered frame will be described with reference to the timing chart of FIG. As in the case of the odd frame, the horizontal period is divided into two periods Tref and Tsig.
In the period Tref, Msig is turned off and Mref is turned on by the control signals SLSIG and SLREF. Then, the wiring RE
The reference voltage Vref applied to F is input. At the same time, both Mda and Mdb are turned on by the control signals SLDA and SLDB. Then, the output voltage V′ref when the reference voltage Vref is input to the amplifier is written to the data lines DBA and DBB.
In the period Tsig, Msig is turned on, Mref is turned off, and Mda is turned off, and Mdb is turned on. Then, the output voltage V'sig when the video signal Vsig is input to the amplifier is written only into the data line DBB.

Here, the potential of the gate line GAn of the n-th row is
When a voltage is applied from Tref to a period Tsig so that the pixel TFT is turned on, V′ref,
V'sig is written. Then, the voltage between both ends of the pixel capacitances Cla and Clb is calculated by the equation as described in the operation description of the first embodiment.
(5), (6). Here, as described in the operation description of the first embodiment, a desired voltage is applied to all pixels by applying a voltage obtained by adding a reference voltage to a voltage twice as high as a voltage to be applied to a liquid crystal pixel as a video signal. Can write.

The liquid crystal display device of the second embodiment is shown in FIG.
Since the driving is performed by the operation method shown in FIG. 12, for the same reason as described in the first embodiment, even when offset variation occurs in the output of the amplifier, the voltage written to the liquid crystal pixels is not affected by the variation. And the effect that the liquid crystal can be AC driven without generating a video signal voltage having a positive polarity and a video signal voltage having a negative polarity with respect to the counter electrode potential.

Next, another operation method of the liquid crystal display device according to the second embodiment will be described with reference to the timing chart shown in FIG.

The operation of the sample holder circuit is shown in FIG.
This is the same as the method shown in FIG. Similarly, the horizontal period is divided into two periods Tref and Tsig. In a period Trefn of writing a voltage to the pixels in the n-th row of the liquid crystal display device, the control signal SL
Msig is turned off and Mref is turned on by SIG and SLREF. Then, the reference voltage V applied to the wiring REF is supplied to the amplifier.
ref is input. At the same time, both Mda and Mdb are turned on by the control signals SLDA and SLDB. Then, the output voltage V′ref when the reference voltage Vref is input to the amplifier is written to the data lines DBA and DBB. In the period Tsign, Msig is turned on, Mref is turned off, and Mda is turned on, and Mdb is turned off. Then, the output voltage V'sig when the video signal Vsig is input to the amplifier is written only to the data line DBA.

Here, the potential of the gate line GAn in the n-th row is
When a voltage is applied from Trefn to a period Tsign so that the pixel TFT is turned on, V'si is applied to nodes a and b, respectively.
g and V'ref are written. Then, the voltage between both ends of the pixel capacitances Cla and Clb is calculated by the equation as shown in the operation description of FIGS.
(3), (4).

Next, in a period Trefn + 1 for writing a voltage to the pixels in the (n + 1) th row, Msig is turned off and Mref is turned on by the control signals SLSIG and SLREF. Then, wiring to the amplifier
The reference voltage Vref applied to REF is input. At the same time, both Mda and Mdb are turned on by the control signals SLDA and SLDB. Then, the output voltage V′ref when the reference voltage Vref is input to the amplifier is written to the data lines DBA and DBB. In the period Tsign + 1, Msig is turned on, Mref is turned off, and Mda is turned off, and Mdb is turned on. Then, the output voltage V'sig when the video signal Vsig is input to the amplifier is written only into the data line DBB.

Here, when the voltage of the gate line GAn + 1 in the (n + 1) th row is applied from the period Trefn + 1 to the period Tsign + 1 so that the pixel TFT is turned on, the nodes a and b Are written with V'ref and V'sig, respectively. Then, the pixel capacity Cl
The voltages at both ends of a and Clb are as shown in Expressions (5) and (6) as described in the operation description of FIGS.

Here, as described in the description of the operation shown in FIGS. 5 to 7, by applying a voltage obtained by adding a reference voltage to a voltage twice as high as a video signal to be applied to the liquid crystal pixels, a desired signal is obtained. Voltage can be written to all pixels.
Alternately, the timing of conducting Mda and Mdb between successive frames is alternately switched, so that AC driving can be realized.

Therefore, the liquid crystal display device of the present embodiment was driven by the operation method shown in FIGS. 11 and 12, and for the same reason as shown in the operation method of FIG. Even if it is, the voltage written to the liquid crystal pixels is not affected by the variation, and without generating a video signal voltage having a positive polarity and a video signal voltage having a negative polarity with respect to the counter electrode potential, Since the liquid crystal can be AC driven and the data line to which the reference voltage is applied changes in each horizontal period, the voltage applied to the data line in one frame period always changes. Thus, an effect similar to that of the gate line inversion driving which is said to be resistant to vertical crosstalk can be obtained.

In the present embodiment, the present invention is not limited to the above-described liquid crystal display device and its driving method, but is applied to an active matrix type liquid crystal display device suitable for applying the present invention and its driving method. can do. As an example, in each of the embodiments described above, a TFT is used as an active element for driving a liquid crystal. However, this TFT may be a so-called α-Si (amorphous silicon) TFT or a poly-Si (polysilicon) TFT. Is a TFT
The present invention is not limited to this, and may be a single crystal silicon transistor.
Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, but can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each figure,
The same components are denoted by the same reference numerals.

[0066]

Since the present invention is configured as described above, it is possible to suppress the influence of the variation in the offset voltage of the amplifier of the data driver circuit and to simplify the circuit configuration. The liquid crystal display device and the driving method thereof can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an active matrix liquid crystal display device and a data driver circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a layout for one pixel of the liquid crystal display device according to the first embodiment.

FIG. 3 is a sectional view taken in the direction of arrows in FIG. 2;

FIG. 4 is a diagram illustrating an equivalent circuit for one pixel of the liquid crystal display device according to the first embodiment.

FIG. 5 is a diagram illustrating an example of an operation method according to the first embodiment, and is a timing chart illustrating an operation method of an odd-numbered frame.

FIG. 6 is a timing chart illustrating an example of an operation method of the first embodiment, the operation method of an even-numbered frame;

FIG. 7 is a diagram illustrating a video signal according to the first embodiment.

FIG. 8 is a timing chart showing another example of the operation method of the first embodiment.

FIG. 9 is a circuit diagram showing a configuration of an active matrix liquid crystal display device and a data driver circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating a configuration of a data driver circuit according to a second embodiment.

FIG. 11 is a diagram illustrating an example of an operation method according to the second embodiment, and is a timing chart illustrating an operation method for an odd-numbered frame.

FIG. 12 is a diagram illustrating an example of an operation method according to the second embodiment, and is a timing chart illustrating an operation method for an even-numbered frame;

FIG. 13 is a timing chart showing another example of the operation method of the second embodiment.

FIG. 14 is a circuit diagram illustrating an example of a configuration of a conventional active matrix liquid crystal display device.

15 is a timing chart showing an example of a method for driving the active matrix liquid crystal display device shown in FIG.

FIG. 16 is a diagram illustrating an example of a video signal.

[Explanation of symbols]

 1, 10, 20 Pixel matrix 2, 11, 21 Data driver circuit 3, 12, 22 Gate driver circuit Amp Amplifier DBA, DBB Data line GA Gate line Mpa, Mpb Pixel TFT PIX Pixel SWin, SWda, SWdb Switch TH Horizontal period Tref , Tsig period

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 2H092 GA21 JA24 JB02 JB46 KA03 KA04 KA05 2H093 NA16 NA33 NA43 NC02 NC12 NC16 NC23 NC34 ND09 ND15 ND35 ND49 NG02 5C006 AA01 AC28 AF44 AF51 AF53 BB14 BB16 FA03 FA25 5C080 AA10 BB05 DD22 DD27 DD29 EE17 FF11 JJ02 JJ03 JJ04 JJ06

Claims (11)

[Claims] 1. A plurality of data signal lines, a plurality of gate signal lines provided to intersect the data signal lines, and a plurality of data signal lines provided in the vicinity of the intersection of the data signal lines and the gate signal lines, and arranged in a matrix. In the active matrix type liquid crystal display device including the divided pixels, each of the pixels includes a plurality of sub-pixels, each sub-pixel is connected to a different one of the data signal lines, and
An active matrix liquid crystal display device wherein different signals are supplied within one horizontal period in which a video signal for a pixel row is input. 2. A plurality of data signal lines, a plurality of gate signal lines provided to intersect these data signal lines, and a plurality of data signal lines provided in the vicinity of the intersection of the data signal lines and the gate signal lines, and arranged in a matrix. An active matrix type liquid crystal display device comprising: a pixel having two pixel transistors and two data signal lines for each pixel column, and the two data signal lines are provided by the pixel An active matrix liquid crystal display device, wherein either one of a reference voltage and a video signal is supplied to each of the two data signal lines connected to each of the transistors and for each pixel column. 3. The active matrix type liquid crystal display device according to claim 2, wherein said pixel transistor comprises one of an amorphous silicon thin film transistor, a polysilicon thin film transistor, and a single crystal silicon transistor. 4. Each of the two pixel transistors is connected to one of two pixel electrodes constituting one pixel, and a pixel electrode of a counter substrate facing the pixel electrode with a liquid crystal layer interposed therebetween. 4. The active matrix liquid crystal display device according to claim 2, wherein each of the pixels is electrically separated and arranged so as to overlap with the two pixel electrodes. 5. A data driver circuit for driving the data signal line, wherein the data driver circuit holds and outputs a video signal for one pixel row.
A holder, an amplifier array including amplifiers equal to or more than the number of pixel columns, a switch array for selectively switching the input of each amplifier to either the output from the sample holder or the reference voltage, and the amplifier And a switch array for controlling the conduction between the data signal lines and the amplifier while distributing the output to the two data signal lines and supplying the data signal lines to the two data signal lines for each pixel column. 5. The active matrix liquid crystal display device according to any one of 2 to 4. 6. The active matrix type liquid crystal display device according to claim 5, wherein said data driver circuit includes a polysilicon thin film transistor or a single crystal silicon transistor. 7. The active matrix type liquid crystal display according to claim 5, wherein said data driver circuit and a gate driver circuit for driving said gate signal line are formed together with said pixels on the same substrate. apparatus. 8. A method for driving an active matrix liquid crystal display device having the configuration according to claim 2, wherein one horizontal period in which a video signal for one pixel row is input is divided into two, and one of the two periods is divided into two. Wherein the reference voltage is applied to both of the two data signal lines for each pixel column, and the video signal is applied to only one of the two data signal lines in the other period, Wherein the potential of a gate signal line of the pixel row to be displayed is set to a potential at which a pixel transistor connected to the gate signal line is turned on. 9. The driving method of an active matrix type liquid crystal display device according to claim 8, wherein the data signal line to which the video signal is applied is switched on a frame basis. 10. The method according to claim 8, wherein the data signal line to which the video signal is applied is switched for each pixel row. 11. A data driver circuit for driving the data signal line, wherein the one horizontal period is an output cycle of the data driver circuit.
0. The driving method of the active matrix type liquid crystal display device according to any one of the above items.