JP2000236360A - Radio receiver and signal processing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain improvement in accuracy as well while attaining the reduction of power consumption concerning a radio receiver capable of receiving the plural channels of different frequencies and selecting the reception channel through digital signal processing. SOLUTION: The power consumption is reduced by performing high-speed and low-bit sampling (a), afterwards, loading filtering through a digital filter (c) after channel selection (b) and reducing a data rate (d) and while paying attention on a narrower frequency band required for processing after demodulation to be performed after the selection of the reception channel in comparison with a frequency band enabling reception as a receiver, the number of bits is increased by utilizing the reduction effect of quantization noises caused by over sampling.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver capable of receiving a plurality of channels of different frequencies, and more particularly to a signal processing method in a radio receiver capable of selecting a reception channel by digital signal processing.

[0002]

2. Description of the Related Art A radio system employing such a radio receiver is called a software radio system. One of the features of the software radio system is that, despite being the same device, communication can be performed with different frequencies and different communication methods by software change.

[0003]

In the field of mobile communication devices such as mobile phones and mobile computers, reduction of power consumption is one of the very important problems. here,
Generally, in the field of the mobile communication devices described above, it is known that power consumption can be reduced by reducing the clock in signal processing.

It is also known that digital signal processing has an advantage that the degree of freedom in processing is higher than analog signal processing. Proposals for reducing power consumption in consideration of the advantages include, for example, Japanese Patent Application Laid-Open No. 6-21 / 1994.
988 (hereinafter, Conventional Example 1) and JP-A-6-291.
Although the invention disclosed in Japanese Patent Publication No. 799 (hereinafter, Conventional Example 2) and the like can be mentioned, the absolute number thereof is relatively small.

[0005] Furthermore, no proposal has been found for improving the accuracy while reducing the power consumption in consideration of the advantages of the digital signal processing described above. The above-mentioned conventional examples 1 and 2 also do not make such a proposal.

Therefore, the present invention considers a new process that takes into account the advantages in digital signal processing. That is, a direct object of the present invention is to improve accuracy while reducing power consumption in a radio receiver capable of receiving a plurality of channels of different frequencies and selecting a reception channel by digital signal processing. It is also to plan.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention roughly performs high-speed, low-bit sampling, performs channel selection, and performs filtering.
By reducing the data rate, power consumption is reduced, and the number of bits is increased to obtain accuracy. Note that, since such processing is premised on an apparatus including a plurality of channel frequencies, it is considered that the processing belongs to the category of FDMA. However, in practice, a channel for performing CDMA and a channel for performing TDMA are also included in the simultaneously receivable band. It goes without saying that it can be included.

[0008] More specifically, the present invention reduces the clock required for signal processing after the data rate is reduced by reducing the data rate, thereby reducing power consumption.

Also, the present invention focuses on the fact that the frequency band necessary for demodulation and subsequent processing performed after selecting a reception channel is narrower than the frequency band that can be received by the receiver, and that oversampling is performed. The number of bits is changed using the effect of reducing quantization noise (more specifically, the number of bits is increased). Accordingly, for the number of bits required for processing after demodulation,
Since the number of bits in the signal processing before A / D conversion and demodulation is reduced, power consumption can be reduced from this point as well.

In the above-described processing, the data rate is reduced and the number of bits is increased after quadrature demodulation or after down-conversion. Further, the reduction of the data rate and the increase of the number of bits may be performed a plurality of times.

Under such a concept, the present invention provides the following first to fifth aspects as means for solving the above-mentioned problems.
To provide a wireless receiver.

That is, according to the present invention, the first radio receiver is a radio receiver capable of receiving a plurality of channel frequencies, and is an A / D converter for A / D converting a received signal.
In a wireless receiver including a converter and a signal processing unit that performs digital signal processing on a signal digitally converted by the A / D converter, the signal processing unit converts a data rate of a digital signal, And a data rate / bit number converter for converting the number of bits of the digital signal.

Further, according to the present invention, as the second radio receiver, a radio receiver capable of receiving a plurality of channel frequencies, wherein the A / D converts a received signal into an A / D signal.
In a wireless receiver comprising a converter and a signal processing unit for performing digital signal processing on a signal digitally converted by the A / D converter, the signal processing unit selects a reception frequency and converts the digital signal into a digital signal. Frequency changing means for selectively changing the frequency, a digital filter for receiving the digital signal whose frequency has been changed, and limiting the band to a specific frequency band, and converting the data rate of the band-limited digital signal and performing the band-limited operation. And a data rate / bit number converter for converting the number of bits of the digital signal.

Further, according to the present invention, as a third wireless receiver, there is provided a wireless receiver capable of receiving a plurality of channel frequencies.
In a wireless receiver including a D converter and a signal processing unit that performs digital signal processing on a signal digitally converted by the A / D converter, the signal processing unit selects a reception frequency and converts the digital signal into a digital signal. Frequency changing means for digitally changing the frequency, a plurality of digital filters, each having a unique frequency band, a digital filter for band-limiting the frequency-changed digital signal, and a plurality of digital filters corresponding to the plurality of digital filters, respectively. And a plurality of data rate / bit number conversion means arranged with the corresponding digital filter at the preceding stage and alternately arranged with the plurality of digital filters,
Data rate / bit number conversion means for converting the data rate of the band-limited digital signal in the corresponding digital filter and also converting the number of bits of the band-limited digital signal; And repeating the data rate conversion and the bit number conversion in the data rate / bit number conversion means a plurality of times.

According to the present invention, as a fourth radio receiver, in any one of the second and third radio receivers, the frequency change in the frequency changing means is orthogonal transform. Is obtained.

Further, according to the present invention, in any one of the first to fourth radio receivers as a fifth radio receiver, the data rate / bit conversion means reduces the data rate. In this manner, the conversion is performed, and the conversion is performed by increasing the number of bits.

Further, the present invention provides a signal processing method in a radio receiver as described below as a specific means for solving the above-mentioned problem under the same concept.

That is, according to the present invention, as a signal processing method in the first radio receiver, an analog filter which receives an input signal containing a plurality of pieces of information having different frequencies and uses the first frequency band as a transmission band is provided. And then subject to sampling and A / D conversion in accordance with a clock having a first frequency to generate a digital signal of the first number of bits, and further select a signal relating to one of the plurality of pieces of information. In a method of digitally processing, a signal having a second frequency lower than the first frequency as a data rate and a second bit number larger than the first bit number as a bit number is processed. As to perform the processing after demodulation, after selecting the signal according to the one information and before demodulating the one information, the signal according to the one information, The second frequency band is narrower than the first frequency band and satisfies the Nyquist condition with respect to the second frequency. Converting the data rate of the received signal into a data rate having the second frequency, and converting the number of bits of the band-limited signal into the second number of bits. A processing method is obtained.

Further, according to the present invention, as a signal processing method in the second wireless receiver, in the signal processing method in the first wireless receiver, the selection of the signal relating to the one piece of information is performed by the first wireless receiver. A signal processing method in a wireless receiver, which is performed by orthogonally transforming the digital signal with a frequency related to information, is obtained.

Further, according to the present invention, as a signal processing method in the third wireless receiver, in the signal processing method in the second wireless receiver, the signal processing method of the second wireless receiver has a half of a width of the second frequency band. The S / N ratio obtained by assuming that the frequency having a value is oversampled at the first frequency increases the number of bits at the time of A / D conversion by a predetermined number of bits from the first number of bits. A signal processing method in a wireless receiver, wherein a sum of the first number of bits and the predetermined number of bits is used as the second number of bits when the S / N ratio is equal to the S / N ratio obtained when Can be

Further, according to the present invention, as a signal processing method in the fourth radio receiver, an input signal including a plurality of pieces of information having different frequencies is received, passed through an analog filter, and has a first frequency. A method of generating a digital signal of the first bit number by sampling and A / D converting in accordance with a clock, and further selectively digitally processing a signal relating to one of the plurality of pieces of information. A signal having a second frequency lower than the first frequency as the rate and having a second bit number larger than the first bit number as a bit number is subjected to processing after demodulation as a processing target. After selecting the signal according to the one information and before demodulating the one information, the signal according to the one information is set to a predetermined frequency band as a transmission band. Applying a filter, performing rate conversion so as to reduce the data rate of the filtered signal to a predetermined frequency at which the predetermined frequency band satisfies the Nyquist condition, and the number of bits of the filtered signal. Performing the process of converting the number of bits so as to increase the number of times by gradually narrowing the predetermined frequency band and lowering the predetermined frequency according to the narrowed predetermined frequency band. Finally, a signal processing method in the wireless receiver is obtained, wherein the signal is converted into a signal having the second frequency as the data rate and the second bit number as the number of bits.

Further, according to the present invention, as a signal processing method in the fifth radio receiver, in the signal processing method in the fourth radio receiver, the selection of the signal relating to the one piece of information is performed in accordance with the one signal. A signal processing method in a wireless receiver, which is performed by orthogonally transforming the digital signal with a frequency related to information, is obtained.

Further, according to the present invention, as a signal processing method in the sixth radio receiver, in the signal processing method in the fifth radio receiver, a value of の of the width of the predetermined frequency band is set. When the S / N ratio obtained by assuming that the frequency having the signal is oversampled at the first frequency is such that the number of bits at the time of A / D conversion is increased by a predetermined number of bits from the first number of bits In the case where the S / N ratio is equal to the number of bits obtained before the filtering, the bit conversion is performed by increasing the number of bits before the filtering to the number of bits given by the sum of the first number of bits and the predetermined number of bits. Thus, a signal processing method in a wireless receiver is obtained.

Further, according to the present invention, as the signal processing method in the seventh radio receiver, the signal processing method in any one of the first and fourth radio receivers may be a signal processing method in the first or fourth radio receiver. The selection is performed by down-converting the frequency of the one piece of information, thereby obtaining a signal processing method in a wireless receiver.

Further, according to the present invention, as the signal processing method in the eighth radio receiver, an input signal including a plurality of pieces of information having different frequencies is received, and after passing through an analog filter, the first frequency is changed. A digital signal of the first bit number is generated by performing sampling and A / D conversion in accordance with a clock having the same, and further by orthogonally converting the digital signal with a frequency related to the one information,
In the method of selecting a signal related to one of the plurality of pieces of information and digitally processing the selected signal related to the one piece of information, the data rate may include a second frequency lower than the first frequency. And, in order to perform processing after demodulation as a processing target for a signal having a second bit number larger than the first bit number as a bit number, after selecting a signal related to the one information, Before demodulating the one piece of information, the signal related to the one piece of information is filtered using a predetermined frequency band as a transmission band, and the predetermined frequency band is set to a predetermined frequency that satisfies the Nyquist condition. Rate-converting the data rate of the filtered signal so as to reduce the data rate; The S / N ratio obtained by assuming that oversampling is performed at the wave number is the same as the S / N ratio obtained when the number of bits at the time of A / D conversion is increased by a predetermined number of bits from the first number of bits. In the case of equality, bit conversion is performed by increasing the number of bits of the filtered signal and the number of bits given by the sum of the first number of bits and the predetermined number of bits. And performing a series of processes for performing bit conversion when possible, a plurality of times by gradually narrowing the predetermined frequency band and lowering the predetermined frequency according to the narrowed predetermined frequency band. And finally converting the data rate into a signal having the second frequency as the data rate and the second bit number as the number of bits. Signal processing method in the receiver is obtained.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) As shown in FIG. 1A, a radio receiver according to a first embodiment of the present invention generally includes an analog filter 101 for limiting the band of an input signal, , An A / D converter 102 which samples an input signal and converts it into a digital signal, and an A / D converter 102
And a signal processing unit 104 for performing digital signal processing.

Here, the signal processing unit 104 may be realized by software or may be configured as hardware. When realized by software, the signal processing unit 104 includes, for example, a digital signal processor (DSP: Digital Sig).
nal Processor) or CPU (Cen
Tral Processing Unit) and RO
M (Read-Only Memory) and RAM
(Ramdom-Access Memory). On the other hand, when implemented by hardware, the signal processing unit 104 includes, for example, a gate array (G / A) or an FPGA (Field Programmable G).
a.Array). In particular, software-based or E ² P
In the case of being constituted by an FPGA composed of a rewritable ROM such as a ROM, a program relating to the digital signal processing can be easily changed, such as changing specifications.

More specifically, the signal processing unit 104 controls the A /
A quadrature demodulation unit 105 for quadrature demodulating the digital data 117 received from the D converter 102;
10, a data rate / bit number conversion unit 111, a demodulation unit 112, a next-stage signal processing unit 113 for performing conventional signal processing such as decoding, a quadrature demodulation unit 105, a demodulation unit 112, and a next-stage signal processing unit Control unit 11 that controls 113
4 is provided.

The quadrature demodulation unit 105 includes a mixer 106
107, a digital oscillator 109, and a π / 2 shift unit 108.

The components provided between the quadrature demodulation unit 105 and the demodulation unit 112, that is, the digital filter 1
10 and the data rate / bit number converter 111 are actually provided one for each of the I and Q signals, but for simplicity of description, FIG.
In the above, two signals are input to and output from one block.

Hereinafter, with respect to the radio receiver according to the present embodiment having such a configuration, the signal processing method executed therein will be further described with reference to FIGS. 1 (b), 2 (a) to 2 (d) and FIG. This will be described in detail. In the following, the radio receiver can select and receive several different channels within the range of the receivable frequency band B, and a specific frequency belonging to the receivable band B. illustrate the operation of the case of selecting receiving the f _IF.

When the analog input signal 115 is input to the analog filter 101, the band is limited there. Here, the analog filter 101 has a receivable frequency band B
Is a pass band.

[0034] Next, signal 116 is band-limited by an analog filter 101, the sampling clock generation sampling frequency f _s in the oscillator 103, is sampled in the A / D converter 102 are quantized.

Here, the sampling frequency f _s is
According to Nyquist's theorem, the frequency must be at least twice the receivable band B (see FIG. 2A). At this time, as shown in FIG. 1 (b), the data rate of the signal 117 is the sampling frequency f _s, the number of bits M
It is. Further, as shown in FIG. 2 (a), selectively receivable frequency channels in the present embodiment, the frequency f _IF1, the frequency f _IF2, and a frequency f _IF, these, in the following, It is assumed that a channel having the frequency _fIF is selectively received and subjected to signal processing.

When the signal 117 (data rate: f _s ) sampled by the A / D converter 102 enters the signal processing unit 104, first, the signal is orthogonalized by the orthogonal demodulation unit 105 at the frequency of the channel desired to be selected. Is converted.

Here, two mixers 106 and 107,
A quadrature demodulation unit including a π / 2 shift unit and a digital oscillator 109 is controlled by a control unit 114 so as to select a frequency _fIF to be received and perform quadrature demodulation. Specifically, the control unit 114 controls the digital oscillator 109 is set to f _IF you want to select the oscillation frequency. As a result, as shown in FIG. 2B, a frequency channel of f _IF is received. FIG. 2 (b)
In the quadrature demodulation unit 105, the reception frequency f
Mixers 106 and 107 to drop _IF to baseband
Signals 118 and 119 after passing through are shown. Further, I and Q signals 118 and 119 generated by quadrature demodulation.
Are not shown separately since they both have the same frequency change.

The I signal 118 obtained by this quadrature demodulation
And the Q signal 119 are respectively transmitted to the digital filter 110
And the band is limited by the digital filter 110. Here, transmission range of the digital filter 110, as shown in FIG. 2 (c), in the frequency band B _0. In the present embodiment, since digital filter 110 has only one stage, frequency band B ₀ is a band required for demodulating the reception channel of the selected frequency _fIF .

The signals 120 and 121 band-limited by the digital filter 110 enter a data rate / bit number converter 111. Data rate / bit number converter 1
11 receives the signals 120 and 121, performs data rate conversion and conversion of the number of bits, and makes the data rate f
a _s0 bits are M ₀ output signal 122 and the 12
3 is output. This data rate f _s0 and the number of bits M ₀
Is the data rate and the number of bits required for signal processing after the demodulation section 112 provided at the subsequent stage of the data rate / bit number conversion section 111. In particular, the data rate f _s0
, Compared band (B _0/2) required for demodulating the frequency f _IF of the channel, is to frequency viewed Nyquist condition. Further, in the present embodiment, it is assumed that M ₀ = M + 1.

Here, the data rate / bit number conversion unit 1
11, how the data rate is converted and why the number of bits may be increased will be described with reference to FIGS. 2D and 3.

As understood with reference to FIG. 2D, the data rates of the signals 122 and 123 whose data rates have been converted by the data rate / bit number converter 111 are f _s0 . As is apparent from this figure, since the band B ₀ of the digital filter 110 is a value equal to or lower than the data rate f _s0 , the Nyquist condition is satisfied.

As is clear from FIG. 2D, the data rate f _s0 is lower than the sampling frequency f _s . That is, in the processing after the demodulation unit 112, the clock rate can be reduced. Thus, according to the present embodiment, lower power consumption can be achieved.

Next, in this state, the demodulation unit 112
_Attention is paid to the relationship between the data rate required in the subsequent processing, that is, the data rate f _s0 required for processing the selectively received channel f _IF and the sampling frequency f _s in the A / D converter. . Originally, the frequency band required for the processing after demodulation is B ₀ , and the minimum sampling frequency required in accordance therewith may be f _s0 , but the radio receiver has the minimum sampling frequency. It is understood that the state is the same as the state where the oversampling is performed at the frequency f _s which is higher than the frequency f _s0 .

Generally, when oversampling is performed,
It is known that the effect of quantization noise in an A / D converter is reduced. Specifically, as shown in FIG.
When the sampling frequency is increased by performing oversampling, it is possible to reduce quantization noise per unit frequency.

Further, oversampling will be described using mathematical expressions.

Generally, when the required signal band is f _B and the sampling frequency is f _s , it is known that the S / N in the A / D converter is calculated as in the following equation (1). . Note that M is the number of bits in the A / D converter.

[0047]

(Equation 1) When this equation (1) is expressed in dB, the following equation 2 is obtained.

[0048]

(Equation 2) Here, with respect to the Nyquist condition is satisfied required frequency a frequency band of the signal that is actually required as f _B, and having been subjected to the 4-times oversampling. That is, if f _s / (2f _B ) = 4 in the equation (2), A / D
It can be seen that the S / N at the converter is improved by 6 dB. In other words, if oversampling is performed four times, the same accuracy as that obtained when the A / D converter 102 samples at the lowest frequency that satisfies the Nyquist condition for the necessary signal band f _B and generates M + 1-bit digital data is obtained. It is understood that.

Based on this, considering the state before demodulation in the present embodiment, after performing the orthogonal transformation, the signal passes through the digital filter 110 of the band B ₀ .
F _B in Equations (1) and (2) is considered to be １ ／ of B ₀ . For this reason, if the condition represented by f _s = 4 * (B _0/2 ) is satisfied, this is the same as performing 4 times oversampling. That is, the number of bits is 1
Even if the number of bits is increased, no accuracy problem occurs as described above. Therefore, in the present embodiment, the A / D converter 102 is set by setting the band B _{0 of the} digital filter to a value that satisfies the above-described condition of 4 times oversampling.
In the case where the number of bits of the signal 117 sampled and generated in
The number of bits after passing through can be set to M + 1 bits.

That is, according to the present invention, in a radio receiver for selectively receiving a plurality of frequency channels, the frequency band B ₀ required for demodulation of the selected channel is sufficiently sufficient for the frequency band B before A / D conversion. Focusing on the narrowness, utilizing this and applying the effect of reducing the quantization noise by oversampling, the number of bits M in the A / D converter is reduced by the bits used for demodulation of the selected channel. The number M ₀ can be increased. In other words, for the number of bits M ₀ required for demodulation, the A / D converter 1
02, the number of bits M can be reduced.

As is apparent from this, in the present embodiment, it is possible to reduce the power consumption by reducing the clock rate in the processing after the demodulation unit 112, and to improve the accuracy by increasing the number of bits. Note that the simplest method of converting the number of bits in the data rate / bit number conversion unit 111 is to add the target digital data and data obtained by delaying the digital data by one sample to increase the number by one digit.

The signals 122 and 123 whose data rate and the number of bits have been converted by the data rate / bit number converter 111 in this way are input to the demodulator 112. Thus, the selected channel is demodulated, and the demodulated signal 124 is passed to the next-stage signal processing unit 113.

The next-stage signal processing unit 113 is an existing signal processing unit which has been used in the related art, and its components include bit synchronization, decoding, and audio reproduction in a signal format. Then, the next-stage signal processing unit 114 performs sound, light, voice,
FAX data, LCD data, PC data, etc. are output.

The data rate / bit number converter 111
May be performed in the digital filter 110. The concept of such a modification will be described later with reference to the drawings.

(Second Embodiment) As shown in FIG. 4A, a radio receiver according to a second embodiment of the present invention generally includes an analog filter 101 for limiting the band of an input signal, and , An A / D converter 102 which samples an input signal and converts it into a digital signal, and an A / D converter 102
And a signal processing unit 104 for performing digital signal processing.

Here, similarly to the first embodiment, the signal processing unit 104 may be realized by software, or may be configured as hardware.

More specifically, the signal processing unit 104 controls the A /
A quadrature demodulator 105 for quadrature demodulating the digital data 117 received from the D converter 102, a first digital filter 202, and a first data rate / bit number converter 2
03, a second digital filter 204, a second data rate / bit number converter 205, and a demodulator 112.
And a next-stage signal processing unit 113 that performs conventional signal processing such as decoding, and a control unit 114 that controls the quadrature demodulation unit 105, the demodulation unit 112, and the next-stage signal processing unit 113. 4A, similarly to FIG. 1A, the first digital filter 202, the first data rate / bit number conversion unit 203, the second digital filter 204, and the second data rate Bit number converter 2
05 indicates that two signals of I and Q are input and output to and from one block, respectively.

Hereinafter, the signal processing method executed in the radio receiver according to the present embodiment having the above configuration will be described in detail with reference to FIGS. 4 (b) and 5 (a) to 5 (e). I do. In the following, the radio receiver can select and receive one channel from a plurality of different frequency channels within the receivable frequency band B. illustrate the operation of the case of selecting receiving a particular frequency f _IF belonging to.

When the analog input signal 115 enters the analog filter 101, the band is limited there. here,
The analog filter 101 is a filter that uses a receivable frequency band B as a pass band.

[0060] Next, signal 116 is band-limited by an analog filter 101, the sampling clock generation sampling frequency f _s in the oscillator 103, is sampled in the A / D converter 102 are quantized.

Here, the sampling frequency f _s is
According to Nyquist's theorem, the frequency must be at least twice the receivable band B (see FIG. 5A). At this time, as shown in FIG. 4 (b), the data rate of the signal 117 is the sampling frequency f _s, the number of bits M
It is.

When the signal 117 (data rate: f _s ) sampled by the A / D converter 102 enters the signal processing unit 201, first, the quadrature demodulation unit 105 uses the frequency f _IF of the channel desired to be selected. Thus, the orthogonal transform is performed (see FIG. 5B). The selection of the frequency in the quadrature demodulation unit 105 is performed under the control of the control unit 114 in the same manner as in the first embodiment.

The I and Q signals 1 obtained by this quadrature demodulation
18 and 119 are first digital filters 20 respectively.
Enter 2. Here, transmission range of the digital filter 202, as shown in FIG. 5 (c), in the frequency band B _1.

The signals 206 and 207 which have been band-limited by the digital filter enter a first data rate / bit number converter 203. Upon receiving the signals 206 and 207, the first data rate / bit number conversion unit 203
Data rate conversion and conversion of the number of bits are performed, and the output signal 20 having the data rate f _s1 and the number of bits M ₁ is output.
8 and 209 are output (see FIG. 4B).

[0065] Here, B _1/2 is in greater than f _s1 / 2 becomes the aliasing noise is generated. The aliasing noise is a general definition. In digital signal processing, a frequency that does not satisfy the Nyquist definition depending on the sampling frequency, that is, a frequency equal to or more than １ ／ of the sampling frequency generates aliasing noise.

For this reason, if the first data rate / bit number conversion section 203 reduces the data rate f _s1 to a value such that B _1/2 becomes larger than f _s1 / 2, the aliasing noise is reduced. However, even if the condition for aliasing is met at this time, the present embodiment avoids this by setting the second digital filter 204 and the like as described later. can do.

Returning to the description of the operation, signals 208 and 209
Enters the second digital filter 204 and is further band-limited by the second digital filter 204.
Here, as described above, even if the condition that the aliasing noise occurs due to the data rate conversion in the first data rate / bit number conversion unit 203 is satisfied, FIG.
If the signal does not fall on the band of the second digital filter 204, as shown in FIG.
Is as shown in FIG. 5E, and it can be seen that the aliasing noise does not affect the characteristics.

The signals 210 and 211 band-limited by the second digital filter 204 are converted to the second data rate
The operation enters the bit number conversion unit 205. When receiving the signals 210 and 211, the second data rate / bit converter 111 performs data rate conversion and bit number conversion, and outputs the output signal 12 having a data rate of f _s0 and a bit number of M _0.
2 and 123 are output. The data rate f _s0 and the number of bits M ₀ are the data rate and the number of bits required for signal processing after the demodulation unit 112 in the subsequent stage, similarly to those in the first embodiment.

The details of the data rate conversion and bit number conversion in the first and second data rate / bit number conversion units 203 and 205 are described in detail in the data rate / bit number conversion unit 111 in the first embodiment. The description is omitted because it is similar to that.

The signals 122 and 123 whose data rate and bit number have been converted by the second data rate / bit number conversion section 205 in this manner are input to the demodulation section 112. Thereby, the selected channel (frequency f _IF )
Are demodulated, and the demodulated signal 124 is passed to the next-stage signal processing unit 113.

The next-stage signal processing section 113 is an existing signal processing section in the related art, and its components include bit synchronization by a signal format, decoding, and audio reproduction. Then, the next-stage signal processing unit 114 performs sound, light, voice,
FAX data, LCD data, PC data, etc. are output.

As in the first embodiment, the data rate / bit number conversion in the first data rate / bit number conversion section 203 is performed by the first digital filter 202.
, Or the conversion in the second data rate / bit number conversion unit 205 may be performed in the second digital filter 204.

Next, the digital filters (first and second digital filters) and the data rate / bit number conversion unit (first and second data rate / bit numbers) in the first and second embodiments described above. FIGS. 6 and 7 show the specific configuration of the conversion unit and the specific configuration in the case where the data rate conversion and the bit conversion attached at the end of each embodiment are also performed in the digital filter. This will be described in detail with reference to FIG. FIG. 6 shows that an input signal having a data rate f _s and the number of bits M is converted to a data rate f _s / 2
FIG. 7 shows a specific configuration when the number of bits is M + 1,
_Shows a specific configuration in a case where an input signal having a data rate f _s · number of bits M is set to a data rate f _s / 4 · number of bits M + 1.

Referring to FIG. 6 (a), the digital filter 301 and the data rate are set to 1/2 and the number of bits is set to 1
An increasing data rate / bit number converter 302 is shown. In FIG. _6A , the input signal 303 having the data rate f _s and the number of bits M is band-limited by the digital filter 301, but the output signal 304 is still
The data rate f _s and the number of bits M remain. When the signal 304 is input to the data rate / bit number conversion unit 302, the data rate conversion and the bit number conversion are performed as described above. As a result, the data rate of the output signal 305 becomes f _s / 2, and the number of bits becomes M + 1.

Further, referring to FIG. 6B, FIG.
A circuit block in which the digital filter 301 and the data rate / bit number conversion 302 shown in FIG. Here, CLK1 and CLK2 shown in FIG. 6B are clocks for operating these logic circuits, and the timing is CLK1 and CLK2.
= Is the data rate _{f s, CLK2 = f s /} 2.

Assuming that the digital filter 301 shown in FIG. 6A is an FIR filter having n taps, the digital filter 301 has n shift registers D ₀ as shown in FIG. 6B. To D _n−1 , and mixers 307, 308,
309 and an adder 310 for adding n data. At this time, the coefficient of n mixers, respectively, a b ₀ ~b _n-1. These b _{0 to} b _n-1 are coefficients for constituting the digital filter 301 together with the signal delay constituted by the shift register 306.

The n output signals of these shift register rows 306 are multiplied by the coefficients (b _{0 to} b _n-1 ) assigned to the respective mixers in the corresponding mixers. Further, the outputs from the n mixers are added by an adder 310, whereby a band-limited output signal 304 is output.
Get.

On the other hand, in FIG. 6B, the data rate / bit number converter 302 shown in FIG. 6A includes a shift register (Y ₀ ) 311 and a shift register (Y ₁ ) 31
2 and an adder 313. Further, in this example, the data rate of the output signal 305 is set to f _s / 2 by the adder 313 operating at CLK2.
It should be noted that the other parts are CLK1 as is apparent from the figure.
Works with

Referring to FIG. 6C, a data rate / bit number conversion filter 314 having a function equivalent to the combination of the digital filter 301 and the data rate / bit number conversion unit 302 shown in FIG. 6A is shown. Have been. In other words, the data rate / bit number conversion filter 314 is a filter that can perform data rate / bit number conversion. In FIG. 6C, the input signal 303 is a signal having a data rate f _s and the number of bits M. This signal is a data rate / bit number conversion filter 3
When the data is input to 14, the band is limited and data rate conversion and bit number conversion are performed as described above. As a result, the data rate of the output signal 305 becomes f _s / 2, and the number of bits becomes M + 1.

Further, referring to FIG. 6D, FIG.
A circuit block in which the data rate / bit number conversion filter 314 shown in (c) is constituted by a logic circuit is shown. Here, CLK1 and CLK2 are clocks for operating this logic circuit, and the timing thereof is C
LK1 = is a data rate _{f s, CLK2 = f s /} 2.

In FIG. 6D, the data rate / bit number conversion filter 314 is composed of a shift register array 315 composed of (n + 1) shift registers D _{0 to} D _n.
And a buffer train 316 and mixers 317, 318, 31
(N + 1) mixers including 9, 320, and (n + 1)
An adder 321 for adding the data is provided. Here, a shift register array 315 including (n + 1) shift registers operates at CLK1. On the other hand, (n +
The 1) buffer columns 316 operate at CLK2. Further, (n + 1) mixers including the mixers 317, 318, 319, and 320 operate at the timing of CLK2. As a result, the power of the data rate / bit number conversion filter 314 is reduced. In order to simply and easily configure the data rate / bit number conversion filter 314, the multiplication coefficients of the FIR filter are set to b ₀ , b ₀ + b ₁ ,. . . . What is necessary is just to set _bn-2 + bn _-1 and bn _-1 . As a result, the data rate / bit number converter can be incorporated in the FIR filter. Further, as shown in the figure, by selectively using CLK1 and CLK2, a low power data rate / bit number conversion filter 314 can be realized.

Next, a specific configuration of the digital filter, the data rate / bit number conversion unit, and the like will be described with reference to FIG. As will be understood with reference to FIG. 7, the output signal 30 in the specific configuration shown in FIG.
5, the data rate of the output signal 402 in this specific configuration is f _s / 2.
_s / 4. In both the configuration shown in FIG. 6 and the configuration shown in FIG. 7, the number of bits of output signal 305 and output signal 402 are both M + 1. However, as is apparent from equation (2), in FIG. 6, the S / N improvement is 3 dB because only twice oversampling is performed, whereas in the configuration shown in FIG.
Since double oversampling is performed, an improvement of 6 dB is obtained.

Referring to FIG. 7 (a), the digital filter 301 has a data rate of 1/4 and the number of bits is one.
An increasing data rate / bit number conversion unit 401 is shown. In FIG. 7A, the input signal 303 having the data rate f _s and the number of bits M is band-limited by the digital filter 301, but the output signal 304 is still
The data rate f _s and the number of bits M remain. When the signal 304 is input to the data rate / bit number conversion unit 401, the data rate conversion and the bit number conversion are performed as described above. As a result, the data rate of the output signal 402 becomes f _s / 4, and the number of bits becomes M + 1.

Further, referring to FIG. 7B, FIG.
A circuit block in which the digital filter 301 and the data rate / bit number conversion 401 shown in FIG. Here, CLK1 and CLK3 shown in FIG. 7B are clocks for operating these logic circuits, and the timing is CLK1 and CLK3.
= Data rate fs, CLK3 = fs / 4.

Assuming that the digital filter 301 shown in FIG. 7A is an FIR filter having n taps, the digital filter 301 has n shift registers D ₀ as shown in FIG. 6B. To D _n−1 , and mixers 307, 308,
309 and an adder 310 for adding n data. At this time, the coefficient of n mixers, respectively, a b ₀ ~b _n-1.

The n output signals of the shift register array 306 are multiplied by the coefficients (b _{0 to} b _n-1 ) assigned to the respective mixers in the corresponding mixers. Further, the output from these n mixers is
, So that the band-limited output signal 30
Get 4.

On the other hand, in FIG. 7B, the data rate / bit number converter 401 shown in FIG. 6A includes shift registers (Y _{0 to} Y ₃ ) 404, 405, 406 and 4
07, mixers 408, 409, 410 and 411, and an adder 412. In particular, while the data rate / bit number converter 302 shown in FIG. 6B only adds two signals, the data rate / bit number converter 401 shown in FIG. Mixer 4
08, 409, 410 and 411, coefficients c ₀ , c ₁ ,
c ₂ , c ₃ and shift registers 404, 405, 406, 4
The FIR filter is constituted by the delay at 07. Further, in this example, the adder 412
By operating in LK3, the data rate of the output signal 302 is set to f _s / 4. Each unit other than the adder 412 operates at CLK1.

FIG. 7C shows a data rate / bit number conversion filter 403 having the same function as the combination of the digital filter 301 and the data rate / bit number conversion unit 401 shown in FIG. 7A. Have been. In other words, the data rate / bit number conversion filter 403 is a filter that can perform data rate conversion and bit number conversion. In FIG. 7C, the input signal 303 is a signal having a data rate f _s and the number of bits M. When this signal is input to the data rate / bit number conversion filter 403, the band is limited as described above, and data rate conversion and bit number conversion are performed.
As a result, the data rate of the output signal 402 becomes f _s / 4, and the number of bits becomes M + 1.

Further, referring to FIG. 7D, FIG.
A circuit block in which the data rate / bit number conversion filter 403 shown in (c) is constituted by a logic circuit is shown. Here, CLK1, C shown in FIG.
LK3 is a clock for operating these logic circuits, and its timing is CLK1 = data rate fs,
CLK3 = fs / 4.

In FIG. 7D, the data rate / bit number conversion filter 403 includes a shift register array 41 composed of (n + 3) shift registers (D _{0 to} D _{n + 2} ).
3 and the buffer row 414 and the mixers 415, 416, 4
(N + 3) mixers including 17,418
3) An adder 419 for adding data is provided.
Here, a shift register array 413 including (n + 3) shift registers operates at CLK1. On the other hand, (n
The (+3) buffer rows 414 operate at CLK3. Furthermore, (n + 3) mixers including the mixers 415, 416, 417, and 418 operate at the timing of CLK3. Thus, the power of the data rate / bit number conversion filter 403 is reduced. In this example, in order to simply and easily configure the data rate / bit number conversion filter 403, it is only necessary to change the number of taps and coefficients of the FIR filter in FIG. Specifically, the multiplication coefficient of the FIR filter is changed as shown in the figure.
b ₀ * c ₀ , b ₀ * c ₁ + b ₁ * c ₀ ,. . . b _n-1 * c ₃ + b
_{n * c 2, b n *} c 3 and may be the setting. As a result, the data rate / bit number converter can be incorporated in the digital filter, and as shown in the figure,
By selectively using CLK1 and CLK3, a low power data rate / bit number conversion filter 403 can be realized.

(Third Embodiment) A radio receiver according to a third embodiment of the present invention is a modification of the second embodiment, and as shown in FIG. (A) The first digital filter 202 and the first data rate / bit number conversion unit 203 are connected to the first data rate / bit number conversion filter 502 by the second digital filter 20.
4 and a configuration in which the second data rate / bit number conversion unit 205 is replaced with a second data rate / bit number conversion filter 503. The specific configurations of the first data rate / bit number conversion filter 502 and the second data rate / bit number conversion filter 503 are as described with reference to FIGS.

(Fourth Embodiment) As shown in FIG. 9A, a radio receiver according to a fourth embodiment of the present invention generally includes an analog filter 601 for limiting the band of an input signal, and , An A / D converter 602 for sampling an input signal and converting it into a digital signal, and an A / D converter 602
And a signal processing unit 604 for performing digital signal processing.

Here, similarly to the first embodiment, the signal processing unit 104 may be realized by software or may be configured as hardware.

More specifically, the signal processing unit 604 controls the A /
A quadrature demodulator 605 for quadrature demodulating the digital data 117 received from the D converter 602, a first half-band filter 606, a first data rate / bit number converter 607, and a second half-band filter 608. , A second data rate / bit number conversion unit 609, a third half band filter 610, a third data rate / bit number conversion unit 611, and a fourth half band filter 61.
2, a fourth data rate / bit number conversion unit 613,
It includes a demodulation unit 614, a next-stage signal processing unit 615 that performs conventional signal processing such as decoding, and a control unit 616. In FIG. 9A, similarly to FIGS. 1A and 4A, each filter and conversion unit is shown in a form in which two signals of I and Q are input / output to one block, respectively. I decided that.

Hereinafter, the signal processing method executed in the radio receiver according to the present embodiment having the above-described configuration will be described in detail with reference to FIGS. 9B and 10A to 10G. I do. In the following, the radio receiver can select and receive one channel from a plurality of different frequency channels within the range of the receivable frequency band B, and the receivable band B ₃ The operation in the case of selectively receiving a specific frequency f _IF3 belonging to the above will be exemplified.

When the analog input signal 617 enters the analog filter 601, the band is limited there. here,
The analog filter 601 has a receivable frequency band B ₃
Is a pass band.

Next, the signal 618 band-limited by the analog filter 601 is sampled and quantized in the A / D converter 602 by the sampling clock of the sampling frequency f _s2 generated by the oscillator 603.

Here, the sampling frequency f _s2 is
The Nyquist theorem, there must be more than twice the frequency of the receivable band B ₃ (see FIG. 10 (a)). At this time, as shown in FIG. 9 (b), the data rate of the signal 619 is the sampling frequency f _s2, the number of bits is M _2.

When the signal 619 (data rate: f _s2 ) sampled by the A / D converter 602 enters the signal processing unit 604, the signal is first _input to the quadrature demodulation unit 605 at the frequency f _IF3 of the channel desired to be selected. Thus, the orthogonal transform is performed (see FIG. 10B). The frequency selection in the quadrature demodulation unit 605 is performed under the control of the control unit 616 in the same manner as in the first and second embodiments.

The I and Q signals 6 obtained by this quadrature demodulation
Reference numerals 20, 621 denote first half-band filters 6 respectively.
Enter 06. Here, the half-band filter is a digital filter having a characteristic of limiting the band to １ ／ of the data rate. Therefore, as shown in FIG. 10C, the cutoff frequency of the first half-band filter is 1/4 of the data rate _fs2 .

The signals 622 and 623 band-limited by the first half-band filter 606 enter a first data rate / bit number converter 607. Here, in the first half-band filter 606, since it is band-limited to a quarter of f _s2, aliasing does not occur even if the data rate f _s3 is 1/2 of f _s2. As shown in FIG. 10D, the output signals 624 and 625 at this time have a data rate f _s3 of １ ／ of f _s2 and the number of bits is M ₃ . Note that, as will be described later, M ₃ is equal to M ₂ +1 for the sake of calculation in this example.

Next, similarly, the output signals 628 and 629 which have passed through the second half-band filter 608 and the second data rate / bit number converter 609 are shown in FIG.
(E). The cutoff frequency of the second half-band filter is 1/4 of the data rate _fs3 . Also,
The output signals 628 and 629 have a data rate f _s4 = f _s3 /
2, the number of bits is M _4.

At this time, the data rate f _s4 = f _s3 / 2 =
f _s2 / 4. This is shown in FIG. 3 and equation (1).
As described with reference to (2) and (2), since the oversampling is quadrupled, the S / N for 6 bits and about 1 bit is used.
Improvement can be expected. Therefore, the number of bits M here
₄ can be increased to M ₂ +1. In this example, for the sake of calculation, M ₃ is also assumed to be M ₂ +1. However, M ₃ is assumed to be equal to M ₂ and M ₂ +1 at the time of M _4.
May be increased.

Next, similarly, the third half band filter 610 and the third data rate / bit number conversion unit 61
The output signals 632, 633 passing through 1 are shown in FIG. The output signals 632 and 633 are output at the data rate f _s5
= F _s4 / 2 and the number of bits M ₅ = M ₄ +1.

Further, similarly, the fourth half band filter 612 and the fourth data rate / bit number converter 6
The output signals 636 and 637 that have passed through 13 are shown in FIG. The data rate of the output signals 636, 637 is f _s6
= _Fs5 / 2 = _fs2 / 16. Therefore, the number of bits M ₆
= M ₂ +2.

The data rate f _s6 and the number of bits M ₆ are the data rate and the number of bits required for signal processing after the demodulation section 614 at the subsequent stage.

The signals 636 and 637 that have passed through the fourth data rate / bit number converter 613 in this manner are input to the demodulator 614. As a result, demodulation of the selected channel f _IF3 is performed, and the demodulated signal 638
Is passed to the next-stage signal processing unit 615.

The next-stage signal processing unit 615 is an existing signal processing unit that has been used in the past, and its components include bit synchronization by signal format, decoding, and audio reproduction. Then, the next-stage signal processing unit 615 outputs sound, light, voice,
FAX data, LCD data, PC data, etc. are output.

As described above, when the combination of the half-band filter and the data rate / bit number converter is provided in two stages, the data rate of the output data is reduced to 1/4, and the accuracy of increasing the number of bits by 1 bit can be realized at 6 dB. By utilizing this fact, if the number of bits in the A / D is reduced by calculating backward from the data rate and the number of bits required for demodulation, low power consumption can be realized.

In the fourth embodiment as well, FIGS. 6C and 6D and FIGS.
As described with reference to (c) and (d), the data rate / bit number conversion function may be provided in the half-band filter to realize the function.

(Fifth Embodiment) As shown in FIG. 11A, a radio receiver according to a fifth embodiment of the present invention generally includes an analog filter 701 for limiting the band of an input signal, and , An A / D converter 702 for sampling an input signal and converting it into a digital signal, and an A / D converter 70
An oscillator 703 for supplying a sampling clock to
A signal processing unit 704 for performing digital signal processing.

Here, similarly to the first embodiment, the signal processing unit 104 may be realized by software, or may be configured as hardware.

More specifically, the signal processing unit 704 controls the A /
Down-conversion unit 705 for down-converting digital data 717 received from D converter 702
A first digital filter 708 that limits the band of the signal after down-conversion, a first data rate / bit number converter 709 that converts the data rate and the number of bits, a second digital filter 710, A second data rate / bit number conversion unit 711 and a demodulation unit 71
2, a next-stage signal processing unit 713 that performs conventional signal processing such as decoding, and a control unit 714.

Further, the down-conversion unit 705
It is composed of a mixer 706 and a digital oscillator 707,
Oscillator 707 according to the channel selected by control unit 714
By controlling to change the oscillation frequency at
A desired channel is selectively received.

Hereinafter, a signal processing method performed by the radio receiver according to the present embodiment having the above-described configuration will be described with reference to FIG.

The analog input signal 716 enters the analog filter 701 and is band-limited there. here,
The analog filter 701 is a filter that uses a receivable frequency band as a pass band.

Next, the signal 716 band-limited by the analog filter 701 is sampled and quantized in the A / D converter 702 by the sampling clock of the sampling frequency _fs7 generated by the oscillator 703.

According to Nyquist's theorem, the sampling frequency f _s7 needs to be a frequency that is at least twice the receivable band. At this time, the data rate of the signal 717 becomes the sampling frequency _fs7 . The number of bits of the signal 717 is M ₇ .

Signal 717 sampled by A / D converter 702 (data rate f _s7 : number of bits M ₇ )
When the signal enters the signal processing unit 704, the signal is first down-converted by the down-conversion unit 705 with the frequency of the channel desired to be selected. This frequency selection is performed under the control of the control unit 714. In particular,
By controlling the digital oscillator 707, the frequency is set to f _IF −f
Set to _IF0 . Here, the frequency to be set is f _IF + f _IF0
It is also good to upconvert.
Note that f _IF0 is a frequency predetermined for this system.

As a result, the signal 718 after down-conversion has the frequency f _IF0 . This signal 718 is
Enters a digital filter 708. Here, the band-limited signal 719 enters the first data rate / bit number converter 709. Here, the output 720 obtained by converting the data rate and the number of bits is, as shown in FIG.
The data rate is f _s8 and the number of bits is M ₈ .

Next, the signal 721 whose band has been further limited by the second digital filter 710 is input to the second data rate / bit number converter 711. Output signal 722
Is the data rate f _s9 and the number of bits M ₉ , which is
The data rate and the number of bits required by the demodulation unit 712 for demodulation.

The processing after these down conversions is as follows:
Since it is the same as that of the above-mentioned second embodiment, detailed description will not be required.

The signal 722 is input to the demodulation unit 712 and demodulated, and the demodulated signal 723 is supplied to the next-stage signal processing unit 7.
13 is passed. The next-stage signal processing unit 713 is a conventional existing signal processing unit, and its components include control by a signal format, decoding, and audio reproduction.
Then, the next-stage signal processing unit 713 performs sound, light, voice, FA
It outputs X data, LCD data, PC data, etc.

Note that also in the fifth embodiment, the data rate / bit number conversion section 70
The conversion of the data rate and the number of bits in 9, 711 may be performed in the digital filters 708, 710.

Although various embodiments have been described above, the present invention is not limited to these embodiments. For example, as the digital filter, a filter disclosed in Japanese Patent Application Laid-Open No. 9-135149 (a wide-area digital filtering method and a filter using this method) can be used instead of the filter having the above-described configuration.

[0126]

According to the present invention, a radio receiver capable of receiving a plurality of channels of different frequencies and capable of selecting a reception channel by digital signal processing performs high-speed and low-bit sampling. After performing the channel selection and further performing the band limitation and reducing the data rate, the clock required for the signal processing can be reduced, thereby reducing the power consumption.

Further, according to the present invention, by utilizing the fact that the frequency band required for demodulation of the channel selected with respect to the frequency band to be received is narrow, A The number of bits in the / D converter can be artificially increased, and the demodulation can be performed with the increased number of bits, so that the accuracy can be improved. Since the number of bits in the / D converter can be reduced, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a wireless receiver according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a signal processing method in the wireless receiver according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining an effect of reducing quantization noise by oversampling.

FIG. 4 is a block diagram illustrating a configuration of a wireless receiver according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a signal processing method in a wireless receiver according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a specific configuration of a main part of the present invention.

FIG. 7 is a diagram showing another specific configuration of a main part of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a wireless receiver according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a wireless receiver according to a fourth embodiment of the present invention.

FIG. 10 is a diagram for explaining a signal processing method in a wireless receiver according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a wireless receiver according to a fifth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 101 analog filter 102 A / D converter 103 oscillator 104 signal processing unit 105 quadrature demodulation unit 106 mixer 107 mixer 108 π / 2 shift unit 109 digital oscillator 110 digital filter 111 data rate / bit number conversion unit 112 demodulation unit 113 next stage signal Processing unit 114 Control unit 201 Signal processing unit 202 First digital filter 203 First data rate / bit number conversion unit 204 Second digital filter 205 Second data rate / bit number conversion unit 301 Digital filter 302 Data rate / Bit number conversion unit 306 Shift register sequence 307 Mixer 308 Mixer 309 Mixer 310 Adder 311 Shift register 312 Shift register 313 Adder 314 Data rate / bit number conversion filter 315 shift register array 316 buffer array 317 mixer 318 mixer 319 mixer 320 mixer 321 adder 401 data rate / bit number converter 403 data rate / bit number conversion filter 404 shift register 405 shift register 406 shift register 407 shift register 408 mixer 409 mixer 410 mixer 411 mixer 412 adder 413 shift register array 414 buffer array 415 mixer 416 mixer 417 mixer 418 mixer 419 adder 501 signal processing section 502 first data rate / bit number conversion filter 503 second data rate / bit number conversion Filter 601 Analog filter 602 A / D converter 603 Oscillator 604 Signal processing unit 605 Quadrature demodulation unit 606 First half Filter 607 first data rate / bit number converter 608 second half band filter 609 second data rate / bit number converter 610 third half band filter 611 third data rate / bit number converter 612 Fourth half-band filter 613 Fourth data rate / bit number conversion unit 614 Demodulation unit 615 Next stage signal processing unit 616 Control unit 701 Analog filter 702 A / D converter 703 Oscillator 704 Signal processing unit 705 Down conversion unit 706 Mixer 707 Digital oscillator 708 First digital filter 709 First data rate / bit number converter 710 Second digital filter 711 Second data rate / bit number converter 712 Demodulation unit 713 Next stage signal processing unit 714 Control unit

Claims (13)

[Claims] 1. A wireless receiver capable of receiving a plurality of channel frequencies, comprising: an A / D converter for A / D converting a received signal; and a signal digitally converted by the A / D converter. A signal processing unit for performing digital signal processing on the digital signal, wherein the signal processing unit converts a data rate of the digital signal, and a data rate / bit number converting means for converting the number of bits of the digital signal. A wireless receiver comprising: 2. A radio receiver capable of receiving a plurality of channel frequencies, comprising: an A / D converter for A / D converting a received signal; and a signal digitally converted by the A / D converter. A signal processing unit that performs digital signal processing on the digital signal. The signal processing unit selects a reception frequency, and digitally changes the frequency of the digital signal. A digital filter that receives a signal and limits the band to a specific frequency band, and a data rate and bit number converter that converts the data rate of the band-limited digital signal and also converts the bit number of the band-limited digital signal And a radio receiver. 3. A radio receiver capable of receiving a plurality of channel frequencies, comprising: an A / D converter for A / D converting a received signal; and a signal digitally converted by the A / D converter. A signal processing unit for performing digital signal processing on the digital signal, the signal processing unit comprising: a frequency changing unit for selecting a reception frequency and digitally changing the frequency of the digital signal; and a plurality of digital filters. A digital filter that band-limits the frequency-changed digital signal with a unique frequency band for each of the plurality of digital filters,
A plurality of data rate / bit number conversion means arranged with the corresponding digital filter at the preceding stage and alternately arranged with the plurality of digital filters, each comprising: a data of a digital signal band-limited in the corresponding digital filter. Data rate / bit number conversion means for converting a rate and also converting the number of bits of the band-limited digital signal, wherein a band limitation in the digital filter and a data rate conversion in the data rate / bit number conversion means are provided. And repeating the conversion of the number of bits a plurality of times. 4. The radio receiver according to claim 2, wherein the frequency change in said frequency change means is an orthogonal transform. 5. The radio receiver according to claim 1, wherein the data rate / bit conversion means performs conversion so as to reduce the data rate and increases the number of bits. A radio receiver characterized in that the radio receiver converts the data. 6. A signal processing method in a wireless receiver, comprising: receiving an input signal including a plurality of pieces of information having different frequencies, passing the signal through an analog filter having a first frequency band as a transmission band, A method of sampling a digital clock having a frequency and performing A / D conversion to generate a digital signal of the first bit number and selectively digitally processing a signal related to one of the plurality of information. A signal having a second frequency lower than the first frequency as a data rate and a second bit number larger than the first bit number as a bit number is subjected to processing after demodulation as a processing target. Therefore, after selecting the signal relating to the one piece of information and before demodulating the one piece of information, the signal relating to the one piece of information is transmitted from the first frequency band. Is also a narrow frequency band and passes through a digital filter that has a second frequency band that satisfies the Nyquist condition with respect to the second frequency as a transmission band. Thereafter, the data rate of the signal band-limited by the digital filter is A signal processing method in a wireless receiver, wherein the signal rate is converted to a data rate having the second frequency, and the number of bits of the band-limited signal is converted to the second bit number. 7. The signal processing method in a wireless receiver according to claim 6, wherein the selection of the signal related to the one piece of information is performed by orthogonally transforming the digital signal using a frequency related to the one piece of information. A signal processing method in a wireless receiver, characterized in that: 8. The signal processing method in a wireless receiver according to claim 7, wherein a frequency having a value of の of a width of the second frequency band is oversampled at the first frequency. When the S / N ratio obtained by assuming is equal to the S / N ratio obtained when the number of bits at the time of A / D conversion is increased by a predetermined number of bits from the first number of bits, the first A signal processing method in a wireless receiver, wherein a sum of the number of bits and the predetermined number of bits is used as the second number of bits. 9. A signal processing method in a wireless receiver, comprising: receiving an input signal including a plurality of pieces of information having different frequencies, passing the input signal through an analog filter, and sampling the signal according to a clock having a first frequency. A method of generating a digital signal of the first number of bits by D-conversion and selectively digitally processing a signal relating to one of the plurality of pieces of information, wherein the data rate is set to be smaller than the first frequency A signal having a lower second frequency and a second bit number larger than the first bit number as a bit number to be processed and subjected to demodulation and subsequent processing. After the selection of the signal and before the demodulation of the one piece of information, the signal concerning the one piece of information is filtered with a predetermined frequency band as a transmission band. The rate conversion is performed so as to reduce the data rate of the filtered signal to a predetermined frequency at which the predetermined frequency band satisfies the Nyquist condition, and to increase the number of bits of the filtered signal. By performing the process of converting the number of bits by a plurality of times by gradually narrowing the predetermined frequency band and lowering the predetermined frequency in accordance with the narrowed predetermined frequency band, A signal having the second frequency as a data rate and the signal having the second bit number as a bit number. 10. The signal processing method in a wireless receiver according to claim 9, wherein the selection of the signal related to the one piece of information is performed by orthogonally transforming the digital signal using a frequency related to the one piece of information. A signal processing method in a wireless receiver, characterized in that: 11. The signal processing method in a wireless receiver according to claim 10, wherein it is assumed that a frequency having a value of 幅 of a width of the predetermined frequency band is oversampled at the first frequency. The filter is applied when the S / N ratio obtained by performing the filtering is equal to the S / N ratio obtained when the number of bits at the time of A / D conversion is increased by a predetermined number of bits from the first number of bits. A signal processing method in a wireless receiver, wherein the bit conversion is performed by increasing the number of previous bits to the number of bits given by the sum of the first number of bits and the predetermined number of bits. 12. The signal processing method according to claim 6, wherein the selection of the signal related to the one piece of information is performed by down-converting a frequency related to the one piece of information. A signal processing method in a wireless receiver. 13. A signal processing method in a wireless receiver, comprising: receiving an input signal including a plurality of pieces of information having different frequencies, passing the input signal through an analog filter, and sampling the signal according to a clock having a first frequency. A digital signal of the first number of bits is generated by D-conversion, and further, the digital signal is orthogonally transformed with a frequency of the one information, thereby obtaining a signal of one of the plurality of information. And digitally processing the selected signal related to the one piece of information, wherein the data rate has a second frequency lower than the first frequency, and the number of bits is greater than the first number of bits. In order to perform processing after demodulation as a signal to be processed with a signal having a large number of second bits, after selecting a signal related to the one information, Before demodulating the one piece of information, a signal related to the one piece of information is filtered with a predetermined frequency band as a transmission band, and the signal is set to a predetermined frequency at which the predetermined frequency band satisfies the Nyquist condition. Assume that the rate conversion is performed so as to reduce the data rate of the filtered signal, and that the frequency having a value of １ ／ the width of the predetermined frequency band is oversampled at the first frequency. The S / N ratio obtained by performing A / D
When the number of bits at the time of conversion is equal to the S / N ratio obtained when the number of bits is increased by a predetermined number of bits from the first number of bits, the number of bits of the filtered signal, the first number of bits and Bit conversion is performed by increasing the number of bits given by the sum of the number of bits, and these filters are applied, rate conversion is performed, and if possible, a series of processes for bit conversion is performed by gradually narrowing the predetermined frequency band. The predetermined frequency is lowered a plurality of times in accordance with the narrowed predetermined frequency band. A signal processing method in a wireless receiver, wherein the signal is converted into a signal having a second bit number.