JP2000236074A5 - - Google Patents

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JP2000236074A5
JP2000236074A5 JP1999309114A JP30911499A JP2000236074A5 JP 2000236074 A5 JP2000236074 A5 JP 2000236074A5 JP 1999309114 A JP1999309114 A JP 1999309114A JP 30911499 A JP30911499 A JP 30911499A JP 2000236074 A5 JP2000236074 A5 JP 2000236074A5
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memory cell
mis transistor
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半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する一方の第１低濃度半導体領域の上方に情報を転送するデータ線が形成され、前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する他方の第２低濃度半導体領域の上方に前記容量素子が形成されており、
前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１低濃度半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２低濃度半導体領域の不純物濃度よりも相対的に高く、前記メモリセル選択用ＭＩＳトランジスタのデータ線側の半導体基板の表面濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の半導体基板の表面濃度よりも相対的に高く、
さらに、前記メモリセルの周囲に設けられた回路にＭＩＳトランジスタが形成されており、
前記ＭＩＳトランジスタのソース、ドレインを構成する一方の低濃度半導体領域の不純物濃度と前記ＭＩＳトランジスタのソース、ドレインを構成する他方の低濃度半導体領域の不純物濃度とが同じであることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
A data line for transferring information is formed above one of the first low-concentration semiconductor regions forming the source and the drain of the memory cell selecting MIS transistor, and the other forming the source and the drain of the memory cell selecting MIS transistor The capacitive element is formed above the second low-concentration semiconductor region of
The impurity concentration of the first low concentration semiconductor region on the data line side of the memory cell selection MIS transistor is relatively higher than the impurity concentration of the second low concentration semiconductor region on the capacitor side of the memory cell selection MIS transistor. The surface concentration of the semiconductor substrate on the data line side of the memory cell selecting MIS transistor is relatively higher than the surface concentration of the semiconductor substrate on the capacitor side of the memory cell selecting MIS transistor;
Further, a MIS transistor is formed in a circuit provided around the memory cell,
A semiconductor wherein the impurity concentration of one of the low-concentration semiconductor regions forming the source and drain of the MIS transistor is the same as the impurity concentration of the other low-concentration semiconductor region forming the source and drain of the MIS transistor. Integrated circuit device. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する一方の第１低濃度半導体領域の上方に情報を転送するデータ線が形成され、前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する他方の第２低濃度半導体領域の上方に前記容量素子が形成されており、
前記メモリセル選択用ＭＩＳトランジスタが形成された半導体基板の表面に、前記半導体基板と同じ導電型の不純物によって構成され、その表面濃度が前記半導体基板の表面濃度よりも相対的に高い不純物表面層が設けられており、
前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１低濃度半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２低濃度半導体領域の不純物濃度よりも相対的に高いことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
A data line for transferring information is formed above one of the first low-concentration semiconductor regions forming the source and the drain of the memory cell selecting MIS transistor, and the other forming the source and the drain of the memory cell selecting MIS transistor The capacitive element is formed above the second low-concentration semiconductor region of
On the surface of the semiconductor substrate on which the memory cell selecting MIS transistor is formed, an impurity surface layer composed of impurities of the same conductivity type as the semiconductor substrate and having a surface concentration relatively higher than the surface concentration of the semiconductor substrate is provided. Is provided,
The impurity concentration of the first low concentration semiconductor region on the data line side of the memory cell selection MIS transistor is relatively higher than the impurity concentration of the second low concentration semiconductor region on the capacitor side of the memory cell selection MIS transistor. Semiconductor integrated circuit device characterized by high cost. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する一方の第１低濃度半導体領域の上方に情報を転送するデータ線が形成され、前記第１低濃度半導体領域を囲んで前記第１低濃度半導体領域と異なる導電型の不純物によって構成された第１半導体領域が形成され、前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する他方の第２低濃度半導体領域の上方に前記容量素子が形成され、前記第２低濃度半導体領域を囲んで前記第２低濃度半導体領域と異なる導電型の不純物によって構成された第２半導体領域が形成されており、
前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１低濃度半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２低濃度半導体領域の不純物濃度よりも相対的に高く、前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２半導体領域の不純物濃度よりも相対的に高いことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
A data line for transferring information is formed above one of the first low-concentration semiconductor regions constituting a source and a drain of the memory cell selecting MIS transistor, and the first low-concentration semiconductor region surrounds the first low-concentration semiconductor region. A first semiconductor region formed of an impurity having a conductivity type different from that of the semiconductor region is formed; and the capacitor is formed above the other second low-concentration semiconductor region forming a source and a drain of the memory cell selecting MIS transistor. Forming a second semiconductor region surrounding the second low-concentration semiconductor region and having a conductivity type different from that of the second low-concentration semiconductor region;
The impurity concentration of the first low concentration semiconductor region on the data line side of the memory cell selection MIS transistor is relatively higher than the impurity concentration of the second low concentration semiconductor region on the capacitor side of the memory cell selection MIS transistor. And the impurity concentration of the first semiconductor region on the data line side of the memory cell selecting MIS transistor is relatively higher than the impurity concentration of the second semiconductor region on the capacitor side of the memory cell selecting MIS transistor. A semiconductor integrated circuit device characterized by being expensive. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタのゲート電極の側壁に設けられたサイドウォールスペーサ下のデータ線側の半導体基板に、ゲート長方向にチャネル領域へ向かって、前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する一方の第１低濃度半導体領域、および前記第１低濃度半導体領域と異なる導電型によって構成された第１半導体領域が順に形成されており、前記サイドウォールスペーサ下の容量素子側の半導体基板に、ゲート長方向にチャネル領域へ向かって、前記メモリセル選択用ＭＩＳトランジスタのソース、ドレインを構成する他方の第２低濃度半導体領域、および前記第２低濃度半導体領域と異なる導電型によって構成された第２半導体領域が形成されており、
前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１低濃度半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２低濃度半導体領域の不純物濃度よりも相対的に高く、前記メモリセル選択用ＭＩＳトランジスタのデータ線側の前記第１半導体領域の不純物濃度が、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２半導体領域の不純物濃度よりも相対的に高いことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
A source and a drain of the memory cell selecting MIS transistor are formed on a semiconductor substrate on a data line side below a sidewall spacer provided on a side wall of a gate electrode of the memory cell selecting MIS transistor toward a channel region in a gate length direction. Are formed in order, and a first semiconductor region having a conductivity type different from that of the first low-concentration semiconductor region is formed in order, and a semiconductor on a capacitive element side below the sidewall spacer is formed. A second low-concentration semiconductor region forming the source and drain of the memory cell selecting MIS transistor and a conductivity type different from the second low-concentration semiconductor region on the substrate in the gate length direction toward the channel region; Formed second semiconductor region,
The impurity concentration of the first low concentration semiconductor region on the data line side of the memory cell selection MIS transistor is relatively higher than the impurity concentration of the second low concentration semiconductor region on the capacitor side of the memory cell selection MIS transistor. And the impurity concentration of the first semiconductor region on the data line side of the memory cell selecting MIS transistor is relatively higher than the impurity concentration of the second semiconductor region on the capacitor side of the memory cell selecting MIS transistor. A semiconductor integrated circuit device characterized by being expensive. 請求項１記載の半導体集積回路装置において、前記メモリセル選択用ＭＩＳトランジスタの容量素子側の前記第２低濃度半導体領域の不純物濃度は、メモリセルの周囲に設けられた回路に形成されて前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型のチャネルを有する何れかのＭＩＳトランジスタのソース、ドレインを構成する一対の低濃度半導体領域の不純物濃度と同じであることを特徴とする半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1 , wherein an impurity concentration of the second low-concentration semiconductor region on a capacitor element side of the memory cell selecting MIS transistor is formed in a circuit provided around a memory cell. A semiconductor integrated circuit device having the same impurity concentration as a pair of low-concentration semiconductor regions forming a source and a drain of any MIS transistor having a channel of the same conductivity type as a channel of a cell selection MIS transistor. 請求項１から５のいずれか１項に記載の半導体集積回路装置において、前記メモリセル選択用ＭＩＳトランジスタのチャネル領域には、しきい値電圧調整用の不純物が導入されていないことを特徴とする半導体集積回路装置。In the semiconductor integrated circuit device according to claim 1, any one of 5, the channel region of the memory cell selecting MIS transistor is characterized in that the impurity for adjusting the threshold voltage is not introduced Semiconductor integrated circuit device. 請求項１から５のいずれか１項に記載の半導体集積回路装置において、前記メモリセル選択用ＭＩＳトランジスタのチャネル領域には、しきい値電圧調整用の不純物が導入されており、前記メモリセル選択用ＭＩＳトランジスタのチャネル領域の不純物濃度は、メモリセルの周囲に設けられた回路に形成されて前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型のチャネルを有する何れかのＭＩＳトランジスタのチャネル領域の不純物濃度と同じか、またはそれ以下であることを特徴とする半導体集積回路装置。In the semiconductor integrated circuit device according to any one of claims 1 to 5, wherein the channel region of the memory cell selecting MIS transistors are introduced impurity for adjusting the threshold voltage, the memory cell selection The impurity concentration of the channel region of the MIS transistor for use in the channel region of any of the MIS transistors formed in a circuit provided around the memory cell and having the same conductivity type as the channel of the MIS transistor for selecting the memory cell. A semiconductor integrated circuit device having the same or lower impurity concentration. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを形成する半導体集積回路装置の製造方法であって、
(a).前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の半導体基板上に、前記メモリセル選択用ＭＩＳトランジスタのゲート絶縁膜およびゲート電極を順次形成する工程と、
(b).前記メモリセル選択用ＭＩＳトランジスタのデータ線側の半導体基板のみに、同一のレジストパターンをマスクにして、前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の第１不純物イオンおよび前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第２不純物イオンを注入する工程と、
(c).前記メモリセル選択用ＭＩＳトランジスタの容量素子側の半導体基板に、前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第３不純物イオンを注入する工程とを有することを特徴とする半導体集積回路装置の製造方法。A method for manufacturing a semiconductor integrated circuit device for forming a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
(a) sequentially forming a gate insulating film and a gate electrode of the memory cell selecting MIS transistor on a semiconductor substrate of a conductivity type different from a channel of the memory cell selecting MIS transistor;
(b) Only the semiconductor substrate on the data line side of the memory cell selecting MIS transistor is masked with the same resist pattern as a mask, and the first impurity ions of the conductivity type different from the channel of the memory cell selecting MIS transistor and Implanting a second impurity ion of the same conductivity type as the channel of the memory cell selecting MIS transistor;
(c) implanting third impurity ions of the same conductivity type as the channel of the memory cell selection MIS transistor into the semiconductor substrate on the capacitor side of the memory cell selection MIS transistor. A method for manufacturing a semiconductor integrated circuit device. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを形成する半導体集積回路装置の製造方法であって、
(a).前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の半導体基板上に、前記メモリセル選択用ＭＩＳトランジスタのゲート絶縁膜およびゲート電極を順次形成する工程と、
(b).前記メモリセル選択用ＭＩＳトランジスタのデータ線側の半導体基板のみに、同一のレジストパターンをマスクにして、前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の第１不純物イオンおよび前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第２不純物イオンを注入する工程と、
(c).前記メモリセル選択用ＭＩＳトランジスタのデータ線側および容量素子側の半導体基板と、メモリセルの周囲に設けられた回路に形成されて前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型のチャネルを有する何れかのＭＩＳトランジスタが形成される半導体基板とに、前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第３不純物イオンを注入する工程とを有することを特徴とする半導体集積回路装置の製造方法。A method for manufacturing a semiconductor integrated circuit device for forming a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
(a) sequentially forming a gate insulating film and a gate electrode of the memory cell selecting MIS transistor on a semiconductor substrate of a conductivity type different from a channel of the memory cell selecting MIS transistor;
(b) Only the semiconductor substrate on the data line side of the memory cell selecting MIS transistor is masked with the same resist pattern as a mask, and the first impurity ions of the conductivity type different from the channel of the memory cell selecting MIS transistor and Implanting a second impurity ion of the same conductivity type as the channel of the memory cell selecting MIS transistor;
(c) The same conductivity type as that of the semiconductor substrate on the data line side and the capacitor side of the memory cell selecting MIS transistor and the channel of the memory cell selecting MIS transistor formed in a circuit provided around the memory cell. Implanting a third impurity ion of the same conductivity type as the channel of the memory cell selecting MIS transistor into a semiconductor substrate on which any of the MIS transistors having the channel is formed. A method for manufacturing a circuit device. 半導体基板上にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを形成する半導体集積回路装置の製造方法であって、
(a).前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の半導体基板上に、前記メモリセル選択用ＭＩＳトランジスタのゲート絶縁膜およびゲート電極を順次形成する工程と、
(b).前記メモリセル選択用ＭＩＳトランジスタのデータ線側の半導体基板のみに、同一のレジストパターンをマスクにして、前記メモリセル選択用ＭＩＳトランジスタのチャネルと異なる導電型の第１不純物イオンおよび前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第２不純物イオンを注入する工程と、
(c).前記メモリセル選択用ＭＩＳトランジスタのデータ線側および容量素子側の半導体基板に、前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の第３不純物イオンを注入する工程と、
(d).前記メモリセル選択用ＭＩＳトランジスタの上層に形成された絶縁膜を加工して、データ線を接続するための第１コンタクトホールおよび前記容量素子を接続するための第２コンタクトホールを前記半導体基板に接して形成する工程と、
(e).前記第１コンタクトホールおよび前記第２コンタクトホールに、前記メモリセル選択用ＭＩＳトランジスタのチャネルと同じ導電型の導電膜を埋め込み、前記導電膜に添加された不純物を前記メモリセル選択用ＭＩＳトランジスタのデータ側および容量素子側の半導体基板へ拡散させる工程とを有することを特徴とする半導体集積回路装置の製造方法。A method for manufacturing a semiconductor integrated circuit device for forming a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
(a) sequentially forming a gate insulating film and a gate electrode of the memory cell selecting MIS transistor on a semiconductor substrate of a conductivity type different from a channel of the memory cell selecting MIS transistor;
(b) Only the semiconductor substrate on the data line side of the memory cell selecting MIS transistor is masked with the same resist pattern as a mask, and the first impurity ions of the conductivity type different from the channel of the memory cell selecting MIS transistor and Implanting a second impurity ion of the same conductivity type as the channel of the memory cell selecting MIS transistor;
(c) implanting third impurity ions of the same conductivity type as the channel of the memory cell selecting MIS transistor into the semiconductor substrate on the data line side and the capacitor side of the memory cell selecting MIS transistor;
(d) processing an insulating film formed on the memory cell selecting MIS transistor to form a first contact hole for connecting a data line and a second contact hole for connecting the capacitive element; A step of forming in contact with the semiconductor substrate;
(e) A conductive film of the same conductivity type as the channel of the memory cell selecting MIS transistor is buried in the first contact hole and the second contact hole, and an impurity added to the conductive film is used for the memory cell selecting MIS transistor. Diffusing the semiconductor device on the data side and the capacitor side of the MIS transistor into a semiconductor substrate. 半導体基板にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタは、前記半導体基板に設けられたソース、ドレイン用の一対の半導体領域と、前記一対の半導体領域の間に設けられた第１領域と、前記半導体基板上において前記第１領域上に設けられ前記メモリセルの非選択時において負の電圧が印加されるゲート電極とを有し、
前記一対の半導体領域は、第１不純物が含有されてなり、前記第１領域は前記一対の半導体領域とは反対導電型になるように第２不純物が含有されてなり、
前記第１領域において、前記一対の半導体領域のうち、データ線が接続された半導体領域の近傍における前記第２不純物の濃度が、前記第１領域の他の領域における第２不純物の濃度よりも高いことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
The memory cell selection MIS transistor includes: a pair of source and drain semiconductor regions provided on the semiconductor substrate; a first region provided between the pair of semiconductor regions; A gate electrode provided on one region and to which a negative voltage is applied when the memory cell is not selected;
The pair of semiconductor regions include a first impurity, and the first region includes a second impurity such that the second region has a conductivity type opposite to that of the pair of semiconductor regions.
In the first region, of the pair of semiconductor regions, the concentration of the second impurity in the vicinity of the semiconductor region to which the data line is connected is higher than the concentration of the second impurity in another region of the first region. A semiconductor integrated circuit device characterized by the above-mentioned. 請求項１１記載の半導体集積回路装置において、前記ゲート電極がｎ+ 型の導体部を有し、前記一対の半導体領域がｎ型であり、前記第１領域がｐ型であることを特徴とする半導体集積回路装置。12. The semiconductor integrated circuit device according to claim 11 , wherein the gate electrode has an n + -type conductor, the pair of semiconductor regions is n-type, and the first region is p-type. Semiconductor integrated circuit device. 請求項１１記載の半導体集積回路装置において、基板バイアスを負側にしたことを特徴とする半導体集積回路装置。12. The semiconductor integrated circuit device according to claim 11 , wherein the substrate bias is set to a negative side. 半導体基板にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタは、前記半導体基板に設けられたソース、ドレイン用の一対の半導体領域と、前記一対の半導体領域の間に設けられた第１領域と、前記半導体基板上において前記第１領域上に設けられたゲート電極とを有し、
前記一対の半導体領域は、第１不純物が含有されてなり、前記第１領域は前記一対の半導体領域とは反対導電型になるように第２不純物が含有されてなり、前記ゲート電極は、前記第１領域と同じ導電型の導体部を有し、
前記第１領域において、前記一対の半導体領域のうち、データ線が接続された半導体領域の近傍における前記第２不純物の濃度が、前記第１領域の他の領域における第２不純物の濃度よりも高いことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
The memory cell selection MIS transistor includes: a pair of source and drain semiconductor regions provided on the semiconductor substrate; a first region provided between the pair of semiconductor regions; A gate electrode provided on one region,
The pair of semiconductor regions include a first impurity, the first region includes a second impurity so as to have a conductivity type opposite to that of the pair of semiconductor regions, and the gate electrode includes: Having a conductor portion of the same conductivity type as the first region,
In the first region, of the pair of semiconductor regions, the concentration of the second impurity in the vicinity of the semiconductor region to which the data line is connected is higher than the concentration of the second impurity in another region of the first region. A semiconductor integrated circuit device characterized by the above-mentioned. 半導体基板にメモリセル選択用ＭＩＳトランジスタと容量素子とが直列接続されたメモリセルを有する半導体集積回路装置であって、
前記メモリセル選択用ＭＩＳトランジスタは、前記半導体基板に設けられたソース、ドレイン用の一対の半導体領域と、前記一対の半導体領域の間に設けられた第１領域と、前記半導体基板上において前記第１領域上に設けられたゲート電極とを有し、
前記一対の半導体領域は、第１不純物が含有されてなり、前記第１領域は前記一対の半導体領域とは反対導電型になるように第２不純物が含有されてなり、前記ゲート電極は、前記第１領域と同じ導電型の導体部を有し、
前記第１領域において、前記一対の半導体領域の両方またはいずれか一方の近傍に、前記第２不純物の濃度が相対的に高く含有された半導体領域を設けたことを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a memory cell in which a memory cell selecting MIS transistor and a capacitor are connected in series on a semiconductor substrate,
The memory cell selection MIS transistor includes: a pair of source and drain semiconductor regions provided on the semiconductor substrate; a first region provided between the pair of semiconductor regions; A gate electrode provided on one region,
The pair of semiconductor regions include a first impurity, the first region includes a second impurity so as to have a conductivity type opposite to that of the pair of semiconductor regions, and the gate electrode includes: Having a conductor portion of the same conductivity type as the first region,
A semiconductor integrated circuit device, wherein in the first region, a semiconductor region containing a relatively high concentration of the second impurity is provided in the vicinity of at least one of the pair of semiconductor regions.
JP11309114A 1998-12-17 1999-10-29 Semiconductor integrated circuit device and its manufacture Pending JP2000236074A (en)

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