JP2000232345A - Digital pulse width modulation power controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplification digital pulse width modulation power controller while keeping digital data as digital signals without making them analog. SOLUTION: This controller generates a full bit clock (c) within the word clock (b) of digital data (PCM digital data (a)) and performs setting so as to turn the time required for comparing preset digital data and the bit clock within one conversion cycle of the word clock to pulse width modulation output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital sound device, a digital sound search, a digital motor drive,
The present invention relates to an output control device such as a digital power supply device.

[0002]

2. Description of the Related Art Conventionally, as this kind, "Millennium" manufactured by Europe TACT, and A
Pogee's "DDX" is known.

[0003]

However, a conventional digital PWM device uses a DSP or the like for signal processing such as noise shaping and a decimation filter in order to improve the bit resolution, and spends a lot of time in programming. Was.

[0004]

In order to solve such a problem, the invention according to the first, second, third and fourth aspects does not use a DSP or the like for improving the bit resolution and reduces programming. That is, a digital power control device is set up so that a digital clock can be obtained by generating a bit clock for each word and comparing and counting the word clock and the PCM data.

[0005]

In the present apparatus, the input digital data is output-controlled as it is digitally, and the input data is hardly deteriorated. That is, the process of converting the input digital data into an analog waveform and then amplifying and outputting the same is not necessary, and the circuit configuration is simplified and high efficiency can be obtained.

[0006]

Embodiments of the present invention will be described below. FIG. 1 shows a first embodiment of the present invention. As an embodiment, the PCM digital data (a) is a digital receiver unit.
The word clock (b) is extracted as input to (1). The word clock (b) is a bit clock in the oscillation section (2).
(c) Generate (full bit clock). On the other hand, the digital data (a) preset in the comparison counter section (5) is
The full bit data is counted by the generated bit clock (c), the quantity is compared, and the difference between the preset digital data (a) and the number of full bit data is output as a count output (d). That is, the input digital data
Output data (d) proportional to (a) is obtained. The digital data control unit 4 and the output control unit (7) include an output power setting unit.
(Variable) (6) enables use at a generally easy-to-handle level with the control signal (e). The A / D converter unit (3) and digital input can be selected by a switch (f) so that a conventional analog signal can be handled.

[0007]

Embodiment 2 FIG. 2 shows Embodiment 2 of the present invention. Second Embodiment As a second embodiment, a PCM transmission path power control device characterized in that a data signal is superimposed on a redundant portion of digital audio data in the PCM audio format. Further, it has a feature that the information amount of the data signal can be changed by adjusting the digital audio data bit amount. P
The CM digital data (A) passes through the digital receiver section (11), and is transmitted to the power data and control data superimposing circuit section (12-1).
The received digital data is kept word by word,
New information data in redundant part of PCM digital data (A)
(AA) is written as output PCM data (BB) in the digital transmitter section (12-2). The analog input signal (13) operates in the same way by the changeover switch (D).
Further, the PCM data (BB) is input to the digital receiver (11), and extracts the word clock (E). Next, the PCM received by the power data / control data separation circuit (12)
The digital data is held for each word, and the superimposed data is separated into control data (B) and power data (C) by an internal latch circuit. (C) and (E) show the counter section (1
7), Look-up table (14), Lower pulse controller (1
5), upper pulse modulation unit by upper data count signal (F)
(16), etc., and the synthesized pulse signal by the pulse synthesizer (18)
(G) is generated. The generated signal (G) is output control unit (1
In 9), the output power setting unit (variable) (20) is used as a PCM output signal (I) by using the control signal (H) at a generally easy-to-handle level. A plurality of control units can be controlled by a signal path (CC) indicated by a broken line, and collective control and stand-alone control can be simultaneously performed. In addition, an A / D converter section (13) and a digital signal can be selected by a switch (D) so that a conventional analog signal can be handled. Furthermore, independent use is possible before the transmitter side (BB) and after the receiver side (BB).

[0008]

According to the present invention, as described above, P
The same operation is performed within the range of the resolution of the CM data. Therefore, the output is proportional to the input digital data, and the same output as the input is obtained, so that there is a certain reproducibility. By superimposing the control data on the power data as in the second embodiment, a system having an intelligent function is provided, and a wide range of simultaneous control and individual control can be performed, and other information can be transmitted. As described above, the circuit configuration is simple, so that it has a feature suitable for an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a circuit diagram of a second embodiment.

[Explanation of symbols]

 (1) Digital receiver (2) Oscillator (3) A / D converter (4) Digital data controller (5) Comparison counter (6) Output power setting (variable) (7) Output controller (a) ) PCM digital data (b) Word clock signal (c) Full bit clock signal (d) Count difference output signal (e) Output control signal (f) PCM digital data switch (g) PCM output signal (11) Digital receiver section (12) Power data and control data separation circuit section (12-1) Power data and control data superimposition section (12-2) Digital transmitter (13) A / D converter section (14) Look-up table (15) Lower pulse control (16) Upper pulse width modulator (17) Counter (18) Pulse synthesizer (19) Output controller (20) Output power setting (A) PCM digital data (B) Control data (C) Power data ( D) Power data changeover switch (E) Word clock ( ) Higher data count signal (G) Synthesis pulse width signal (H) output control signal (I) PCM output signal (AA) superposed control data (BB) output PCM data (CC) signal communications paths

Claims (4)

[Claims] 1. A maximum data bit clock (sampling frequency × data length) is generated in a basic clock (word clock) of digital data (PCM signal), and the number of digital data (PCM signal) is determined by a preset counter for comparison. The pulse width modulation is obtained by comparing and counting the power control signals. 2. An upper bit clock (sampling frequency × data length−lower data length) in a basic clock of digital data.
The counter is compared with the number of digital data by the counter to obtain the upper pulse width modulation, and the lower pulse determines the delay amount from the lower data amount using the internal delay in the arithmetic element, and performs the upper pulse width modulation. A power control device characterized in that a high-precision pulse-width modulation can be obtained by taking measures to increase the resolution by adding, and to further correct input data with a look-up table in order to increase the output error accuracy. 3. The intelligent power control device according to claim 1, wherein the digital data has a redundant data width for future expansion, and this data is used for control. 4. A power control device, wherein digital data has a redundant data width for future expansion, and superimposes control data on a redundant portion.