JP2000232166A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which the short-channel effect of a CMOS transistor can be suppressed and the current driving ability of the transistor can be improved, and then, the density of the transistor can be increased. SOLUTION: A semiconductor device manufacturing method includes a step for selectively introducing an n-type impurity to an nMOS transistor forming area 1 by using a gate electrode 5 as a make, a step for forming first side walls 7 on the side faces of gate electrodes 5, and a step for selectively introducing a p-type impurity to a pMOS transistor forming area 2 by using another gate electrode 5 and first side walls 7 formed on the side faces of the electrode 5 as masks. The method also includes a step for forming second side walls 9 which are narrower in width than the first side walls 7 on the side faces of the electrodes 5 after removing the first side walls 7, and a step for selectively introducing the n- and p-type impurities to the nMOS and pMOS transistor forming areas 1 and 2, respectively, by using the gate electrodes 5 and second side walls 9 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of increasing the density and speed of a CMOS transistor.

2. Description of the Related Art In recent years, the importance of CMOS transistors has been increasing in promoting low power consumption and high speed of various electronic devices such as computers. However, CMOS transistors include nMOS transistors and pMOS transistors on the same substrate. Since it is formed, it is more difficult to optimize the device parameters than in the case of forming each individually, and there arises a problem such as deterioration of characteristics, and a solution to the problem is desired.

[0003]

2. Description of the Related Art FIGS. 5 and 6 are cross-sectional views showing the main parts of a conventional CMOS transistor manufacturing process. First, FIG.
As shown in (a), an nMOS transistor formation region 21, a pMOS transistor formation region 22, and an element isolation region 23 are formed on a semiconductor substrate, and the nMOS transistor formation region
A gate oxide film 24 and a gate electrode 25 are formed on the region 21 and the pMOS transistor formation region 22.

[0005] Next, as shown in FIG. 5 (b), the nMOS transistor formation region 21 is formed using the gate electrode 25 as a mask.
Arsenic (As) is selectively ion-implanted under the conditions of an acceleration energy of 10 KeV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to form an n ⁻ layer 26 which becomes an LDD (Lightly Doped Drain) region of an nMOS transistor.
To form

Then, as shown in FIG. 5C, the pMOS transistor formation region 22 is formed using the gate electrode 25 as a mask.
Then, boron fluoride (BF ₂ ) is selectively ion-implanted under the conditions of an acceleration energy of 10 KeV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to form a p ⁻ layer 27 which becomes an LDD region of a pMOS transistor.

Next, as shown in FIG. 6A, a sidewall 28 having a width of about 160 nm is formed on the side surface of the gate electrode 25 by anisotropic dry etching after depositing a silicon oxide film on the entire surface.

[0007] Next, as shown in FIG.
The nMOS transistor is formed by using the electrode 25 and the sidewall 28 as a mask.
Acceleration energy 10 KeV, implantation amount 4 in transistor formation region 21
× 10 ¹⁵cm^-2Selectively implant As ions under the conditions of
N which becomes the S / D (Source / Drain) region of the transistor⁺layer
Form 29.

Next, as shown in FIG.
Using the electrode 25 and the sidewall 28 as a mask, the pMOS transistor
Acceleration energy 10 KeV, implantation amount 5 in transistor formation region 22
× 10 ¹⁵cm^-2BF under the condition_TwoIs selectively ion-implanted and pMO
P serving as the S / D region of the S transistor⁺Form layer 30
You.

Finally, heat treatment at 1000 ° C. for 10 seconds (RTA)
Treatment) to activate the ion-implanted impurities.
As a result, the gate electrode 25, n^-Layer 26, n⁺Layer 29, p^-Tier 2
7, p ⁺The resistance of the layer 30 is reduced.

[0010]

In the above-described process of manufacturing the CMOS transistor, the sidewall is formed of S / D.
This is provided in order to suppress the diffusion of the impurity ion-implanted into the region into the channel. If the sidewall width is set to be narrower than necessary, the suppression of the short channel effect becomes insufficient.
The parasitic resistance in the / D region increases, and the current driving capability decreases.

Therefore, the side wall width is short.
Trade-off between suppression of tunnel effect and improvement of current drive capability
Must be set to a value determined by the
Optimum value of wall width depends on diffusion coefficient of impurity
Therefore, the nMOS transistor and the pMOS transistor
Setting the optimal value for both at the same time is generally
Have difficulty. For example, the aforementioned CMOS transistor
In the manufacturing process, the diffusion coefficient of boron (B) is
Therefore, under the same heat treatment conditions, p ⁺Layer 30
The spread is n⁺It is larger than the extent of layer 29. Therefore, p
The optimal sidewall width for MOS transistors
It becomes too wide for nMOS transistors,
As a result, the parasitic resistance of the nMOS transistor increases,
The current driving capability is reduced. Conversely, nMOS transistors
The optimum sidewall width for the transistor is the pMOS transistor.
Too short for the transistor
The suppression may be insufficient.

As described above, in the conventional CMOS transistor manufacturing process, it is impossible to set the sidewall width to the optimum value for both the nMOS transistor and the pMOS transistor. There has been a problem that the suppression of the effect becomes insufficient and the current driving capability also decreases.

Further, the sidewall width actually set in this manner generally becomes an unnecessarily large value for an nMOS transistor.
There is a problem that the area occupied by the nMOS transistor increases and hinders the increase in the density of the CMOS transistor.

In general, it is necessary to sufficiently activate the impurities in the S / D region to lower the parasitic resistance in order to improve the current driving capability. Therefore, it is desirable to perform a high-temperature heat treatment. Since it is necessary to make the LDD region as shallow as possible to suppress the effect, it is desirable to perform a low-temperature heat treatment.

However, in the above-described conventional CMOS transistor manufacturing process, the impurity ion implantation for forming the LDD region is performed before the impurity ion implantation for forming the S / D region. The effect of the heat treatment for activation naturally affects the LDD region. As a result, when the heat treatment temperature is increased to lower the resistance of the S / D region, the current driving capability is improved, but the LDD region is improved.
As the region becomes deeper, suppression of the short channel effect becomes insufficient. This is a particularly serious problem for a pMOS transistor using an impurity having a larger diffusion coefficient than an nMOS transistor.

B is usually used as a p-type impurity for forming a pMOS transistor. Gallium (Ga) and indium (In) have a small diffusion coefficient as compared with B, which is advantageous in forming a shallow LDD region, but have a low activation rate and a high resistance in the S / D region, deteriorating transistor characteristics. There was a problem of letting it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a CMOS transistor capable of both suppressing the short channel effect and improving the current driving capability and increasing the density.

[0018]

Means for Solving the Problems The above problems can be solved by nM
Forming a gate electrode in the OS transistor formation region and the pMOS transistor formation region, forming an n ⁻ layer by selectively introducing an n-type impurity into the nMOS transistor formation region using the gate electrode as a mask; Forming a first sidewall on a side surface of the electrode;
Forming a p ⁺ layer by selectively introducing a p-type impurity into the pMOS transistor formation region using the gate electrode and the first sidewall as a mask; and removing the first sidewall to remove the gate. Forming a second sidewall narrower than the first sidewall on the side surface of the electrode; and selectively using an n-type impurity in the nMOS transistor formation region using the gate electrode and the second sidewall as a mask. To form an n ⁺ layer, and using the gate electrode and the second side wall as a mask to form the n ⁺ layer.
Selectively introducing a p-type impurity S transistor forming region p ^- method of manufacturing a semiconductor device which comprises forming a layer or, the p after forming the p ⁺ layer ^-
A step of performing a first heat treatment before forming a layer, and a step of performing a second heat treatment at a lower temperature than the first heat treatment after forming the p ⁻ layer. Manufacturing method, or nMOS transistor formation region and p
A step of forming a gate electrode in the MOS transistor formation region, a step of selectively introducing an n-type impurity into the nMOS transistor formation region using the gate electrode as a mask to form an n ⁻ layer, and a step of forming the n ⁻ layer using the gate electrode as a mask. pMOS
By selectively introducing p-type impurities into the transistor
^- forming a layer, and forming a first side wall on the side surfaces of the gate electrode, the gate electrode and the first
Forming ap ⁺ layer by selectively introducing a p-type impurity into the pMOS transistor formation region using the side wall of the gate as a mask; and, after removing the first side wall, forming the first side wall on the side surface of the gate electrode. Forming a second side wall narrower than the side wall of the nMOS; and forming the nMOS using the gate electrode and the second side wall as a mask.
An n-type impurity is selectively introduced into the transistor
^A method of manufacturing a semiconductor device, including a step of forming a ⁺ layer, or a method of manufacturing the semiconductor device, wherein indium or gallium is used as a p-type impurity for forming the p ⁻ layer. Alternatively, it is achieved by the above-described method for manufacturing a semiconductor device, wherein germanium is introduced at the same time as indium or gallium is introduced.

When the impurity used for forming the nMOS transistor has a smaller diffusion coefficient than the impurity used for forming the pMOS transistor, the optimum value of the sidewall width used for forming the nMOS transistor is determined by the side wall used for forming the pMOS transistor. The width is smaller than the optimum value.

According to the first aspect, the p ⁺ layer serving as the S / D region of the pMOS transistor is formed using the first side wall as a mask, and the second side is narrower than the first side wall. N using the wall as a mask
Since the n ⁺ layer serving as the S / D region of the MOS transistor is formed, even if the impurity used for forming the p ⁺ layer has a larger diffusion coefficient than the impurity used for forming the n ⁺ layer, the p ⁺ The optimum sidewall width can be set for each of the nMOS transistors, the short channel effect can be suppressed and the current driving capability can be improved as compared with the conventional case, and the width can be reduced when the manufacturing process is completed. Since only the narrow second sidewall is left, the occupied area of the semiconductor device can be reduced as compared with the related art.

Further, since the p ⁺ layer can be formed before the p ⁻ layer, the temperature of the subsequent second heat treatment can be reduced by sufficiently activating the impurities of the p ⁺ layer by the first heat treatment. Even if the temperature is lower than the temperature of the first heat treatment, p ⁺
It does not affect the resistance of the layer. Therefore, by performing the second heat treatment at a temperature lower than the first heat treatment as shown in claim 2, without causing the increase in resistance of the p ⁺ layer p ^-
It is possible to make the layer shallower. That is, the short channel effect on the pMOS transistor can be suppressed without lowering the current driving capability.

The third aspect is the same as in the conventional example.^-Layer p⁺
2. The invention according to claim 1, wherein the layer is formed before the layer.
PMOS using the first sidewall as a mask
P serving as the S / D region of the transistor⁺When the layer is formed
In addition, the second support, which is narrower than the first sidewall, is provided.
S of nMOS transistor using
/ D region n⁺Since a layer is formed, p⁺Layer shape
The impurity used for formation is n ⁺Compared to the impurities used to form the layer
PMOS transistor even when the diffusion coefficient is large
The optimum for each of the
It is now possible to set the sidewall width
Compared to the short channel effect suppression and current drive capability
Can be improved and when the manufacturing process is completed
Semi-conductive because only the narrow second sidewall is left
The occupied area of the body device can be reduced.

Further, as shown in claim 4, p ^- shallow with small Ga or In of the diffusion coefficient as a p-type impurity for forming the layer p ^- even more short channel effect by forming a layer Can be suppressed. In this case, if, for example, B having a high activation rate is used as an impurity for forming the p ⁺ layer, a decrease in current driving capability can be suppressed.

When Ga or In is introduced, Ge and In
When Si is introduced, a SiGe mixed crystal is formed and the solid solubility limit can be substantially increased, so that the resistance of the p ⁻ layer can be reduced as compared with the case where Ga or In is introduced alone.

[0025]

1 and 2 are sectional views showing a main part of a CMOS transistor manufacturing process according to a first embodiment of the present invention. First, as shown in FIG.
An S transistor formation region 1, a pMOS transistor formation region 2, and an element isolation region 3 are formed, and a gate oxide film 4 and a gate electrode 5 are formed on the nMOS transistor formation region 1 and the pMOS transistor formation region 2. The thickness of the gate oxide film 4 is 5 nm, and the thickness of the gate electrode 5 is 100 nm.
A 150 nm-thick polycrystalline silicon film using the silicon oxide film as a cap layer. Alternatively, the gate electrode 5 may have a structure in which TiN is sandwiched between the silicon oxide film and polycrystalline silicon.

Next, as shown in FIG. 1B, the nMOS transistor forming region 1 is formed using the gate electrode 5 as a mask.
At an acceleration energy of 10 KeV and a dose of 1 × 10 ¹⁴ cm ^-2
As ion is selectively implanted and nMOS transistor LD
An n ⁻ layer 6 serving as a D region is formed.

Then, as shown in FIG. 1C, a first sidewall 7 having a width of 160 nm is formed on the side surface of the gate electrode 5 by anisotropic dry etching after depositing a silicon oxide film on the entire surface. . Silicon oxide film is low temperature thermal CVD method,
It can be deposited by a well-known film forming method such as a plasma CVD method or a high-temperature thermal CVD method. Alternatively, a BSG film, a PSG film, a BPSG film, a silicon nitride film, or the like can be used instead of the silicon oxide film.

Next, as shown in FIG. 1D, the pMOS transistor formation region 2 is formed using the gate electrode 5 as a mask.
At an acceleration energy of 10 KeV and a dose of 1 × 10 ¹⁵ cm ^-2
BF ₂ ions are selectively implanted and the S
A p ⁺ layer 8 serving as a / D region is formed.

Subsequently, the first sidewall 7 is removed. Here, if the silicon oxide film is formed by the low-temperature thermal CVD method or the plasma CVD method in the step shown in FIG. 1C, the first sidewall 7 is formed by wet etching using an HF-based processing solution. Removal is easier.

Then, as shown in FIG. 2A, a silicon oxide film is deposited and a second sidewall 9 having a width of 40 nm is formed on the side surface of the gate electrode 5 by anisotropic dry etching. At this time, the silicon oxide film is also formed by a low-temperature thermal CVD method,
It can be deposited by a well-known film forming method such as a plasma CVD method or a high-temperature thermal CVD method. Alternatively, a BSG film, a PSG film, a BPSG film, a silicon nitride film, or the like can be used instead of the silicon oxide film.

Then, as shown in FIG. 2B, the nMO is performed using the gate electrode 5 and the second side wall 9 as a mask.
As ions are selectively implanted into the S transistor formation region 1 under the conditions of an acceleration energy of 10 KeV and an implantation amount of 4 × 10 ¹⁵ cm ^−2.
An n.sup. ⁺ Layer 10 serving as an S / D region of a MOS transistor is formed.

Next, a heat treatment for activating the impurities implanted in the above steps is performed. At this stage, since ion implantation of impurities for forming the LDD region of the pMOS transistor has not been performed yet, pMOS
The most advantageous heat treatment conditions for reducing the resistance of the gate electrode 5, the p ⁺ layer 8, and the n ⁺ layer 10 can be set without considering the expansion of the LDD region of the transistor. Here, heat treatment is performed at a high temperature of about 1000 ° C. for about 10 seconds.

It should be noted that the heat treatment at a high temperature makes the nMO
The activation of the n ⁻ layer 6 which becomes the LDD region of the S transistor is also performed at the same time, but since the diffusion coefficient of As is sufficiently smaller than that of B, it does not become deeper than the p ⁻ layer formed in a later step. There is no problem in suppressing the short channel effect on the nMOS transistor.

Then, as shown in FIG. 2C, the pMO is formed using the gate electrode 5 and the second side wall 9 as a mask.
BF ₂ ions are selectively implanted into the S transistor formation region 2 under the conditions of an acceleration energy of 10 KeV and an implantation amount of 1 × 10 ¹⁴ cm ⁻² to form a p ⁻ layer 11 which becomes an LDD region of a pMOS transistor.

Then, p^-Impurities implanted in layer 11
A heat treatment for activating the object is performed. As mentioned earlier,
Port electrode 5, p⁺Layer 8, n⁺Layer 10 is heat treated at high temperature.
Already fully activated, p^-Activation of layer 11
Heat treatment temperature lower than previous heat treatment temperature
be able to. Here, the heat treatment temperature is suppressed to about 900 ° C.
For this reason, the gate electrode 5, p⁺Layer 8, n⁺Layer 10 high
P without resistance ^-Layer 11 can be shallow.

Subsequently, a CMOS transistor is completed through an interlayer insulating film forming step, a metal wiring forming step, and the like. In the present invention, since the first sidewall is removed during the process, only the narrow second sidewall needs to be considered when laying out the device, and the area occupied by the CMOS transistor can be reduced accordingly. .

Next, the CMO according to the second embodiment of the present invention will be described.
An S transistor manufacturing process will be described with reference to FIGS. First, as shown in FIG. 3A, an nMOS transistor formation region 1, a pMOS transistor formation region 2, and an element isolation region 3 are formed, and a film thickness of 5 nm is formed on the nMOS transistor formation region 1 and the pMOS transistor formation region 2.
And a gate electrode 5 made of a 150 nm-thick polycrystalline silicon film using a 100 nm-thick silicon oxide film as a cap layer. Alternatively, a structure in which TiN is interposed between the silicon oxide film and polycrystalline silicon may be employed.

Next, as shown in FIG. 3B, the nMOS transistor forming region 1 is formed using the gate electrode 5 as a mask.
At an acceleration energy of 10 KeV and a dose of 1 × 10 ¹⁴ cm ^-2
As ion is selectively implanted and nMOS transistor LD
An n ⁻ layer 6 serving as a D region is formed.

Next, as shown in FIG. 3C, the pMOS transistor formation region 2 is formed using the gate electrode 5 as a mask.
At an acceleration energy of 10 KeV and an injection amount of 4 × 10 ¹⁴ cm ^-2
In ions or Ga ions are selectively implanted to form ap ⁻ layer 11 which becomes an LDD region of the pMOS transistor.

Then, as shown in FIG. 3D, a first sidewall 7 having a width of 160 nm is formed on the side surface of the gate electrode 5 by anisotropic dry etching after depositing a silicon oxide film on the entire surface. . Silicon oxide film is low temperature thermal CVD method,
It can be deposited by a well-known film forming method such as a plasma CVD method or a high-temperature thermal CVD method. Alternatively, a BSG film, a PSG film, a BPSG film, a silicon nitride film, or the like can be used instead of the silicon oxide film.

Then, as shown in FIG. 4A, the pMOS transistor formation region 2 is formed using the gate electrode 5 as a mask.
At an acceleration energy of 10 KeV and a dose of 1 × 10 ¹⁵ cm ^-2
BF ₂ ions are selectively implanted and the S
A p ⁺ layer 8 serving as a / D region is formed.

Subsequently, the first sidewall 7 is removed. Here, if the silicon oxide film is formed by the low-temperature thermal CVD method or the plasma CVD method in the step shown in FIG. 3D, the first sidewall 7 is formed by wet etching using an HF-based processing solution. Removal is easier.

Next, as shown in FIG. 4B, a silicon oxide film is deposited and a second sidewall 9 having a width of 40 nm is formed on the side surface of the gate electrode 5 by anisotropic dry etching. At this time, the silicon oxide film is also formed by a low-temperature thermal CVD method,
It can be deposited by a well-known film forming method such as a plasma CVD method or a high-temperature thermal CVD method. Alternatively, a BSG film, a PSG film, a BPSG film, a silicon nitride film, or the like can be used instead of the silicon oxide film.

Next, as shown in FIG. 4C, the nMO is performed using the gate electrode 5 and the second sidewall 9 as a mask.
As ions are selectively implanted into the S transistor formation region 1 under the conditions of an acceleration energy of 10 KeV and an implantation amount of 4 × 10 ¹⁵ cm ^−2.
An n.sup. ⁺ Layer 10 serving as an S / D region of a MOS transistor is formed.

Next, a heat treatment (RTA) at 1000 ° C. for 10 seconds
Process) to activate the ion-implanted impurities.

As described above, in the second embodiment, Ga exists.
Or shallow p by using In ^-Forming layer 11
And p⁺B is used for forming the layer 8.
To form a low-resistance S / D region.
Suppresses the short channel effect compared to the conventional as in the embodiment
In addition, this is effective in improving the current driving capability.

In the second embodiment, unlike the first embodiment, the p ^- layer 11 is formed before the p ⁺
The effect of the heat treatment on ⁺ layer 8 also affects p ⁻ layer 11. However, p ^- Since the layer 11 small In or Ga diffusion coefficient is injected by the high-temperature heat treatment p ^- spreading the effect of suppression of small short-channel effect in comparison with the case of using B layer 11 in the prior art Larger than compared.

Furthermore, in the second embodiment, since the first sidewall is removed during the process as in the first embodiment, only the narrow second sidewall is taken into account during device layout. It suffices to reduce the area occupied by the CMOS transistors.

Also, when implanting Ga and In ions,
Ion can be simultaneously implanted with Ge. Ge
Of SiGe mixed crystal is formed by ion implantation of
Since a and In can increase the solid solubility limit, Ga and In
Compared to the case of using ^-Lower resistance of layer 11
Can be

In the case of using Ga and Ge, the implantation conditions of Ge at an acceleration energy of 15 KeV and an implantation amount of 1 × 10 ¹⁶ cm ⁻² , and the implantation conditions of Ga at an acceleration energy of 10 KeV and an implantation amount of 4 × 10 ¹⁴ cm ⁻² are used. Used. At this time, Ge is ion-implanted first, and then
When Ga is ion-implanted, the distribution of Ga can be made shallower.

In the case of using In and Ge, the implantation conditions of Ge at an acceleration energy of 15 KeV and an implantation amount of 1 × 10 ¹⁶ cm ^{−2 and} the implantation conditions of In at an acceleration energy of 10 KeV and an implantation amount of 4 × 10 ¹⁴ cm ⁻² are used. Used. At this time, Ge is ion-implanted first, and then
By implanting In, the distribution of In can be made shallower.

[0052]

As described above, according to the present invention, by forming the first sidewall and the second sidewall, it is possible to both suppress the short channel effect of the CMOS transistor and improve the current driving capability. Further, only the narrow second sidewall is left after the completion of the manufacturing process, so that the area occupied by the CMOS transistor is reduced, and the chip area can be reduced as compared with the conventional case. Further, by using Ga or In for forming the LDD region of the pMOS transistor, the short channel effect can be more effectively suppressed, and the CM
This is advantageous in increasing the speed of a semiconductor device including an OS transistor and reducing the chip area.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a first embodiment of the present invention (part 1).

FIG. 2 is a process sectional view showing the first embodiment of the present invention (part 2).

FIG. 3 is a process sectional view showing a second embodiment of the present invention (part 1).

FIG. 4 is a process sectional view showing a second embodiment of the present invention (part 2).

FIG. 5 is a process sectional view showing a conventional example (part 1).

FIG. 6 is a process sectional view showing a conventional example (part 2).

[Explanation of symbols]

1, 21 nMOS transistor formation region 7 first
Side wall 2, 22 pMOS transistor formation region 8, 30
p ⁺ layer 3, 23 element isolation region 9 second
Side wall 4, 24 Gate oxide film 10, 29
n ⁺ layer 5, 25 Gate electrode 11, 27
p ^- layer 6, 26 n ^- layer 28 sidewall

Continued on the front page F term (reference) 5F048 AA01 AC03 BA01 BB05 BB09 BB12 BC06 BC15 BG12 DA25 DA27 DA29 DA30

Claims (5)

[Claims] 1. An nMOS transistor forming region and a pMO
Forming a gate electrode in the S transistor formation region, selectively introducing an n-type impurity into the nMOS transistor formation region using the gate electrode as a mask, and forming an n ⁻ layer; Forming a p ⁺ layer by selectively introducing a p-type impurity into the pMOS transistor formation region using the gate electrode and the first side wall as a mask; Forming a second sidewall narrower than the first sidewall on a side surface of the gate electrode after removing the sidewall of the nMOS; and using the gate electrode and the second sidewall as a mask to form the nMOS. the p forming a selectively introducing an n-type impurity into the transistor forming region n ⁺ layer, the gate electrode and the second side wall as a mask The method of manufacturing a semiconductor device which comprises forming a layer ^- OS transistor forming region selectively introducing a p-type impurity into the p. 2. A step of performing a first heat treatment after forming the p ⁺ layer and before forming the p ^- layer; and forming a second heat treatment at a lower temperature than the first heat treatment after forming the p ^- layer. 2. The method according to claim 1, further comprising the step of:
The manufacturing method of the semiconductor device described in the above. 3. An nMOS transistor forming region and a pMO
Forming a gate electrode in the S transistor formation region, selectively introducing an n-type impurity into the nMOS transistor formation region using the gate electrode as a mask to form an n ⁻ layer, using the gate electrode as a mask, forming a p ⁻ layer by selectively introducing a p-type impurity into a pMOS transistor formation region; forming a first sidewall on a side surface of the gate electrode; the gate electrode and the first sidewall Forming ap ⁺ layer by selectively introducing a p-type impurity into the pMOS transistor formation region using the mask as a mask; and, after removing the first sidewall, forming a first sidewall on a side surface of the gate electrode. Forming a second sidewall having a smaller width; and forming the nMOS transistor using the gate electrode and the second sidewall as a mask. The method of manufacturing a semiconductor device characterized by comprising the steps of forming a selectively introduced n ⁺ layer with an n-type impurity. 4. The method according to claim 3, wherein indium or gallium is used as a p-type impurity for forming the p ⁻ layer. 5. When introducing indium or gallium,
5. The method according to claim 4, wherein germanium is introduced at the same time.