JP2000232144A - Semiconductor device and method for inspecting its contact resistance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire the distribution, etc., of the contact resistance of a semiconductor device with accuracy by defining the contact resistance value corresponding to the inspecting standard of a method for inspecting contact resistance, by providing a resistance monitor composed of a contact having a higher resistance than the other contacts have in a contact array by positioning the monitor in advance. SOLUTION: The inspecting standard of a method for inspecting contact resistance can be made to be set quickly and accurately by providing a resistance monitor 51 composed of a high-resistance contact in an ordinary contact array, by positioning the monitor 51 in advance and estimating in advance the resistance value of the monitor 51. Namely, an inspecting standard value is set so that the monitor 51 may be recognized as a defect and the value is applied to other areas. Since the monitor 51 is provided in advance in the contact array in this embodiment, the position of the monitor 51 in the array is known in advance. Therefore, the propriety of the inspecting standard value can be judged by discriminating whether or not the contact at the position is judged as a high resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a contact resistance inspection method, and more particularly, to a semiconductor device having a contact array for inspecting contact resistance and a contact resistance inspection method thereof.

[0002]

2. Description of the Related Art In a process for forming a contact hole in a semiconductor device, the etching rate depends on the aspect ratio of the contact hole, and the shape of a resist mask affects the shape of the contact hole.
The fact that the etching rate is affected by various conditions causes variations in contact resistance and poor contact. In addition, various abnormalities other than the contact hole etching process, such as the occurrence of an abnormal high-resistance layer on the substrate surface in the contact hole during cleaning and drying, the abnormal shape of the conductive film embedded in the contact hole, and the decrease in adhesion. The cause of contact abnormalities in a simple process. Therefore, in order to evaluate the manufacturing process and the element structure, it is necessary to advance the product development while evaluating the contact resistance value and its variation and the yield. If an abnormality is found in the contact resistance, it is necessary to identify the position of the defective contact, perform a physical analysis such as a shape analysis, and quickly determine the cause of the defect, and improve the process in question. is there. Furthermore, in order to improve the yield during mass production, it is important to measure the contact resistance at all times or periodically, and to evaluate the resistance value, the yield, and analyze the failure.

However, factors other than the contact process affect the product yield and defects, and it takes a considerable amount of labor and time to distinguish only contact defects by analysis. Therefore, conventionally, an inspection test wafer for measuring a contact resistance has been manufactured and periodically managed and monitored so that only a contact defect and a product yield resulting therefrom can be inspected in a short period of time. FIG. 8A is a cross-sectional view showing a configuration of the test wafer for inspection, and FIG. 8B is a top view thereof. As shown in the drawing, the test wafer for inspection has a large number of contacts in which the conductive layer 7 buried in the contact hole 6 formed in the interlayer insulating film 5 and the diffusion region 4 are in contact with each other. It comprises a contact resistance measuring circuit called a contact chain connected in series by the electrodes 8. In this manufacturing method, first, a normal LOCOS (LOCal Oxidation of Si) is formed on a semiconductor substrate 1 having a P-well region 2 formed on a surface layer.
The element isolation insulating film 3 is formed by using the (licon) method. A region surrounded by the element isolation insulating film 3 is a contact formation region.

Next, after forming a thin oxide film (not shown) for preventing contamination, an N-type impurity is introduced only into the region where the contact resistance is to be measured. Next, after an interlayer insulating film 5 is formed on the entire surface, a heat treatment is performed to activate the ion-implanted impurities, thereby forming an N-type diffusion region 4 in the P-well region 2. Subsequently, two contact holes 6 are formed in the interlayer insulating film 5 on the N-type diffusion region 4 per N-type diffusion region 4. Next, a laminated thin film of titanium and titanium nitride is formed in the contact hole 6 by a sputtering method to form a barrier metal, and then tungsten is buried to form a plug 7. The plug 7 is formed by contact between the diffusion region 4 and the plug 7. Form a contact. Thereafter, by forming the wiring / electrode 8 for connecting the plug 7 between the adjacent contact formation regions, a large number of contacts are formed in the diffusion region 4 and the wiring / electrode 8.
Thereby, a contact resistance measuring circuit called a contact chain connected in series is completed. At this time, in order to apply a voltage to the contact chain, the pads 9a, 9
b is formed so as to be connected to the contacts at both ends of the chain structure. The resistance is measured by connecting one pad 9a to the ground, applying a voltage to one pad 9b, and detecting a current. However, according to this method using a contact chain, even if a very small number of high-resistance contacts are included in a large number of normal contacts, if the contact value does not affect the resistance value of the entire contact chain, the contact is not affected. It may not be possible to determine whether the chain contains high resistance contacts. Further, even if it can be determined that the contact chain includes the high-resistance contact, there is a problem that the position cannot be specified by a normal method.

Accordingly, a method for specifying the position of a high resistance contact in a contact chain is disclosed in Japanese Patent Laid-Open No. 4-2902.
No. 42 and Japanese Unexamined Patent Publication No. 4-274339 describe a scanning electron microscope (SEM).
e) or focused ion beam (FIB)
m) is disclosed. This contact resistance measuring circuit is shown in FIGS. 9 (a) and 9 (b). FIG. 9A is a sectional view, and FIG. 9B is a top view. As shown in FIG. 9, one pad 9a is formed on the interlayer insulating film 5 in a region where the P well region 2a is not formed, and the silicon substrate 1 is formed through a plug 7a embedded in a contact hole 6a of the interlayer insulating film 5. Connected to Although not shown in the figure, a part or a plurality of portions of the contact chain is in contact with the silicon substrate 1. In FIG. 8, FIG.
The same reference numerals are given to the same components as those of the above-mentioned components, and the description thereof will be omitted.

The contact chain is observed using FIB or SEM, and a secondary electron image is obtained. Charged particles are irradiated to the entire circuit at the time of observation, but the electric potential between the wire / electrode 8 connected to the high-resistance contact 10 and the pad 9a connected to the silicon substrate 1 is such that the electric charge is on the silicon substrate 1 side. The wiring / electrode 8 on the open end side of the high-resistance contact 10 is charged up to a high potential because of the potential distribution of the secondary substrate according to the potential difference. Differences occur. A secondary electron detector having an amplification factor that reflects this energy difference is used. In the case of a detection system having a secondary electron detector provided with an energy filter, the current detection amount or the secondary electron detection amount of the secondary electron detector is adjusted by adjusting the set value of the energy filter. Is caused. It is stated that the broken portion and the position of the high-resistance contact 10 can be specified from the contrast difference of this image (this is called a voltage contrast).

Further, as an example using voltage contrast, a method is employed in which the amount of secondary electrons is detected by using an SEM while eliminating various fluctuation factors and a defect (high-resistance contact) is inspected. There is also. FIG. 10A is a top view of an inspection wafer used for this, and contact holes 16a, 16a are formed in the interlayer insulating film 15 using a resist film as a mask.
This shows a state after the formation of b, 16c and removal of the resist film. FIG. 10B is a cross-sectional view taken along the line II of FIG. In the figure, contact holes 16a, 1
6b penetrates and contacts the N-type diffusion regions 14a and 14b, but the contact hole 16c does not penetrate. Reference numeral 11 denotes a silicon substrate, 12 denotes an N-type well region, and 13 denotes an element isolation insulating film.

According to this inspection, as shown in FIG. 10B, most of the irradiated electrons flow into the silicon substrate 1 in the penetrated contact holes 16a and 16b.
Electrons cannot flow into the silicon substrate 1 in the contact hole 16c that does not penetrate, and
c and remains on the periphery thereof. Although the plug and the wiring / electrode are omitted in the drawing, the same applies to the case where a contact having the plug and the wiring / electrode is formed. This difference causes a potential difference near the contact holes 16b and 16c. A difference occurs in the signal intensity of the detection system according to the potential difference, and a difference (voltage contrast) appears in the SEM image. However, the amount of secondary electrons emitted depends on the cleanliness of the surface of the object to be detected, the degree of vacuum inside the device, the irradiation history, the amount of current, the scanning speed, the capacitance of the resistance measurement circuit, the structure in the silicon substrate, the resistance value, It is practically impossible to directly estimate the contact resistance from the amount of secondary electron emission, because it is affected by various factors such as a method of connecting to the reference potential.

In the above two methods, the amount of secondary electrons emitted depends on the cleanliness of the surface of the object to be detected, the degree of vacuum inside the apparatus, the irradiation history, the amount of current, the scanning speed, the capacity of the resistance measuring circuit, and the structure in the silicon substrate. , Resistance, and the method of connecting the entire silicon substrate to the reference potential.
There is a problem that it is practically impossible to directly estimate the contact resistance from the amount of secondary electron emission. Further, according to the methods described in JP-A-4-290242 and JP-A-4-274339, when there are a large number of defective contacts, it is not always possible to detect the positions of all the defective portions. Therefore, such a difficult-to-control factor (2)
In order to eliminate as much as possible the fact that the secondary electron intensity depends on various conditions), as shown in the figure, the secondary electron intensity from adjacent contact holes is compared, or adjacent SEM images are compared. Then, it is a certain inspection reference value (a reference for judging that there is an abnormality by comparison, hereinafter also referred to as a threshold value. Specifically, the secondary electron intensity is set so as to be low by what%, etc.). ) Is adopted as a method of recognizing a defect when the value exceeds. In addition, it is often the case that defective contacts are detected using a defect inspection device, the product wafer usually has a contact array structure, and if there are many defects, all defects are inspected in a chain structure. In general, a periodic contact array is often used as an inspection pattern because it is not always possible.

[0010]

However, in the conventional example using the contact array, the position of the high-resistance contact is detected by a defect inspection apparatus using an SEM or an appearance inspection using an SEM. In this case, it is necessary to set a criterion (threshold) for determining the degree of difference in the signal strength and determining whether the signal strength is high. In this case, if the threshold value is set lower than necessary, the number of contacts (pseudo-defects) determined to be defective even though they are normal contacts increases, and the reliability of inspection is significantly reduced. In addition, when the threshold value is gradually increased, the number of contacts recognized as a defect decreases, and the defect may be overlooked. Normally, the threshold value is set so high that there is no false defect and low enough that no defect is overlooked. However, since there is no method for directly measuring the resistance value, there is a problem in that it is not possible to obtain information as to how much resistance the set threshold value has detected.

In addition, the inspection conditions may be shifted, for example, when the surface condition of the inspection wafer is different. In this case, even if the resistance value of the inspected high-resistance contact is deviated, the inspection is performed in a normal inspection method. There is also a problem that it cannot be found. In addition, when measuring an outline of the distribution of the contact resistance to be inspected, or when it is desired to detect only a contact having a resistance value of a certain level or more, it is possible in principle to change the threshold value. In the conventional method, there is also a problem that since the relationship between the threshold value and the detected resistance value is not clear, such measurement and the like are practically impossible.

The present invention has been made in view of the above circumstances, and it is possible to clarify how much the contact resistance corresponds to the inspection reference value and to obtain the contact resistance distribution and the like with high accuracy. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the reliability of defect inspection by eliminating detection of false defects and oversight of defects.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of contacts formed by contacting an impurity region of a semiconductor layer with a conductive layer. A semiconductor device having a contact array is characterized in that one or more resistance monitors composed of contacts having higher resistance than other contacts are provided in the contact array in advance.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the impurity concentration of the impurity region in the resistance monitor is lower than the impurity concentration of the impurity region in a contact around the resistance monitor. It is characterized by having.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, a contact area between the impurity region and the conductive layer in the resistance monitor is different from that of the impurity region in a contact around the resistance monitor. It is characterized in that it is smaller than the contact area with the layer.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect, wherein the resistance monitor comprises a plurality of types of resistance monitors having different contact areas.

According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect, the resistance of the conductive layer in the resistance monitor is higher than the resistance of the conductive layer in a contact around the resistance monitor. It is characterized by.

According to a sixth aspect of the present invention, there is provided the semiconductor device according to any one of the first to fifth aspects, wherein the method of forming the high-resistance contact is the same as the method of forming the high-resistance contact in a region different from a region where the contact array is formed. Is characterized in that a resistance measuring circuit is created by the method.

According to a seventh aspect of the present invention, there is provided a method for inspecting contact resistance of a semiconductor device, wherein a plurality of contacts formed by contacting an impurity region of a semiconductor layer and a conductive layer are arranged in a contact array. A contact resistance inspection method of a semiconductor device for detecting a contact having a high resistance, wherein at least one resistance monitor including a contact having a resistance higher than that of another contact is provided in the contact array in advance and provided. Is set as an inspection reference value that is determined to be defective.

The invention according to claim 8 relates to the contact resistance inspection method for a semiconductor device according to claim 7, wherein the resistance value of the resistance monitor is directly measured, and the inspection reference value is set based on the measured value. It is characterized by:

According to a ninth aspect of the present invention, there is provided a method for inspecting a contact resistance of a semiconductor device according to the seventh aspect, wherein a resistance is measured in a region different from a region where the contact array is formed by the same method as that of forming the resistance monitor. A circuit is created,
By measuring the resistance value of the high resistance contact in the resistance measurement circuit corresponding to the resistance monitor, the resistance value of the resistance monitor in the contact array is estimated, and the inspection reference value is set based on this value. It is characterized by:

The invention according to claim 10 is the invention according to claim 7.
According to the method for testing the contact resistance of a semiconductor device according to the above, after arbitrarily changing the inspection reference value and classifying the contacts for each of the inspection reference values, by measuring the resistance value of the contact within each of the inspection reference values, A relationship between the inspection reference value arbitrarily set and the resistance value of the contact corresponding to the inspection reference value is obtained, and the inspection reference value is set based on this relationship.

The invention according to claim 11 is the same as the invention according to claim 7.
11. A method for inspecting contact resistance of a semiconductor device according to any one of Items 10 to 10, wherein the contact resistance is compared by irradiating the charged particles and comparing the amount of secondary electrons emitted from the irradiated area. It is characterized by.

According to a twelfth aspect of the present invention, there is provided a method for inspecting contact resistance of a semiconductor device according to any one of the seventh to tenth aspects, wherein the semiconductor device is irradiated with charged particles and is absorbed in a semiconductor substrate. It is characterized in that the contact resistance is compared by comparing the amount of current.

[0025]

According to the structure of the semiconductor device of the present invention, the resistance monitor of the high-resistance contact is formed in a predetermined position in the contact array. In principle, a contact array refers to a case where contacts are isolated from each other and a case where the contacts have a periodic structure. However, the contact array referred to in this specification is such that contacts are connected in series or the like. And a case without a periodic structure. In this case, a resistance measurement circuit having a contact structure similar to that of the resistance monitor is provided in a region different from the formation region of the contact array, and the resistance value of the resistance monitor in the contact array is estimated by measuring the contact resistance. . Alternatively, a current detection type atomic force microscope (AFM)
The contact resistance of the resistance monitor in the actual contact array is measured directly by bringing the electrode into contact with the plug using a scope or a fine contact probe.

Thus, when a defect is inspected by a defect inspection apparatus using an SEM or by a visual inspection using an SEM, the amount of secondary electrons emitted and the contact amount are adjusted so that the resistance monitor is judged as a defect. An inspection reference value (threshold) for the amount of secondary electrons is set by associating the measured value or the estimated value of the resistance. In addition, the inspection reference value of the amount of secondary electrons emitted is set arbitrarily, contacts corresponding to each inspection reference value are detected and classified, and the contact resistance of the contact within each inspection reference value is directly measured. An inspection reference value is set from the relationship between the reference value and the corresponding contact resistance value.

In this case, in particular, by arranging the contacts in a very small period or in a very narrow region, the contact resistance can be evaluated under almost the same conditions, and the deviation between the inspection reference value and the actual contact resistance can be reduced. be able to.
By adopting these methods, it is possible to clarify what contact resistance value is detected as a bad contact, and to improve the reliability of defect inspection by eliminating false defect detection and defect oversight. Can be. Furthermore, by setting the inspection reference value to the same resistance value each time, comparison can be performed for a long period or between a plurality of inspection wafers.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a top view showing an arrangement of a contact array formed on a contact inspection wafer according to a first embodiment of the present invention. FIG. 2A is a top view of a contact resistance measuring circuit formed in a peripheral portion of a contact array forming region, and FIG. 2B is a cross-sectional view along the line III-III of FIG. 2A. In the inspection wafer of this embodiment, as shown in FIG. 1, a semiconductor substrate is separated into a plurality of contact formation regions by an element isolation insulating film, and one contact is formed per one contact formation region.
Each contact includes a diffusion region formed in the surface layer of the semiconductor substrate in the contact formation region, contact holes 27a to 27c formed in the interlayer insulating film on the diffusion region, and plugs 28a to 28c embedded in the contact hole.
The plugs 28a to 28c are brought into contact with each other and the plug 2
8a to 28c are electrically separated from each other, and are constituted by independently provided wiring / electrodes 29a to 29c. A set of these contacts constitutes a contact array. In the contact array, for example, the number of fabricated high-resistance contacts (resistance monitors) per 1M low-resistance contacts is periodically arranged so as to be about 500. The reason why the contacts are periodically arranged is that a defect inspection apparatus used for defect inspection compares a periodic structure.

Further, as shown in FIG. 2A, a contact resistance measuring circuit is prepared in the peripheral portion of the contact array forming region shown in FIG. 1, and the contact resistance is measured to measure the contact resistance in the contact array. The resistance value of the resistance monitor can be estimated. The arrangement of the contacts in this contact resistance measuring circuit is such that the exposure and etching conditions of the resist are the same as those of the contact array as much as possible. The contact resistance measuring circuit is shown in FIG.
As shown in FIG. 2, unlike the contact array of the contact array formation region of FIG. 1, the high concentration diffusion region 24d and the low concentration diffusion region 24e are formed in the same contact formation region so as to partially overlap each other. Diffusion area 24e
A high-resistance contact plug 28e that contacts the high-concentration diffusion region 24d and a low-resistance contact plug 28d that contacts the high-concentration diffusion region 24d are connected in series through the diffusion regions 24d and 24e, and the pads 30a and 3 are respectively connected to the plugs 28d and 28e.
0b so that a voltage can be externally applied.
A large number of such resistance measuring circuits are arranged around the contact array forming region.

Next, a method of manufacturing a semiconductor device incorporating the above-described contact array and resistance measuring circuit will be described. FIG. 3 shows this manufacturing process in the order of the process.
FIG. Here, the contact array portion will be mainly described, and the description of the resistance measurement circuit portion will be omitted. First, as shown in FIG.
An element isolation insulating film 23 is formed on a semiconductor substrate 21 made of silicon having P-type conductivity in which a P-well region 22 is formed by a normal LOCOS method using thermal oxidation. Next, after forming the resist film 25a, an opening is formed in a region of the contact array where a low-resistance contact is formed. Through the opening of the resist film 25a, boron fluoride is accelerated at a voltage of 30 keV and a dose of 3 ×
Ion implantation at 10 ¹⁵ / cm ² and high concentration diffusion region 24
A high concentration P-type impurity is introduced into the regions to be a and 24b.

Next, after removing the resist film 25a, a new resist film 25b is formed as shown in FIG. 3B, and an opening is formed in a region of the contact array where a high-resistance contact is to be formed. Form. Subsequently, through the opening of the resist film 25b, boron fluoride is supplied with an acceleration voltage of about 3
Ion implantation is performed under the conditions of 0 keV and a dose of about 5 × 10 ¹³ / cm ² to introduce a low-concentration P-type impurity into a region where a high-resistance contact is formed. Next, FIG.
As shown in the figure, atmospheric pressure CVD (Chemical Vapor Depositio
a silicon oxide film having a thickness of 100 nm and a
m BPSG (BoroPhosphoSilicate Glass) films are sequentially deposited to form an interlayer insulating film 26, and then, in a nitrogen atmosphere,
A heat treatment is performed at a temperature of 850 ° C.
And the implanted impurities are activated to form P-type high-concentration diffusion regions 24a and 24b and P-type low-concentration diffusion regions 24c. Next, after removing the oxide film formed on the back surface, a resist film (not shown) is formed on the interlayer insulating film 26 on the front surface, and then an opening is formed in the contact formation region, and the interlayer insulating film is formed in the opening. Expose 26. Subsequently, the interlayer insulating film 26 is etched through the opening of the resist film by the plasma etching method to expose the semiconductor substrate 21 and to form the contact holes 27a to 27a.
7c is formed.

Further, a barrier metal layer is formed by sequentially depositing a titanium film and a titanium nitride film while covering the contact holes 27a to 27c by a sputtering method. Subsequently, a tungsten film is formed on the entire surface of the barrier metal layer by a sputtering method, and then etched back by a plasma etching method. Thereby, the contact hole 2
7a to 27, the tungsten film and the barrier metal layer on the interlayer insulating film 26 are removed and the contact hole 2 is removed.
7a to 27c, leaving a tungsten film or the like in the plug 28
a to 28c are formed. At this time, the high concentration diffusion region 24
Plugs (low-resistance contact plugs) 28a and 28b having low-resistance contacts, which are in contact with low-concentration diffusion regions 24c (high-resistance contact plugs)
28c will have a high resistance contact. Next, after forming a titanium nitride film on the entire surface by a sputtering method,
An aluminum copper alloy film is formed thereon by a sputtering method. Subsequently, the aluminum copper alloy film and the titanium nitride film are sequentially etched using a resist film (not shown) newly formed on the aluminum copper alloy film as a mask,
As shown in FIG. 3D, each one plug 28
isolated wires / electrodes 29a-29 that come into contact with a-28c
Form c.

Next, when this is heated in hydrogen at a temperature of about 400 ° C. to lower the contact resistance, a test wafer for contact defect inspection is completed. Although not described above, the portion of the circuit for measuring the contact resistance can be formed in substantially the same manner as in the above steps. Next, a method for measuring the contact resistance value and the resistance variation will be described. First, FIG. 4 shows the result of measuring the contact resistance using the resistance measuring circuit having the configuration shown in FIG. In the figure, the vertical axis indicates the frequency (%) of the measured contact resistance value represented by a linear scale. The horizontal axis represents the contact resistance value (kΩ) expressed on a logarithmic scale.

As shown in FIG. 4, the resistance value of a normal low-resistance contact is as shown in distribution A, and the resistance value of a high-resistance contact is distribution B (in this example, about 1 MΩ is the center of distribution B). become that way. The resistance value of the high resistance contact can be arbitrarily changed by adjusting the impurity concentration of the low concentration diffusion region 24e. Next, the contact in the contact array is measured using the SEM. In the SEM, a beam having a beam diameter of about 0.1 μm φ is formed, and the wafer is irradiated with primary electrons at an acceleration voltage of about 1 to 2 keV and a current amount of about 1 to 100 nA, and is generated from the irradiation area according to the potential of the electrode surface. The secondary electron image to be detected is detected. At this time, the secondary electron detection system may be adjusted so that only electrons having a specific energy or more can be detected, and the difference in the amount of secondary electrons generated from the high-resistance contact and the low-resistance contact may be increased. .

In this inspection method, as described in the prior art, the high-resistance contact and the low-resistance contact are distinguished from each other based on the difference in the amount of secondary electrons emitted from the adjacent periodic structure wiring / electrode. . This utilizes the fact that the amount of secondary electrons emitted is affected by the surface potential of the electrode. That is, the potential of the electrode surface is
If the resistance value between the electrodes is large, a potential difference from the substrate is generated accordingly, and the amount of secondary electrons changes. Further, by comparing the difference in the amount of secondary electrons caused by this potential in a very narrow region, various other factors affecting the amount of secondary electrons can be made the same. In this way, by comparing the amount of emitted secondary electrons between nearby contacts, it is determined whether or not the resistance is high. To that end, the difference in the amount of emitted secondary electrons is determined by the amount of resistance. You have to know in advance what the difference is. Here, the result of FIG. 4 is used.
In the conventional method, this point is unclear, and the inspection reference value (threshold) is set arbitrarily. If the inspection reference value is set too low, a contact that is not abnormal is regarded as a defect. recognize. Conversely, if the inspection reference value is set too high, there is a problem that the probability of missing a defect increases. Also, even if the inspection reference value could be set within an appropriate range, it was not clear how much resistance the contacts were selecting, so its reliability was low and the reproducibility of the inspection was extremely poor There was a problem.

Therefore, in this embodiment, a resistance monitor composed of a high-resistance contact is pre-positioned and formed in a normal contact array, and the resistance value (about 1 MΩ in this example) of the resistance monitor is estimated in advance according to FIG. By doing so, the setting of the inspection reference value can be performed quickly and accurately. That is, an inspection reference value is set so that the resistance monitor can recognize the defect as a defect, and the inspection reference value is applied to other areas. In the contact array of this embodiment, since the resistance monitor is built, the position of the resistance monitor in the contact array is known in advance.
Therefore, the validity of the inspection reference value can be determined based on whether the contact at that position is determined to have high resistance. FIG.
Shows a result obtained by performing an inspection by changing the threshold value using the inspection pattern of the present embodiment, and acquiring the relationship between the detection rate of the built-in high-resistance contact (resistance monitor) and the threshold value. In the drawing, the vertical axis indicates the detection rate (%) of the high-resistance contact expressed on a linear scale. The horizontal axis indicates a threshold value represented by a linear scale. The threshold value is high on the left side and low on the right side.

When the threshold is changed from the higher resistance to the lower resistance based on the resistance distribution of FIG. 4, the detection rate is low until the high resistance distribution B of FIG. Distribution B
, The detection rate starts to increase gradually, and the detection rate is saturated until it reaches the higher skirt of the low-resistance distribution A beyond the lower skirt. Therefore, by setting the threshold value in a region where the detection rate is saturated, the threshold value can be made as small as possible, and the probability that the contact is determined as a defect even though the contact has a normal resistance value is minimized. Can be. Specifically, in FIG. 5, when the correlation C is present, the ratio of detecting a built-in high-resistance contact when the threshold value is high is about 5%, but the detection rate decreases as the threshold value is lowered. The detection rate becomes 50% at the threshold value Th1, and the detection rate is saturated at a lower threshold value. Considering that the resistance value of the built-in high resistance contact is distributed around 1 MΩ,
By setting the threshold value at a point substantially at the center Th2 of the saturation region, a high-resistance contact having a resistance value of about 1 MΩ can be detected, and the false defect detection rate can be suppressed.

When the inspection conditions are shifted in the inspection wafer surface, when there is a difference in the surface state of the inspection wafer, or when the inspection wafer is replaced, the threshold value and the detected resistance value are used. May deviate, for example, like the correlation D. In this case, in the conventional method, the shift cannot be recognized by the inspector, and the threshold may be set before the detection rate reaches the saturation region. However, according to the method of this embodiment, the shift of the threshold is reflected in the detection rate of the built-in high-resistance contact, and in the case of FIG. 5, the detection rate increases as a whole. Since the threshold can be reset in the saturation region of the detection rate, for example, Th3, there is an advantage that the reliability of the inspection is improved. Also,
From the relationship between the threshold value and the detection rate, and the resistance distribution of the built-in high-resistance contact, the threshold value can be set and the resistance value that can be detected at that threshold value can be estimated. By doing so, a distribution of the resistance value of the high-resistance contact can be obtained.

Second Embodiment FIG. 6 is a sectional view showing a method for manufacturing a semiconductor device having a contact array according to a second embodiment of the present invention. FIG. 6 shows that the contact array of this embodiment is significantly different from the contact array of the first embodiment.
As shown in (c), a resistance monitor 51a having a set of contacts having three types of contact areas is periodically arranged. As shown in FIG. 6 (a), a contact array forming method of this embodiment first forms an oxide film for preventing contamination (not shown) on an N-type semiconductor substrate 31 to a thickness of about 5 nm and then applies As to an accelerating voltage. At a dose of about 5 × 10 ¹⁵ atoms / cm ² at 30 keV, a high concentration N-type impurity is introduced into the semiconductor substrate 31.

Next, an oxide film having a thickness of about 100 nm and a BPSG film having a thickness of about 400 nm are sequentially deposited by normal pressure CVD to form an interlayer insulating film 33. Subsequently, heat treatment is performed in a nitrogen atmosphere at a temperature of about 850 ° C. to activate the ion-implanted impurities. Thus, an N ⁺ -type high-concentration diffusion region 32 doped with a high-concentration N-type impurity is formed. Next, a resist film (not shown) is formed on the interlayer insulating film 33, and three types of openings each having a maximum diameter of about 0.3 μm and a diameter slightly smaller than this are formed as one set. To form a resist film periodically. Next, the interlayer insulating film 33 is plasma-etched through the opening of the resist film, and a plurality of resistance monitors having a set of contact holes 34a to 34c having three kinds of diameters are formed periodically. Then, FIG.
As shown in (b), after depositing an oxide film having a thickness of 100 to 200 nm, etching is performed by a plasma etching method to form a sidewall of the oxide film on the side wall in the contact hole. Note that in order to reduce the contact resistance, phosphorus may be ion-implanted into the diffusion region 32 of the semiconductor substrate after forming the sidewall on the side wall of the contact hole. Next, after removing the oxide film on the back surface,
A polycrystalline silicon film or an amorphous silicon film (hereinafter, referred to as polycrystalline silicon or the like) 3 having a thickness of about 10 to 50 nm;
5, and an amorphous silicon film 36 containing phosphorus having a thickness of about 700 nm is further deposited. At this time, as the diameter of the contact holes 34a to 34c becomes smaller, the amorphous silicon film 36 containing phosphorus which is deposited later becomes less buried in the contact holes 34b and 34c, and the polycrystalline silicon film which does not contain phosphorus which is deposited earlier The ratio of 35 etc. increases. In some cases, phosphorus may be ion-implanted into the lower polycrystalline silicon film 35 to reduce the resistance of the lower polycrystalline silicon film 35.

Next, the upper amorphous silicon film 36 and the lower polycrystalline silicon film 35 are etched back in order by plasma etching to form contact holes 34a.
The silicon film is left only in the area 34c. Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of about 850 ° C. to activate the amorphous silicon film to form poly plugs 39a to 39c in the contact holes 34a to 34c. At this time, as the diameter of the contact holes 34a to 34c becomes smaller, the proportion of the polycrystalline silicon film 35 not containing phosphorus in the contact holes 34a to 34c increases, so that the contact resistance depends on the diameter of the contact holes 34a to 34c. Can be adjusted. Next, a two-layer film of a titanium film / titanium nitride film, an aluminum copper alloy film, and a titanium nitride film as an antireflection film are sequentially deposited by a sputtering method. Subsequently, after forming a resist film (not shown) and patterning to form a resist mask, FIG.
As shown in (c), the titanium nitride film, the aluminum copper alloy film, and the two-layer film of the titanium film / titanium nitride film are sequentially etched by the plasma etching method according to the resist mask, and the wiring / electrode 37a is formed on the poly plugs 39a to 39c.
To 37c. During this step, a polycrystalline silicon 38 containing phosphorus is formed on the back surface of the silicon substrate 31.

Thereafter, when the contact resistance is reduced by heat treatment at a temperature of about 400 ° C. in a hydrogen atmosphere, a test wafer is completed. At this time, the contact array is formed by forming a plurality of resistance monitors 51a having a set of contacts of three types of contact holes 34a to 34c with a pattern having a diameter of about 0.3 μm as a maximum. In the second embodiment, in a normal contact, as shown in FIG. 6B, a high-resistance polycrystalline silicon film or the like 35 and a low-resistance amorphous silicon film are formed in contact holes 34a to 34c. 36, the contact resistance is reduced, but the diameter of the contact holes 34a to 34c is gradually reduced, so that the etching rate of the interlayer insulating film 33 in the contact region gradually increases due to the microloading effect of plasma etching. Therefore, the smaller the diameter of each of the contact holes 34a to 34c, the smaller the depth of the contact holes 34a to 34c, and the lower the resistance of the amorphous silicon film 36 in the contact holes 34a to 34c. Together with the increase in the proportion of high-resistance polycrystalline silicon film 35 etc. In such reason, the contact resistance is very high,
The variation increases.

Next, the resistance value of the fabricated high-resistance contact is measured. Unlike the measurement method for detecting secondary electrons according to the first embodiment, the resistance of a contact arranged in an actual inspection area is directly measured using a current detection type AFM. FIG. 7 shows the measuring method. As shown in FIG. 7, the back surface of the silicon substrate 31 is connected to the ground. A polycrystalline silicon film 38 containing phosphorus is formed on the back surface of the silicon substrate 1, and an ohmic contact is taken from a stage with which the back surface contacts, and is connected to the ground with low resistance.
For the probe 40, a tungsten needle having a tip with a curvature of 500 nm or more and larger than usual is used. Further, it is preferable to use a beam 41 supporting the probe 40 having a higher spring constant than a beam that is normally used. In FIG. 7, the same reference numerals are given to the units corresponding to the components in FIG. 6, and the description will be omitted.

The contact resistance is measured as follows. That is, a voltage of about several volts is applied to the probe 40, and the contact array is scanned to scan the probe 40 and the wiring / electrode 37.
The contact resistance is calculated by measuring the current flowing between a to 37c. Since the position of the built-in high-resistance contact is set in advance, by measuring the vicinity of the region, the resistance values of many high-resistance contacts can be obtained, and the contact position and the resistance value can be known in advance. . Regarding the setting of the threshold value, when the resistance value of the high-resistance contact is set to, for example, 5 MΩ, the detection rate of the contact having the resistance value of about 5 MΩ increases, and the threshold value is set so that the detection rate is saturated. Thus, a highly reliable high-resistance contact can be detected similarly to the first embodiment.
Further, the resistance measuring circuit of this embodiment has an advantage that the contact resistance can be measured without forming a contact chain. In addition, the threshold value is set in advance in several stages, and the contact resistance detected at each level of the threshold value after the inspection is measured, thereby obtaining the relationship between the threshold value and the detected resistance value, The resistance distribution can be obtained based on this. This method requires a considerable amount of time to directly measure the resistance value of the high-resistance contact, but it is not necessary to measure the resistance value of the high-resistance contact in advance. Not necessary.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like within the scope of the present invention. Even this is included in the present invention. For example, in the above-described embodiment, a method of reducing the impurity concentration of the diffusion region or a method of reducing the contact area is used as a method of forming the formed high-resistance contact. However, the present invention is not limited thereto. A method of reducing the concentration of impurities introduced into the contact plug may be used. Although the contacts in the contact array are isolated from each other, FIG.
Alternatively, the contacts may be connected in series as shown in FIG.

[0046]

As described above, according to the structure of the present invention, a resistance monitor composed of a high-resistance contact is formed in a contact array in advance and the resistance value of the resistance monitor is estimated or estimated. By actually measuring, SE
When a defect is inspected by a defect inspection apparatus using M or by visual inspection using an SEM, the released 2
An inspection reference value can be set by associating the amount of secondary electrons with an actual measured value or an estimated value of the contact resistance in the contact array.

Further, the inspection reference value of the amount of secondary electrons to be emitted is set arbitrarily, contacts corresponding to each inspection reference value are detected, and the contact resistance of the contact detected by each inspection reference value is actually measured. Thus, the inspection reference value can be set from the relationship between each inspection reference value and the corresponding contact resistance value. As a result, it is possible to clarify how much the contact resistance value corresponds to the inspection reference value, so that the distribution of the contact resistance and the like can be acquired with high accuracy, and the detection of the pseudo defect and the oversight of the defect can be prevented. The reliability of the defect inspection can be improved.

[Brief description of the drawings]

FIG. 1 is a top view schematically showing a configuration of an inspection wafer according to a first embodiment of the present invention.

FIG. 2A is a top view showing a configuration of a contact resistance measurement circuit formed in a peripheral portion of a contact formation region of the inspection wafer, and FIG. 2B is a view along line III-III in FIG. It is sectional drawing.

FIG. 3 is a sectional view taken along the line II-II of FIG. 1 showing the method for manufacturing the contact array of the inspection wafer.

FIG. 4 is a graph showing a result of measuring a contact resistance using the contact resistance measuring circuit.

FIG. 5 is a graph showing a result obtained by performing an inspection by changing a threshold value using the contact resistance measurement circuit and acquiring a relationship between a detection rate of the resistance monitor and the threshold value.

FIG. 6 is a sectional view showing a method for manufacturing a contact array of an inspection wafer according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method for measuring a contact resistance.

FIG. 8A is a cross-sectional view showing a configuration of a conventional contact array of an inspection wafer, and FIG. 8B is a top view showing the same arrangement.

9A is a cross-sectional view showing a conventional method for inspecting a defect of a contact array of an inspection wafer, and FIG. 9B is a top view showing the same arrangement.

FIG. 10A is a top view showing a conventional method for inspecting a defect of a contact array of another inspection wafer, and FIG.
FIG. 2 is a cross-sectional view taken along line II of FIG.

[Explanation of symbols]

21, 31 Semiconductor substrate 22 P well region 24a, 24b, 24d, 32 High concentration diffusion region 24c, 24e Low concentration diffusion region 26, 33 Interlayer insulating film 27a-27c, 34a-34c Contact hole 28a, 28b, 28d Plug (low 28c, 28e Plug (high resistance contact plug) 29a-29c, 37a-37c Wiring / electrode 30a, 30b Pad 39a-39c Poly plug 40 Probe 41 Beam 51, 51a Resistance monitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M106 AA01 AB20 BA01 BA03 BA14 CA04 CA08 CA15 CA38 DB05 DH09 DH24 5F033 HH09 HH33 JJ18 JJ19 JJ33 KK01 PP15 QQ09 QQ10 QQ12 QQ31 QQ37 QQ58 QQ65 QQ73 QQ74XX15 SS15

Claims (12)

[Claims] 1. A semiconductor device having a contact array in which a plurality of contacts formed by contacting an impurity region of a semiconductor layer and a conductive layer are arranged, wherein a contact having a higher resistance than other contacts is arranged in the contact array. Wherein at least one resistance monitor is provided in advance and positioned. 2. The semiconductor device according to claim 1, wherein an impurity concentration of said impurity region in said resistance monitor is lower than an impurity concentration of an impurity region in a contact surrounding said resistance monitor. 3. A contact area between the impurity region and the conductive layer in the resistance monitor is smaller than a contact area between the impurity region and the conductive layer in a contact around the resistance monitor. The semiconductor device according to claim 1. 4. The resistance monitor according to claim 3, wherein said resistance monitor comprises a plurality of types of resistance monitors having different contact areas.
13. The semiconductor device according to claim 1. 5. The resistance of the conductive layer in the resistance monitor is higher than the resistance of the conductive layer in a contact surrounding the resistance monitor.
13. The semiconductor device according to claim 1. 6. The resistance measuring circuit according to claim 1, wherein a resistance measuring circuit is formed in a region different from a region where the contact array is formed by the same method as the method of forming the high resistance contact. 3. The semiconductor device according to claim 1. 7. A contact resistance inspection method for a semiconductor device for detecting a contact having a higher resistance than other contacts in a contact array in which a plurality of contacts formed by contacting an impurity region of a semiconductor layer and a conductive layer are arranged. In the contact array, at least one resistance monitor composed of a contact having a higher resistance than other contacts is provided in advance and provided, and an inspection reference value for determining that the resistance monitor is defective is set. And a contact resistance inspection method for a semiconductor device. 8. Directly measuring the resistance value of the resistance monitor,
8. The method according to claim 7, wherein the inspection reference value is set based on the value. 9. A resistance measurement circuit is created in a region different from the contact array formation region by the same creation method as the resistance monitor, and the resistance of the high resistance contact in the resistance measurement circuit corresponding to the resistance monitor is created. 8. The contact resistance test for a semiconductor device according to claim 7, wherein a resistance value of a resistance monitor in the contact array is estimated by measuring the value, and the inspection reference value is set based on the value. Method. 10. The inspection which is arbitrarily set by arbitrarily changing the inspection reference value and classifying the contacts for each of the inspection reference values, and then measuring a resistance value of a contact within each of the inspection reference values. 8. The method according to claim 7, wherein a relationship between a reference value and a resistance value of the contact corresponding to the reference value is determined, and the inspection reference value is set based on the relationship. 11. The method according to claim 7, wherein the contact resistance is compared by irradiating the charged particles and comparing the amount of secondary electrons emitted from the irradiated area. 7. A method for testing contact resistance of a semiconductor device according to claim 1. 12. The semiconductor according to claim 7, wherein the contact resistance is compared by irradiating the charged particles and comparing the amount of current absorbed in the semiconductor substrate. Inspection method for contact resistance of equipment.