JP2000232121A - Method for forming bump electrode of semiconductor device - Google Patents
Method for forming bump electrode of semiconductor deviceInfo
- Publication number
- JP2000232121A JP2000232121A JP11032944A JP3294499A JP2000232121A JP 2000232121 A JP2000232121 A JP 2000232121A JP 11032944 A JP11032944 A JP 11032944A JP 3294499 A JP3294499 A JP 3294499A JP 2000232121 A JP2000232121 A JP 2000232121A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- bump
- electrode
- semiconductor device
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置のバン
プ電極形成方法に関する。The present invention relates to a method for forming a bump electrode of a semiconductor device.
【０００２】[0002]
【従来の技術】従来からの公知の技術として、半導体装
置を裸のまま下向き（フェイスダウン）にて、加熱加圧
し回路基板のパターン上に接続する、フリップチップ実
装構造が提案されている。この実装方法での従来技術を
ガラスエポキシ基板への実装を例に、工程順に従い図３
を用いて説明する。2. Description of the Related Art As a conventionally known technique, a flip-chip mounting structure has been proposed in which a semiconductor device is heated and pressed downward (face down) while being naked and connected to a pattern on a circuit board. The conventional technique in this mounting method is shown in FIG.
This will be described with reference to FIG.
【０００３】図３（ａ）はフリップチップ実装する直前
の状態を示す断面図である。図３（ａ）において半導体
装置であるところのベアチップＩＣ１が実装される回路
基板２の部品実装面３には複数の配線パターンが導電材
料にて形成されており、各配線パターンの先端の表面に
は、金メッキがなされた電極５が形成されている。ま
た、各配線パターンは、電極５の部分を除いてソルダー
レジスト６で覆われている。ここで回路基板２は、配線
パターンを複数の層に配置した、ガラスエポキシよりな
る多層基板である。配線パターンの下の絶縁層１０を介
して２層目の配線パターン１１が設けられ、さらにその
下にも絶縁層１０を介し３層目の配線パターン１２が設
けられている。FIG. 3A is a sectional view showing a state immediately before flip-chip mounting. In FIG. 3A, a plurality of wiring patterns are formed of a conductive material on a component mounting surface 3 of a circuit board 2 on which a bare chip IC 1 which is a semiconductor device is mounted. Has an electrode 5 plated with gold. Each wiring pattern is covered with a solder resist 6 except for a part of the electrode 5. Here, the circuit board 2 is a multilayer board made of glass epoxy in which wiring patterns are arranged in a plurality of layers. A second-layer wiring pattern 11 is provided via an insulating layer 10 below the wiring pattern, and a third-layer wiring pattern 12 is further provided thereunder via an insulating layer 10.
【０００４】ベアチップＩＣ1には、能動面７にアルミ
等の導電材料で形成された複数の電極が基板の電極に対
応させて配置され、各電極の表面にはバンプ８が形成さ
れている。バンプ８はＡｕやＳｎ−Ｐｂ合金等の金属材
料で形成されている。In the bare chip IC1, a plurality of electrodes formed of a conductive material such as aluminum are arranged on the active surface 7 in correspondence with the electrodes of the substrate, and bumps 8 are formed on the surface of each electrode. The bump 8 is formed of a metal material such as Au or Sn-Pb alloy.
【０００５】ベアチップＩＣ１の能動面を下向きにし
て、加熱・加圧ツール２３にてベアチップＩＣ１を吸着
する。その後、そのままの状態で加熱・加圧ツール２３
にてベアチップＩＣ１を加熱、加圧し回路基板２の電極
５の部分に押し付け実装する。The bare chip IC 1 is sucked by the heating / pressing tool 23 with the active surface of the bare chip IC 1 facing downward. Then, the heating / pressing tool 23 is left as it is.
Then, the bare chip IC1 is heated and pressurized, and pressed against the electrode 5 of the circuit board 2 for mounting.
【０００６】しかしながら前記のような半導体装置の実
装構造では、半導体装置を実装する導体パターンが形成
された回路基板が、液晶表示パネルのガラス基板のよう
な基板自身の表面平坦性の優れたものには問題はない
が、ガラスエポキシを基材とし、導体パターンが形成さ
れた回路基板に代表されるような、表面の平坦性が確保
できない基板に実装する場合は、バンプ８と電極５の接
合面で問題があった。However, in the above-described semiconductor device mounting structure, the circuit board on which the conductor pattern for mounting the semiconductor device is formed has a superior surface flatness such as a glass substrate of a liquid crystal display panel. Although there is no problem, when mounting on a substrate that cannot ensure the flatness of the surface, such as a circuit board having a conductive pattern formed on a glass epoxy base material, the bonding surface between the bump 8 and the electrode 5 There was a problem.
【０００７】図３（ｂ）は、ベアチップＩＣ1が回路基
板２の電極５に接触した直後の状態を示している。バン
プ８と電極５が、導通している部分と、していない部分
が存在している。FIG. 3B shows a state immediately after the bare chip IC1 comes into contact with the electrode 5 of the circuit board 2. There are portions where the bumps 8 and the electrodes 5 are conductive, and portions where they are not.
【０００８】その後さらに、半導体装置に加熱加圧を加
え、回路基板２への実装が終了した状態を図３（ｃ）に
示すが、ここで回路基板２の部品実装面３は、加熱加圧
により絶縁層１０が軟化し電極５が適度に沈み込んでい
る。この絶縁層の沈み込みが、回路基板２の部品実装面
３のうねりを吸収し電極５と配線パターン４の電気的導
通を確保している。つまり、絶縁層の加熱軟化特性が実
装性や電気的品質を大きく左右しているのである。FIG. 3C shows a state in which the semiconductor device is further heated and pressed to complete the mounting on the circuit board 2, wherein the component mounting surface 3 of the circuit board 2 is heated and pressed. As a result, the insulating layer 10 is softened and the electrode 5 sinks appropriately. The sinking of the insulating layer absorbs the undulation of the component mounting surface 3 of the circuit board 2 and secures electrical conduction between the electrode 5 and the wiring pattern 4. That is, the heat softening characteristic of the insulating layer greatly affects the mountability and the electrical quality.
【０００９】図３（ｄ）は絶縁層１０が硬すぎる場合の
実装後の断面図を示す。絶縁層が硬すぎると回路基板２
のうねりを吸収できずに回路基板２の部品実装面３の表
面のうねりの山の部分では、バンプ８と電極５の導通が
確保されるが（図面の矢印Ａ部）、うねりの谷の部分で
は導通できない状態（図面の矢印Ｂ部）となってしま
う。また、導通不良にはならないものの、回路基板２の
うねりの山の部分の、バンプ８からの局所的な圧力によ
り、ベアチップＩＣが破壊する恐れもある。FIG. 3D is a cross-sectional view after mounting when the insulating layer 10 is too hard. If the insulating layer is too hard, the circuit board 2
Although the undulation cannot be absorbed, conduction between the bumps 8 and the electrodes 5 is secured at the undulation peaks on the surface of the component mounting surface 3 of the circuit board 2 (arrow A in the drawing), but at the undulation valleys. In such a case, conduction cannot be achieved (arrow B in the drawing). In addition, although the conduction failure does not occur, the bare chip IC may be broken by local pressure from the bumps 8 at the undulation peaks of the circuit board 2.
【００１０】一方、絶縁層が軟らか過ぎる場合は、図３
（ｅ）に示す通り、加熱・加圧ツールからの荷重がバン
プ８を介し電極５を押し込み、沈み込みが大きくなり２
層目の配線パターン１１とショートしてしまう（図面の
矢印Ｃ部）。また、ベアチップＩＣ１の端部と配線パタ
ーンが接触するエッジショートの危険性もある。（図面
の矢印Ｄ部）つまり、絶縁層１０は適度に沈み込みバン
プ８と電極５の導通を確保しつつ、しかも２層目の配線
パターンとは絶縁性を保つ必要があった。On the other hand, if the insulating layer is too soft,
As shown in (e), the load from the heating / pressing tool pushes the electrode 5 through the bump 8 and the sinking becomes large.
A short circuit occurs with the wiring pattern 11 of the layer (arrow C in the drawing). In addition, there is a risk of edge short-circuiting where the end of the bare chip IC1 and the wiring pattern are in contact. That is, it is necessary that the insulating layer 10 sinks appropriately to ensure conduction between the bump 8 and the electrode 5 and that the insulating layer 10 be insulated from the wiring pattern of the second layer.
【００１１】[0011]
【発明が解決しようとする課題】上述した従来技術は、
絶縁層の特性により実装性が大きく左右されるという欠
点を有していた。つまり、実装時に加熱・加圧ツールよ
りベアチップＩＣのバンプを介して回路基板に加えられ
る荷重に対し、絶縁層が固い場合は、回路基板のうねり
を吸収できずに電極とバンプの導通不良の部分が発生し
てしまう。The prior art described above is
There is a disadvantage that the mountability is greatly affected by the characteristics of the insulating layer. In other words, if the insulating layer is hard against the load applied to the circuit board via the bumps of the bare chip IC from the heating / pressing tool at the time of mounting, the undulation of the circuit board cannot be absorbed, and the portion of the electrode and the bump that has poor conduction cannot be absorbed. Will occur.
【００１２】一方軟らかい場合は、回路基板の層間での
ショートやベアチップＩＣのエッジショートの危険性が
ある。絶縁層は適度に沈み込み、回路基板の部品実装面
のうねりを吸収しベアチップＩＣのバンプと、回路基板
の電極の電気的導通を確保しつつ２層目以降の配線パタ
ーンとの絶縁性を保つ必要があり、絶縁層に何を選定す
るかが非常に重要であった。On the other hand, if it is soft, there is a risk of short-circuit between layers of the circuit board and edge short-circuit of the bare chip IC. The insulating layer sinks in moderately, absorbs undulations on the component mounting surface of the circuit board, and maintains insulation between the bumps of the bare chip IC and the wiring patterns of the second and subsequent layers while ensuring electrical continuity between the electrodes of the circuit board. It was necessary, and what was selected for the insulating layer was very important.
【００１３】電子機器の多機能化に伴い、複数の半導体
装置を１枚の回路基板に高密度に実装されるマルチチッ
プモジュール（以下ＭＣＭという）の場合を考えると、
さらに大きな問題がある。あるベアチップＩＣに最適な
絶縁層を選択しても必ずしもサイズやバンプ数の異なる
他のベアチップＩＣに最適とは限らないからである。つ
まり従来技術では、ＭＣＭのすべてのベアチップの実装
性を満足する絶縁層を選択する事は困難であった。Considering the case of a multi-chip module (hereinafter referred to as an MCM) in which a plurality of semiconductor devices are mounted on a single circuit board at a high density as electronic devices become multifunctional,
There is an even bigger problem. This is because even if an insulating layer optimal for a certain bare chip IC is selected, it is not always optimal for another bare chip IC having a different size and a different number of bumps. That is, in the related art, it has been difficult to select an insulating layer that satisfies the mountability of all bare chips of the MCM.
【００１４】本発明は上記課題に鑑みてなされたもので
あり、その目的とするところは、回路基板にうねりがあ
ったとしても、安定した回路基板の電極と、ベアチップ
ＩＣのバンプとの電気的接続信頼性を確保できる実装構
造を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide an electric connection between a stable electrode of a circuit board and a bump of a bare chip IC even if the circuit board has undulation. An object of the present invention is to provide a mounting structure capable of securing connection reliability.
【００１５】[0015]
【課題を解決するための手段】以上のような問題を解決
するために、本発明の半導体装置のバンプ電極形成方法
は、半導体装置のバンプ電極に凹凸を設けることを特徴
とする。In order to solve the above-mentioned problems, a method for forming a bump electrode of a semiconductor device according to the present invention is characterized in that bump electrodes of the semiconductor device are provided with irregularities.
【００１６】請求項１に係る本発明の半導体装置のバン
プ電極形成方法は、半導体装置のバンプ形成工程におい
て、半導体装置のアルミ電極パット上にバンプ電極を形
成した後、前記バンプの電極を凹凸形状に整形する事を
特徴とする。According to a first aspect of the present invention, there is provided a method for forming a bump electrode of a semiconductor device, comprising: forming a bump electrode on an aluminum electrode pad of the semiconductor device in the bump forming step of the semiconductor device; It is characterized by shaping into.
【００１７】また、請求項２に係る本発明の半導体装置
のバンプ電極形成方法は、バンプ電極が金からなること
を特徴とする。According to a second aspect of the present invention, there is provided a bump electrode forming method for a semiconductor device, wherein the bump electrode is made of gold.
【００１８】また、請求項３に係る本発明の半導体装置
のバンプ電極形成方法は、バンプ電極がメッキ法により
形成されたことを特徴とする。According to a third aspect of the present invention, there is provided a bump electrode forming method for a semiconductor device, wherein the bump electrode is formed by a plating method.
【００１９】また、請求項４に係る本発明の半導体装置
のバンプ電極形成方法は、バンプ電極がボールボンディ
ング法により形成されたことを特徴とする。According to a fourth aspect of the present invention, there is provided a bump electrode forming method for a semiconductor device, wherein the bump electrode is formed by a ball bonding method.
【００２０】また、請求項５に係る本発明の半導体装置
のバンプ電極形成方法は、バンプ電極が転写バンプ法に
より形成されたことを特徴とする、請求項１記載の半導
体装置のバンプ電極形成方法。According to a fifth aspect of the present invention, in the method of forming a bump electrode of a semiconductor device according to the present invention, the bump electrode is formed by a transfer bump method. .
【００２１】[0021]
【発明の実施の形態】（１） 第１実施形態 以下図面により、本発明の実施形態を詳述する。DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
【００２２】図１（ａ）〜（ｃ）は、本発明の実施形態
を実装の工程順に示した断面図である。本実施形態は、
異方性導電膜を用いたガラスエポキシ基板へのフリップ
チップ実装を例に説明する。FIGS. 1A to 1C are sectional views showing an embodiment of the present invention in the order of mounting steps. In this embodiment,
An example of flip-chip mounting on a glass epoxy substrate using an anisotropic conductive film will be described.
【００２３】まず図１（ａ）において、メッキ法により
バンプ８を形成したベアチップＩＣ１をステージ２１の
上に能動面７を上にした状態で搭載する。ここでツール
２２はバンプを一括加重して、バンプ上面に凹凸を整形
する加圧ツールである。この加圧ツールの表面には細か
な凹凸が設けられている。この加圧ツール２２を下げる
ことによりバンプ８の上面に凹凸９を整形する。ここ
で、凹凸の段差は、異方性導電膜に分散されている、導
電粒子径φ５μｍと同じく、５μｍ程度が望ましい。First, in FIG. 1A, a bare chip IC 1 on which bumps 8 are formed by a plating method is mounted on a stage 21 with an active surface 7 facing up. Here, the tool 22 is a pressure tool that weights the bumps at once and shapes the bumps on the bumps. Fine irregularities are provided on the surface of the pressing tool. By lowering the pressing tool 22, the unevenness 9 is formed on the upper surface of the bump 8. Here, the step of the unevenness is desirably about 5 μm, like the conductive particle diameter φ5 μm dispersed in the anisotropic conductive film.
【００２４】次に図１（ｂ）は、ベアチップＩＣ１を実
装する直前の状態を示す。図１（ｂ）において、前工程
でバンプ８の表面に凹凸９をつけたベアチップＩＣ１の
能動面７を下にしたフェイスダウン状態にして、加熱・
加圧ツール２３に吸着する。ここで回路基板２は部品実
装面以外にも配線パターンを有する多層基板である。回
路基板２はガラスエポキシを基材としているので部品実
装面３には、うねり、反りがある。１０は絶縁層を示
す。回路基板２の部品実装面３には既に異方性導電膜２
４が仮圧着されている状態を示す。ここで、異方性導電
膜とは、絶縁性樹脂２５に導電粒子２６が均一分散され
て形成されており、この導電粒子２６がバンプ８と電極
５の間に介在し電気的導通を確保するのである。FIG. 1B shows a state immediately before the bare chip IC 1 is mounted. In FIG. 1 (b), the bare chip IC 1 in which the bumps 8 are provided with irregularities 9 in the previous step is placed in a face-down state with the active surface 7 facing down.
It is adsorbed on the pressure tool 23. Here, the circuit board 2 is a multilayer board having a wiring pattern other than the component mounting surface. Since the circuit board 2 is made of glass epoxy, the component mounting surface 3 has undulation and warpage. Reference numeral 10 denotes an insulating layer. The component mounting surface 3 of the circuit board 2 already has an anisotropic conductive film 2
4 shows a state of being temporarily crimped. Here, the anisotropic conductive film is formed by uniformly dispersing the conductive particles 26 in the insulating resin 25, and the conductive particles 26 are interposed between the bumps 8 and the electrodes 5 to secure electrical conduction. It is.
【００２５】次に、ベアチップＩＣ1の能動面７が異方
性導電膜２４に向くように設定して異方性導電膜２４上
にベアＩＣチップ１を載せ、ベアチップＩＣ1を介し異
方性導電膜２４を加圧加熱（１８０度Ｃ、２０秒程度）
してベアチップＩＣ1の実装を行う。加熱することによ
り、異方性導電膜２４の絶縁性樹脂２５が軟化し、加圧
することにより押し広げられ、ベアチップＩＣ1の能動
面７と回路基板２の部品実装面３の間を充填する。ま
た、余った絶縁性樹脂２５は、押し出され、ベアチップ
ＩＣ1の側面を充填し保護する。Next, the active surface 7 of the bare chip IC1 is set so as to face the anisotropic conductive film 24, and the bare IC chip 1 is mounted on the anisotropic conductive film 24. 24 is heated under pressure (180 ° C, about 20 seconds)
Then, the bare chip IC1 is mounted. By heating, the insulating resin 25 of the anisotropic conductive film 24 is softened, and is spread out by applying pressure to fill the space between the active surface 7 of the bare chip IC 1 and the component mounting surface 3 of the circuit board 2. The surplus insulating resin 25 is extruded and fills and protects the side surface of the bare chip IC1.
【００２６】図１（ｃ）は半導体装置の実装を終了した
状態を示す断面図である。回路基板２の部品実装面３と
ベアチップＩＣ1の能動面７側とは、異方性導電膜２４
の絶縁性樹脂２６を介して接合される。また、異方性導
電膜２４に混在する導電粒子２６はバンプ８により回路
基板２の電極５に押圧されるので回路基板２とベアチッ
プＩＣ1とは電気的にも接続される。FIG. 1C is a sectional view showing a state where the mounting of the semiconductor device has been completed. The component mounting surface 3 of the circuit board 2 and the active surface 7 side of the bare chip IC1 are in contact with the anisotropic conductive film 24.
Are bonded via the insulating resin 26. In addition, the conductive particles 26 mixed in the anisotropic conductive film 24 are pressed against the electrodes 5 of the circuit board 2 by the bumps 8, so that the circuit board 2 and the bare chip IC1 are also electrically connected.
【００２７】ここで、バンプ８の表面に整形された凹凸
は電極５に押圧されるが、回路基板のうねりの山の部分
では、バンプ８の凹凸部は大きく塑性変形し、一方うね
りの谷の部分ではバンプ８の塑性変形は少ない。回路基
板２のうねりをバンプ８で吸収するので回路基板２の部
品実装面の電極５と２層目の配線パターン１１及び３層
目の配線パターン１２の間隔は変らず層間の配線パター
ンのショートは発生しない。Here, the irregularities formed on the surface of the bump 8 are pressed by the electrode 5, but the irregularities of the bump 8 are largely plastically deformed at the undulation peaks of the circuit board, while the undulation valleys are formed. In portions, the plastic deformation of the bump 8 is small. Since the undulations of the circuit board 2 are absorbed by the bumps 8, the distance between the electrode 5 on the component mounting surface of the circuit board 2 and the wiring patterns 11 and 12 of the second layer does not change, and short-circuiting of the wiring patterns between the layers does not occur. Does not occur.
【００２８】つまり、ベアチップＩＣのバンプ８に凹凸
９を設ける事により、絶縁層１０の特性によらず安定し
た実装構造が実現できる。That is, by providing the bumps 8 of the bare chip IC with the irregularities 9, a stable mounting structure can be realized regardless of the characteristics of the insulating layer 10.
【００２９】尚、本実施形態は、ベアチップＩＣのバン
プはメッキ法により形成されたものを例に詳述したが、
ボールボンディング法、転写バンプ法いずれの方法で形
成されたバンプにも適用可能なことはいうまでもない。In the present embodiment, the bumps of the bare chip IC have been described in detail by way of example formed by plating.
It goes without saying that the present invention can be applied to bumps formed by either the ball bonding method or the transfer bump method.
【００３０】（２） 第２実施形態 本実施形態は、第１実施形態の変形例である。第１実施
形態では、表面に凹凸のある加圧ツールにて一括してベ
アチップＩＣのバンプ上面に凹凸を整形したのに対し、
本変形例はより大きな凹形状を整形し、より大きなうね
り、反りを有する回路基板にも対応できるバンプ形成方
法を述べる。(2) Second Embodiment This embodiment is a modification of the first embodiment. In the first embodiment, the bumps of the bare chip IC are collectively shaped with bumps on the upper surface using a pressure tool having bumps on the surface.
This modification describes a bump forming method that shapes a larger concave shape and can cope with a circuit board having a larger undulation and warpage.
【００３１】フリップチップ実装工法において、シング
ルポイントボンディングＴＡＢ方式が実用化されてい
る。例えば、工業調査会 １９９４年２月１０日発行の
ハイブリッドマイクロエレクトロニクス協会編 「エレ
クトロニクス実装技術 基礎講座 第１巻 総論」に記
載があるが、図２（ａ）に示す通り、ベアチップＩＣ１
のバンプと回路基板よりでているリード３０を、１本づ
つボンディングツール３２にて、荷重と超音波を加えな
がら実装していく方式である。In the flip chip mounting method, a single point bonding TAB method has been put to practical use. For example, as described in the Hybrid Microelectronics Association, published by the Industrial Research Council on February 10, 1994, "Electronic Packaging Technology Fundamental Course, Vol. 1, General", as shown in FIG.
In this method, the bumps and the leads 30 formed from the circuit board are mounted one by one by a bonding tool 32 while applying a load and ultrasonic waves.
【００３２】本実施形態では、このシングルポイントボ
ンディングＴＡＢ方式の設備を用い、ベアチップＩＣの
バンプに凹形状を整形する。In the present embodiment, a concave shape is formed in the bump of the bare chip IC using the equipment of the single point bonding TAB method.
【００３３】図２（ｂ）において、加熱台３１に載せた
ベアチップＩＣ１のバンプ８に、ボンディングツール３
２より荷重と超音波を加え、図２（ｃ）に示すようなバ
ンプ中央部が凹となる形状を整形する。第１実施形態で
述べた凹凸の形成方法は、一括荷重による方法のため、
整形するバンプ数が多い場合は総荷重の高い大がかりな
設備が必要となる。一方、本実施形態の方法は、バンプ
ごとに凹形状を形成するため、より大きな凹凸を整形で
き、しかも低荷重であるため、ベアチップＩＣにより少
ないダメージで形成できる。そして、より大きな凹形状
を整形してあるため、、より大きなうねり、反りを有す
る回路基板にも対応できる。In FIG. 2B, the bonding tool 3 is attached to the bump 8 of the bare chip IC 1 placed on the heating table 31.
A load and an ultrasonic wave are applied from Step 2 to shape the concave portion of the bump as shown in FIG. Since the method of forming unevenness described in the first embodiment is a method using a collective load,
If the number of bumps to be shaped is large, large-scale equipment with a high total load is required. On the other hand, in the method of the present embodiment, since a concave shape is formed for each bump, larger irregularities can be shaped, and since the load is low, the bare chip IC can be formed with less damage. Since the larger concave shape is shaped, it is possible to cope with a circuit board having larger undulation and warpage.
【００３４】[0034]
【発明の効果】以上のように、本発明の半導体装置のバ
ンプ電極形成方法によれば、回路基板のうねりを絶縁層
で吸収するのではなく、ベアチップＩＣのバンプに整形
した凹凸を塑性変形させることにより吸収させる為、安
定した実装品質を実現し、信頼性の高い半導体装置の実
装構造を提供でき、極めて実現性が高い物である。As described above, according to the bump electrode forming method of the semiconductor device of the present invention, the undulation of the circuit board is not absorbed by the insulating layer, but the bumps of the bare chip IC are plastically deformed. As a result, stable mounting quality can be achieved, and a highly reliable semiconductor device mounting structure can be provided.
【図１】本発明の第１実施形態を示す実装構造の断面図
を示す。FIG. 1 is a sectional view of a mounting structure according to a first embodiment of the present invention.
【図２】本発明の第２実施形態を示す実装構造の断面図
を示す。FIG. 2 is a sectional view of a mounting structure according to a second embodiment of the present invention.
【図３】従来技術の実装構造の断面図を示す。FIG. 3 shows a cross-sectional view of a conventional mounting structure.
１…ベアチップＩＣ ２…回路基板 ３…部品実装面 ５…電極 ６…ソルダーレジスト ７…能動面 ８…バンプ ９…凹凸 １０…絶縁層 １１…２層目の配線パターン １２…３層目の配線パターン ２１…ステージ ２２…加圧ツール ２３…加熱・加圧ツール ２４…異方性導電膜 ２５…絶縁性樹脂 ２６…導電粒子 ３０…リード ３１…加熱台 ３２…ボンディングツール DESCRIPTION OF SYMBOLS 1 ... Bare chip IC 2 ... Circuit board 3 ... Component mounting surface 5 ... Electrode 6 ... Solder resist 7 ... Active surface 8 ... Bump 9 ... Unevenness 10 ... Insulating layer 11 ... Second layer wiring pattern 12 ... 3rd layer wiring pattern DESCRIPTION OF SYMBOLS 21 ... Stage 22 ... Pressure tool 23 ... Heating / pressure tool 24 ... Anisotropic conductive film 25 ... Insulating resin 26 ... Conductive particles 30 ... Lead 31 ... Heating table 32 ... Bonding tool
Claims (5)
導体装置のアルミ電極パット上にバンプ電極を形成した
後、前記バンプの電極を凹凸形状に整形する事を特徴と
する半導体装置のバンプ電極形成方法。1. A bump electrode forming method for a semiconductor device, comprising: forming a bump electrode on an aluminum electrode pad of the semiconductor device in a bump forming step of the semiconductor device, and then shaping the bump electrode into an uneven shape. .
る、請求項１記載の半導体装置のバンプ電極形成方法。2. The method according to claim 1, wherein the bump electrode is made of gold.
とを特徴とする、請求項１記載の半導体装置のバンプ電
極形成方法。3. The method according to claim 1, wherein the bump electrode is formed by a plating method.
形成されたことを特徴とする、請求項１記載の半導体装
置のバンプ電極形成方法。4. The method according to claim 1, wherein the bump electrodes are formed by a ball bonding method.
たことを特徴とする、請求項１記載の半導体装置のバン
プ電極形成方法。5. The method according to claim 1, wherein the bump electrode is formed by a transfer bump method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11032944A JP2000232121A (en) | 1999-02-10 | 1999-02-10 | Method for forming bump electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11032944A JP2000232121A (en) | 1999-02-10 | 1999-02-10 | Method for forming bump electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000232121A true JP2000232121A (en) | 2000-08-22 |
Family
ID=12373072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11032944A Pending JP2000232121A (en) | 1999-02-10 | 1999-02-10 | Method for forming bump electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000232121A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277733A (en) * | 2007-04-06 | 2008-11-13 | Hitachi Ltd | Semiconductor device |
-
1999
- 1999-02-10 JP JP11032944A patent/JP2000232121A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277733A (en) * | 2007-04-06 | 2008-11-13 | Hitachi Ltd | Semiconductor device |
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