JP2000232064A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a method for manufacturing a semiconductor integrated circuit which can prevent reduction in the mobility of an electron transit region. SOLUTION: An insulating layer 3 is formed on a semiconductor substrate 1, having a channel region, an opening 3a for a gate electrode, is made in the insulating layer 3 on the channel region, a protective layer 9 is formed on the insulating layer 3, a lower electrode 4 is formed on the protective layer 9, a capacitive element insulating layer 5 is formed on the lower electrode 4, an upper electrode 6 is formed on the capacitor element insulating layer 5, the protective layer 9 for the gate electrode opening 3a is removed, and a gate electrode 7 is formed in the opening 3a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a field effect transistor and a capacitor are integrated.

[0002]

2. Description of the Related Art First, a method of manufacturing a conventional semiconductor integrated circuit having a field effect transistor and a capacitor will be described with reference to FIG.

First, as shown in FIG. 5A, a very fine resist pattern 2 is formed on a semiconductor substrate 1 by a phase shift method. Next, after depositing an insulating layer 3 composed of a silicon oxide film on the semiconductor substrate 1, the resist pattern 2 is removed by a lift-off method. At this time, FIG.
As shown in (b), the insulating layer 3 has an opening 3a for a gate electrode of a field effect transistor.

[0004] Next, as shown in FIG.
The lower electrode 4 of the capacitor is formed on the upper part.

After that, as shown in FIG. 5D, a capacitive element insulating layer 5 made of strontium titanate (SrTiO ₃ : STO) is formed on the insulating layer 3 by RF sputtering using plasma. Capacitive element insulating layer 5
An upper electrode 6 is formed thereon.

Next, as shown in FIG. 5E, the capacitor element insulating layer 5 and the upper electrode 6 are formed into a predetermined shape by wet etching.

Finally, as shown in FIG. 5 (f), a gate electrode 7 is formed in the opening 3a and ohmic electrodes 8 are formed on both sides of the gate electrode 7. Thereafter, semiconductor integration is performed by a normal method. Complete the circuit.

[0008]

However, in the conventional method of manufacturing a semiconductor integrated circuit, plasma used for forming the capacitive element insulating layer 5 is directly applied to the surface of the semiconductor substrate 1 at the gate electrode opening 3a. To touch
A defect occurs in an electron traveling region existing on the surface of the semiconductor substrate 1. As a result, the mobility of the electron transit region, which was about 5500 cm ² / V · sec before the formation of the capacitive element insulating layer 5, is reduced to about 3200 cm ² / V · sec, and the operation of the field effect transistor The characteristics deteriorate.

[0009] Contrary to the conventional method of manufacturing a semiconductor integrated circuit shown here, if the capacitive element insulating layer 5 is formed before the gate electrode opening 3a is formed, the capacitive element insulating layer 5 can be formed. At times, since the electron traveling region is protected by the insulating layer 3, the problem that the mobility of the electron traveling region decreases does not occur. However, when the capacitor element insulating layer 5 is formed first, when forming the gate electrode opening 3a, as shown in FIG. 6, the capacitor is already completed, and the gate electrode opening 3a is formed. When the photoresist 11 for forming 3a is formed, the thickness of the photoresist 11 becomes non-uniform or the light 12 is irregularly reflected from the step at the time of exposure because the capacitive element has a step. This causes another problem that the diameter of the gate electrode opening 3a does not reach a desired value. This problem is particularly apparent when the gate electrode opening 3a is to be finely formed by using a phase shift method.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit which can prevent a decrease in the mobility of an electron transit area even if a capacitive element insulating layer 5 is formed after forming a gate electrode opening 3a. And

[0011]

According to a method of manufacturing a semiconductor integrated circuit of the present invention, an insulating layer is formed on a semiconductor substrate having a channel region, and a gate electrode opening is formed in the insulating layer on the channel region. Forming a protective layer on the insulating layer; forming a lower electrode on the protective layer; forming a capacitive element insulating layer on the lower electrode; Forming an upper electrode on the insulating layer; removing the protective layer in the gate electrode opening; and forming a gate electrode in the gate electrode opening.

According to the present invention, when the capacitor element insulating layer is formed, the electron traveling region is protected by the protective layer, so that a decrease in the mobility of the electron traveling region can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS.

Embodiment 1 Hereinafter, a method for manufacturing a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to FIG.

FIGS. 1A to 1G show a method of manufacturing a semiconductor integrated circuit according to the first embodiment of the present invention.

First, as shown in FIG.
A resist pattern 2 is formed by a phase shift method on a semiconductor substrate 1 having a channel region (not shown) formed by an epitaxial growth method. Next, after an insulating layer 3 made of silicon oxide is deposited on the semiconductor substrate 1 by an electron beam evaporation method, the resist pattern 2 is removed by a lift-off method. At this time, as shown in FIG. 1B, the opening 3a for the gate electrode of the field effect transistor is formed in the insulating layer 3. The resist may be of a negative type or a positive type.

Next, as shown in FIG.
A protective layer 9 made of Al is formed thereon.

Subsequently, as shown in FIG. 1D, the lower electrode 4 of the capacitive element having a Ti / Pt film (not shown) on the protective layer 9, and titanic acid deposited by RF sputtering using plasma. Strontium (SrTiO ₃ : STO)
Are sequentially formed, and the upper electrode 6 of the capacitor is formed. Here, when forming the capacitive element insulating layer 5, the channel region of the semiconductor substrate 1 is
Therefore, it is protected from damage of RF sputtering using plasma, and can maintain a favorable crystal state.

Next, using the ion milling method, FIG.
As shown in (e), the lower electrode 4, the capacitor element insulating layer 5, and the upper electrode 6 are formed into a predetermined shape.

Next, as shown in FIG. 1F, the protective layer 9 on the gate electrode opening 3a is removed with hydrochloric acid. Here, Al constituting the protective layer 9 is easily etched by hydrochloric acid, but silicon oxide constituting the insulating layer 3 is not etched at all by hydrochloric acid. Therefore, the gate electrode opening 3a can maintain a fine shape.

A method of using silicon nitride as the material of the protective layer 9 and removing the protective layer 9 by a dry etching method using CF ₄ gas may be adopted. In this case, the silicon nitride forming the protective layer 9 is easily etched by CF ₄ gas, but the silicon oxide forming the insulating layer 3 is
Etching is not easy even with F ₄ gas, and the etching rate is about 1/40 that of silicon nitride.

Therefore, even if etching is continued after the protective layer 9 on the gate electrode opening 3a is completely removed with hydrochloric acid (over-etching), the shape of the gate electrode opening 3a in the insulating layer 3 is maintained. Is almost maintained.

FIG. 2 is a diagram showing the relationship between the time of over-etching and the width of the gate electrode opening 3a. As can be seen from FIG. 2, if the over-etching time is within 2 minutes, the amount of increase in the width of the gate electrode opening 3a can be suppressed to within 10%, so that the problem of characteristic deterioration does not actually occur.

After the protective layer 9 is removed, as shown in FIG. 1G, a gate electrode 7 is formed in the gate electrode opening 3a, and ohmic electrodes 8 are formed on both sides of the gate electrode 7. Thereafter, the semiconductor integrated circuit is completed by a usual method.

In this embodiment, the protective layer 9
After the formation of the lower electrode 4 was formed on the protective layer 9, the lower electrode 4 was formed as shown in FIG.
Is formed first, and then the protective layer 9 is formed so as to cover the peripheral portion of the lower electrode 4, so that the protective layer 9 is sandwiched between the lower electrode 4 and the capacitive element insulating layer 5 at the peripheral portion of the lower electrode 4. It will be in the form. Accordingly, the end of the capacitive element insulating layer 5 that easily becomes a path of the leak current does not directly contact the lower electrode 4, and the leak current is reduced. If the protective layer 9 is made of silicon nitride having excellent insulating properties, the leak current can be reduced more effectively.

(Embodiment 2) Next, a method of manufacturing a semiconductor integrated circuit according to Embodiment 2 of the present invention will be described with reference to FIG.

FIGS. 4A to 4I show a method of manufacturing a semiconductor integrated circuit according to the second embodiment of the present invention.

First, as shown in FIG.
An insulating layer 3 made of silicon oxide is formed on a semiconductor substrate 1 having a channel region (not shown) formed by an epitaxial growth method, and a portion on the channel region on the insulating layer 3 and a capacitive element A resist pattern 2 is formed by a phase shift method on a region where is to be formed.

Next, after a mask layer 10 made of Al is deposited on the semiconductor substrate 1 by an electron beam evaporation method, the resist pattern 2 is removed by a lift-off method. At this time, as shown in FIG. 4B, a mask opening 10a is formed in the mask layer 10.

Next, as shown in FIG. 4C, a protective layer 9 made of a silicon nitride film is formed.

Subsequently, as shown in FIG. 4D, the lower electrode 4 of the capacitor having a Ti / Pt film (not shown) on the protective layer 9 and titanic acid deposited by RF sputtering using plasma. Strontium (SrTiO ₃ : STO)
Are sequentially formed, and the upper electrode 6 of the capacitor is formed. Here, when forming the capacitive element insulating layer 5, the channel region of the semiconductor substrate 1 is
Therefore, it is protected from damage of RF sputtering using plasma, and can maintain a favorable crystal state.

Next, using the ion milling method, FIG.
As shown in (e), the lower electrode capacitive element 4, the capacitive element insulating layer 5, and the upper electrode 6 are formed into a predetermined shape.

Next, as shown in FIG. 4F, a photoresist 11 is formed so as to cover the capacitive element, and a portion of the protective layer 9 not covered with the photoresist 11 is CF
Removed by dry etching using ₄ gases. Here, the mask layer 10 made of Al is hardly etched by dry etching using CF ₄ gas. At this time, although the insulating layer 3 is slightly etched, there is no particular problem in manufacturing.

Next, as shown in FIG. 4G, using the mask layer 10 as a mask, the insulating layer 3 is removed by dry etching using CHF ₃ gas, and the gate electrode opening 3a is formed in the insulating layer 3. Provide.

Next, as shown in FIG. 4H, the mask layer 10 and the photoresist 11 are removed.
As shown in (i), a gate electrode 7 is formed in the gate electrode opening 3a, and ohmic electrodes 8 are formed on both sides of the gate electrode 7. Thereafter, a semiconductor integrated circuit is completed by a usual method.

[0036]

As described above, according to the present invention, even when a capacitive element insulating layer having a high dielectric constant is formed by sputtering using plasma, the electron traveling region of the semiconductor substrate is protected by the insulating layer. Therefore, damage to the electron traveling region due to the plasma is reduced, and the electron mobility is maintained. Thus, an integrated circuit including a high-capacitance capacitive element and a high-speed transistor can be manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing the relationship between the time of over-etching and the width of a gate electrode opening;

FIG. 3 is a diagram showing a method of manufacturing another semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a method of manufacturing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional method of manufacturing a semiconductor integrated circuit.

FIG. 6 is a diagram showing another conventional method for manufacturing a semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 resist pattern 3 insulating layer 3a gate electrode opening 4 lower electrode 5 capacitive element insulating layer 6 upper electrode 7 gate electrode 8 ohmic electrode 9 protective layer 10 mask layer 10a mask opening 11 photoresist 12 light

Continuing on the front page (72) Inventor Katsuhiko Kawashima 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (10)

[Claims] A step of forming an insulating layer on a semiconductor substrate having a channel region; a step of forming a gate electrode opening in the insulating layer on the channel region; and forming a protective layer on the insulating layer. Performing a step of forming a lower electrode on the protective layer; forming a capacitive element insulating layer on the lower electrode; forming an upper electrode on the capacitive element insulating layer; A method of manufacturing a semiconductor integrated circuit, comprising: a step of removing the protective layer in a gate opening; and a step of forming a gate electrode in the gate electrode opening. 2. The method according to claim 1, wherein the gate electrode opening is formed by a phase shift method. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the insulating layer is formed of a silicon oxide film, and the protective layer is formed of a silicon nitride film. 4. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the insulating layer is formed of a silicon nitride film, and the protective layer is formed of a silicon oxide film. 5. The semiconductor device according to claim 1, wherein the insulating layer is made of a silicon oxide film or a silicon nitride film, and the protective layer contains one of aluminum, titanium, gold, and tungsten. The manufacturing method of the semiconductor integrated circuit described in the above. 6. A step of forming an insulating layer on a semiconductor substrate having a channel region, a step of forming a mask layer having a mask opening on the channel region on the insulating layer, A step of forming a protective layer, a step of forming a lower electrode on the protective layer, a step of forming a capacitive element insulating layer on the lower electrode, and a step of forming an upper electrode on the capacitive element insulating layer Removing the protective layer from the opening, forming a gate electrode opening in the insulating layer over the channel region, and forming a gate electrode in the gate electrode opening. A method for manufacturing a semiconductor integrated circuit, comprising: 7. The method according to claim 6, wherein the mask opening is formed by a phase shift method. 8. The semiconductor integrated circuit according to claim 6, wherein the insulating layer is made of a silicon oxide film or a silicon nitride film, and the mask layer contains one of aluminum and gold. Circuit manufacturing method. 9. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein said capacitive element insulating layer contains an oxide of titanium. 10. A step of forming an insulating layer on a semiconductor substrate having a channel region, a step of forming a gate electrode opening in the insulating layer on the channel region, and forming a lower electrode on the insulating layer Forming a protective layer on the gate electrode opening and on the peripheral edge of the lower electrode; forming a capacitive element insulating layer on the lower electrode; and forming a protective layer on the capacitive element insulating layer. Manufacturing a semiconductor integrated circuit, comprising: a step of forming an upper electrode; a step of removing the protective layer in the gate electrode opening; and a step of forming a gate electrode in the gate electrode opening. Method.