JP2000231487A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2000231487A5 JP2000231487A5 JP1999031693A JP3169399A JP2000231487A5 JP 2000231487 A5 JP2000231487 A5 JP 2000231487A5 JP 1999031693 A JP1999031693 A JP 1999031693A JP 3169399 A JP3169399 A JP 3169399A JP 2000231487 A5 JP2000231487 A5 JP 2000231487A5
- Authority
- JP
- Japan
- Prior art keywords
- clk
- flip
- divides
- series
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Description
分周回路１１は、典型的には、直列接続された複数のフリップフロップから構成されており、外部から入力される外部クロックＥ＿Ｃｌｋを分周して、互いに異なる周波数を有する複数の内部クロックＩ＿Ｃｌｋを同時に作り出して出力する。本実施形態では、図２のように、分周回路１１は、直列接続された２個のフリップフロップ１３および１４を含んでおり、これによって、周波数ｆ1 〜ｆ3 を有する３個の内部クロックＩ＿Ｃｌｋ1 〜Ｉ＿Ｃｌｋ3 が同時に生成される。また、図２の構成では、周波数ｆ1 〜ｆ3 の間には、ｆ2 ＝ｆ1 ／２、およびｆ3 ＝ｆ1 ／４の関係が成り立つ。 The frequency dividing circuit 11 is typically composed of a plurality of flip-flops connected in series, divides an external clock E_Clk input from the outside, and divides a plurality of internal clocks I_Clk having different frequencies from each other. Create and output at the same time. In this embodiment, as shown in FIG. 2, the frequency divider circuit 11 includes two flip-flops 13 and 14 connected in series, whereby three internal clocks having frequencies f 1 to f 3 are included. I_Clk 1 to I_Clk 3 are generated at the same time. In the configuration of FIG. 2, between the frequency f 1 ~f 3, f 2 = f 1/2, and f 3 = relationship f 1/4 is satisfied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11031693A JP2000231487A (en) | 1999-02-09 | 1999-02-09 | Digital signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11031693A JP2000231487A (en) | 1999-02-09 | 1999-02-09 | Digital signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000231487A JP2000231487A (en) | 2000-08-22 |
| JP2000231487A5 true JP2000231487A5 (en) | 2006-03-30 |
Family
ID=12338168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11031693A Pending JP2000231487A (en) | 1999-02-09 | 1999-02-09 | Digital signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000231487A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6591358B2 (en) * | 2001-01-26 | 2003-07-08 | Syed Kamal H. Jaffrey | Computer system with operating system functions distributed among plural microcontrollers for managing device resources and CPU |
| US7730250B2 (en) | 2006-12-27 | 2010-06-01 | Seiko Epson Corporation | Interrupt control circuit, circuit board, electro-optic device, and electronic apparatus |
-
1999
- 1999-02-09 JP JP11031693A patent/JP2000231487A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7005900B1 (en) | Counter-based clock doubler circuits and methods with optional duty cycle correction and offset | |
| US7236557B1 (en) | Counter-based clock multiplier circuits and methods | |
| TW200520387A (en) | Programmable low-power high-frequency divider | |
| TW200733567A (en) | Clock generation circuit and method of generating clock signals | |
| JPH0439690B2 (en) | ||
| US6906571B1 (en) | Counter-based phased clock generator circuits and methods | |
| JP4977717B2 (en) | Frequency divider circuit | |
| KR100967103B1 (en) | Circuit and Method for Generating Clock | |
| JP2000231487A5 (en) | ||
| JP3649874B2 (en) | Frequency divider circuit | |
| ATE446610T1 (en) | FREQUENCY DIVIDER | |
| TW563297B (en) | A multi-cell digital delay generator device wherein the cells have transistor stacks and selective stack transistor bypasses | |
| JPH10215153A (en) | Clock multiplication circuit and semiconductor integrated circuit | |
| KR200164990Y1 (en) | 50% duty odd frequency demultiplier | |
| CN108055019A (en) | Towards the inexpensive ring oscillator of NB-IoT | |
| JP2004153536A (en) | Transceiver module | |
| JPH03171820A (en) | 2n-1 frequency dividing circuit | |
| JPH01319321A (en) | Digital frequency multiplier circuit | |
| JPS61230427A (en) | 2/(2n+1) frequency division circuit | |
| JPH067383Y2 (en) | Clock generator | |
| JP2754005B2 (en) | Polyphase pulse generation circuit | |
| JP2543108B2 (en) | Synchronous pulse generator | |
| JPS62126717A (en) | Serial parallel conversion circuit | |
| JPS63186461A (en) | Large scale integrated circuit | |
| KR940012090A (en) | Clock divider |