JP2000228524A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an reverted staggered polycrystal silicon thin-film transistor together with its manufacturing method wherein the photolithography and thermal process are simplified. SOLUTION: A gate electrode 3 is formed on a glass substrate 1, a polycrystal silicon film 5 is formed through a gate insulating film 4, a phosphorus(P) ion is implanted into the polycrystal silicon film 5 with an insulator layer 6 as a mask to film-form inter-layer insulating films 9 and 11, and then a part of the inter-layer insulating films 9 and 11 on the polycrystal silicon film 5 is opened, through which opening part the phosphorus(P) ion is implanted again to form a source region (N+-Si) 8a and drain region (N+-Si) 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a polycrystalline silicon thin film transistor (hereinafter abbreviated as TFT) having an inverted stagger structure in a liquid crystal display device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional inverted stagger type TFT having an LDD (Lightly Doped Drain) structure is manufactured according to the manufacturing process shown in FIG.

That is, as shown in FIG. 6A, a silicon oxide (Si) is formed on a glass substrate 41 as an undercoat film.
Ox) film 42 is formed and its silicon oxide (SiOx)
A gate electrode 43 made of an Al alloy is formed on the film 42 into a predetermined shape by the first photolithography. Next, a gate insulating film 44 made of SiOx is
Then, a polycrystalline silicon layer 45 is formed.
The polycrystalline silicon layer is formed by forming amorphous silicon into a film, dehydrogenating, and annealing with an excimer laser. Thereafter, an insulator layer SiOx 46 serving as a mask is formed on the entire surface.

[0006] Next, as shown in FIG. 6 (b), the insulator layer SiOx 46 on the polycrystalline silicon layer 45 serving as the channel portion of the TFT is etched into a predetermined shape by the second photolithography. Thereafter, phosphorus (P) ions are ion-doped at an acceleration voltage of 15 kV and a dose of 5 ×.
10 was injected at ¹² / cm ^2, n-type LDD region ⁽ⁿ - -S
i) Form 47. The insulator layer SiOx 46 is used as a mask in the channel portion of the TFT, and phosphorus ions are not implanted. After the ion implantation, the polycrystalline silicon layer 45 is etched into a predetermined shape by the third photolithography.

Next, as shown in FIG. 6C, a portion of the polycrystalline silicon layer 45 is covered with a resist 55 by a fourth photolithography, and phosphorus (P) ions are accelerated by an ion doping method. Voltage 15KV, dose 1 × 10
Implanted at ¹⁵ / cm ² to form n-type source / drain regions 48
After the formation of a and b, the resist 55 is removed. After the implantation is completed, the impurities are activated by a heat treatment at about 400 ° C.

Next, as shown in FIG. 6D, a first interlayer insulating film 49 made of a silicon oxide (SiOx) film is formed, and a transparent conductive film made of indium tin oxide (ITO) is formed for the fifth time. A pixel electrode 50 is formed by etching by photolithography, and a second interlayer insulating film 51 made of a silicon oxide (SiOx) film is formed. Next, the source region (n ⁺ -Si) 48a and the drain region (n ⁺ -Si)
48b, and the interlayer insulating films 49, 5 on the pixel electrodes 50
A part of 1 is opened by etching by a sixth photolithography, and a source / drain wiring 52 formed of a laminated film of aluminum (Al) 52a and titanium (Ti) 52b is formed by a seventh photolithography. I do. Thereafter, a passivation film 53 made of a silicon nitride (SiNx) film is formed, a predetermined position is etched and opened by photolithography for the eighth time, and the semiconductor layer is hydrogenated by heat treatment at 350 ° C. in a hydrogen atmosphere. Then, the TFT is completed.

[0007]

In order to manufacture a TFT having a conventional LDD structure, it is necessary to go through a number of steps as described above, and it is desired to simplify the manufacturing steps.

An object of the present invention is to provide a TFT which can be manufactured by simplifying a photolithography, an etching step, a film forming step, and a heat treatment step as compared with a conventional manufacturing method.

Another object of the present invention is to provide a method of manufacturing a TFT in which the photolithography, etching, film formation, and heat treatment steps are simplified as compared with the conventional manufacturing method.

[0010]

The present invention has the following configuration to achieve the above object.

That is, in the thin film transistor according to the first structure of the present invention, a first conductive layer is selectively formed on one main surface of a substrate, and the first conductive layer is formed on the first main surface via a first insulating layer. A non-single-crystal semiconductor layer is formed so as to partially overlap with the first conductor layer, and a part of the non-single-crystal semiconductor layer is overlapped with the first conductor layer, or A low-concentration impurity region is formed in a self-aligned manner with respect to the end of the conductive layer, and a second insulator layer is deposited on the entire surface; and the second insulator layer on the non-single-crystal semiconductor layer is formed. An opening is formed in the layer, a high-concentration impurity region is formed in the non-single-crystal semiconductor layer in the opening, and a second conductor layer is formed by being connected to the high-concentration impurity region. It is characterized by. According to such a configuration, an inverted staggered TFT having an LDD structure capable of simplifying the photolithography and heat treatment steps can be provided. Further, since the manufacturing process is simplified, it is possible to provide a TFT with small variations in the characteristics of the LDD region.

Further, according to a method of manufacturing a thin film transistor according to a first configuration of the present invention, a step of selectively forming a first conductor layer on one main surface of a substrate, and a step of covering the first insulator layer with the first conductor layer. Attaching a non-single-crystal semiconductor layer, and attaching the non-single-crystal semiconductor layer to a part of the non-single-crystal semiconductor layer so as to overlap with the first conductor layer or at an end of the first conductor layer. Forming a third insulator layer in a self-aligned manner, implanting an impurity into the non-single-crystal semiconductor layer using the third insulator layer as a mask, Depositing a body layer, forming an opening in the second insulator layer over the non-single-crystal semiconductor layer, and injecting impurities directly into the non-single-crystal semiconductor layer through the opening. Performing a step of selectively forming a second conductor layer, and a step of heat treatment. That. According to such a configuration, the inverse stagger type TFT having the LDD structure can be manufactured by simplifying the photolithography and heat treatment steps. Further, since the manufacturing process is simplified, it is possible to manufacture a TFT having a small variation in the characteristics of the LDD region.

In a thin film transistor according to a second configuration of the present invention, a first conductive layer is selectively formed on one principal surface of a substrate, and the first conductive layer is formed on the first main surface via a first insulating layer. A non-single-crystal semiconductor layer is formed so as to partially overlap the first conductor layer, and a second insulator layer is further formed on the entire surface;
An opening is formed in the second insulator layer over the non-single-crystal semiconductor layer, a high-concentration impurity region is formed in the non-single-crystal semiconductor layer in the opening, and the high-concentration impurity region is connected to the non-single-crystal semiconductor layer. A second conductor layer is formed by deposition. According to such a configuration, it is possible to provide an inverted stagger type TFT capable of simplifying the photolithography, the etching step, the film formation step, and the heat treatment step.

According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising the steps of selectively forming a first conductive layer on one main surface of a substrate; Depositing a non-single-crystal semiconductor layer;
Forming an opening in the second insulator layer over the non-single-crystal semiconductor layer; and directly forming impurities in the non-single-crystal semiconductor layer through the opening. , A step of selectively forming a second conductor layer, and a heat treatment step. According to such a configuration, photolithography, an etching step,
The inverse stagger type TFT can be manufactured by simplifying the film forming step and the heat treatment step.

According to each of the above configurations of the present invention,
Since the manufacturing process can be simplified, a liquid crystal display device with reduced manufacturing cost can be provided.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor and a method for manufacturing the same according to the present invention will be described with reference to specific embodiments.

(Embodiment 1) TFT of this embodiment
As shown in FIG. 1, a silicon oxide film 2 as an undercoat film is formed on a main surface of a glass substrate 1, and a gate electrode 3 is selectively formed thereon as a first conductor layer. ing. Further, a gate insulating film 4 is laminated thereon as a first insulator layer. Furthermore, a polycrystalline silicon layer 5 is laminated thereon as a non-single-crystal semiconductor layer so as to overlap the gate electrode 3. An LDD region (n ⁻ −) as an impurity region into which phosphorus (P) ions are implanted at a low concentration is formed on both sides of the polycrystalline silicon layer 5 that are not opposed to the gate electrode 3.
Si) 7 is formed. In addition, phosphorus (P) is added to the polycrystalline silicon layer 5 in the openings of the first interlayer insulating film 9 and the second interlayer insulating film 11 as the second insulator layer formed on the entire surface.
Source region (n ⁺ -Si) 8a and drain region (n ⁺ -Si) 8b as impurity regions into which ions are implanted at a high concentration
Are formed. Furthermore, aluminum (Al) 12a
A source / drain wiring 12 as a second conductor layer, which is made of a laminated film of titanium and titanium (Ti) 12b, is connected to the source region 8a and the drain region 8b through the opening. Further, in order to use this TFT in a liquid crystal display device, a pixel electrode 10 and a passivation film 13 are formed as in the conventional technique.

The TFT according to the present embodiment is manufactured according to the manufacturing steps shown in FIG.

First, as shown in FIG. 2A, a silicon oxide (Si) as an undercoat film is formed on a glass substrate 1.
An Ox) film 2 is formed, and a gate electrode 3 made of an Al alloy is formed on the silicon oxide (SiOx) film 2 in a predetermined shape by the first photolithography. Next, a gate insulating film 4 made of SiOx is formed to a thickness of 100 nm on the entire surface, and then a polycrystalline silicon layer 5 is formed. The polycrystalline silicon layer is formed by forming amorphous silicon into a film, dehydrogenating, and annealing with an excimer laser. Thereafter, an insulator layer SiOx6 serving as a mask is formed on the entire surface.

Next, as shown in FIG. 2B, the insulator layer SiOx 6 on the polycrystalline silicon 5 serving as the channel portion of the TFT is etched into a predetermined shape by the second photolithography. At this time, if the resist is exposed from the back surface of the glass substrate 1 using the gate electrode 3 as a mask, the insulating layer SiOx 6 can be etched while being self-aligned with the end of the gate electrode 3. Thereafter, phosphorus (P) ions are implanted by an ion doping method at an acceleration voltage of 15 kV and a dose of 5 × 10
N-type LDD region (n ^-- Si) 7 implanted at ¹² / cm ²
To form SiOx6 is used as a mask in the channel portion of the TFT, and phosphorus ions are not implanted. After ion implantation, 3
By the second photolithography, the polycrystalline silicon layer 5
Is etched into a predetermined shape.

Next, as shown in FIG. 2C, a first interlayer insulating film 9 made of a silicon oxide (SiOx) film is formed on the entire surface, and a transparent conductive film made of indium tin oxide (ITO) is formed. The pixel electrode 10 is formed by etching by the second photolithography, and the second interlayer insulating film 11 made of a silicon oxide (SiOx) film is formed on the entire surface. next,
An interlayer insulating film 9 on the pixel electrode 10 and on the polycrystalline silicon layer 5 where the source and drain regions are to be formed;
A part of 11 is etched and opened by the fifth photolithography. Then, phosphorus (P) ions are ion-doped through the opening 15 at an acceleration voltage of 20 KV,
The source region (n) is implanted at a dose of 1 × 10 ¹⁵ / cm ² .
⁺ -Si) 8a and a drain region (n ⁺ -Si) 8b. Since the acceleration voltage is low, the polycrystalline silicon layer 5 other than the opening 15 is blocked by the interlayer insulating films 9 and 11 so that phosphorus (P) ions are not implanted.

Next, as shown in FIG. 2D, a source / drain wiring 12 made of a laminated film of aluminum (Al) 12a and titanium (Ti) 12b is formed by etching by a sixth photolithography. . Thereafter, a passivation film 13 made of a silicon nitride (SiNx) film is formed, a predetermined position is etched and opened by photolithography for the seventh time, and a passivation film 13 is formed in a hydrogen atmosphere.
By performing a heat treatment at 0 ° C., the TFT of this embodiment is completed.

Although a similar TFT can be manufactured in a nitrogen atmosphere or an air atmosphere as a heat treatment atmosphere, the connection resistance of the source / drain wiring 12 to the gate electrode 3 can be stabilized by setting the atmosphere to a hydrogen atmosphere.

By changing the temperature of the heat treatment in a hydrogen atmosphere from the conventional 350 ° C. to 400 ° C.,
The activation of phosphorus (P) ions in the D region, the source region, and the drain region can be performed simultaneously with the hydrogenation of the semiconductor layer without performing heat treatment after ion implantation as in the related art. FIG. 3 shows the mobility of the TFT with respect to the heat treatment temperature in a hydrogen atmosphere. As shown in FIG.
At ~ 420 ° C, mobility equivalent to the conventional one is obtained. 360 ° C
In this case, it is considered that the activation of phosphorus (P) ions in the source region and the drain region was insufficient, and a predetermined specific resistance was not obtained, so that the mobility was reduced. Meanwhile, 4
At 40 ° C. or higher, it is considered that the properties of the semiconductor layer were degraded due to the release of hydrogen from the semiconductor layer, and the mobility was reduced.

As described above, in the TFT of the present embodiment, the heat treatment process can be simplified as compared with the conventional case, and the photolithography process can be reduced from eight times to seven times.

(Embodiment 2) TFT of this embodiment
Is an offset structure in which the LDD region is reduced as shown in FIG. That is, a silicon oxide film 22 as an undercoat film is formed on the main surface of the glass substrate 21,
A gate electrode 23 is selectively formed thereon as a first conductor layer. Further thereon, a gate insulating film 24 is laminated as a first insulator layer. Further thereon, a polycrystalline silicon layer 25 is stacked as a non-single-crystal semiconductor layer so as to overlap with the gate electrode 23. Then, the polysilicon layer 2 in the openings of the first interlayer insulating film 29 and the second interlayer insulating film 31 as the second insulator layer formed on the entire surface
5, a source region (n ⁺ -Si) 28a and a drain region (n ⁺ -Si) 28b are formed as impurity regions into which phosphorus (P) ions are implanted at a high concentration. Further, a source / drain wiring 32 as a second conductor layer made of a laminated film of aluminum (Al) 32a and titanium (Ti) 32b is formed in the source region 28a through the opening.
And the drain region 28b. Also, this T
Since the FT is used for the liquid crystal display device, the pixel electrode 30 and the passivation film 33 are formed as in the conventional technology.

The TFT according to the present embodiment is manufactured according to the manufacturing steps shown in FIG.

First, as shown in FIG. 5A, a silicon oxide (S) as an undercoat film is formed on a glass substrate 21.
iOx) film 22 is formed, and its silicon oxide (SiO
x) A gate electrode 23 made of an Al alloy is
A predetermined shape is formed by the second photolithography.
Next, a gate insulating film 24 made of SiOx is
Then, a polycrystalline silicon layer 25 is formed. The polycrystalline silicon layer is formed by forming amorphous silicon into a film, dehydrogenating, and annealing with an excimer laser.

Next, as shown in FIG. 5B, the polycrystalline silicon layer 25 is etched into a predetermined shape by the second photolithography. Next, silicon oxide (S
A first interlayer insulating film 29 made of an iOx) film is formed on the entire surface, a transparent conductive film made of indium tin oxide (ITO) is etched by a third photolithography to form a pixel electrode 30, and a silicon oxide (SiOx) 2) A second interlayer insulating film 31 made of a film is formed on the entire surface.

Next, as shown in FIG. 5C, the interlayer insulating films 29 and 31 on the pixel electrode 30 and on the polycrystalline silicon layer 25 where the source and drain regions are formed.
Is partially opened by etching by the fourth photolithography. Thereafter, phosphorus (P) ions are implanted through the opening 35 by ion doping at an acceleration voltage of 20 KV and a dose of 1 × 10 ¹⁵ / cm ² to form a source region (n ⁺ −
An Si) 28a and a drain region (n ⁺ -Si) 28b are formed. Since the acceleration voltage is low, the polycrystalline silicon layer 25 other than the opening 35 is blocked by the interlayer insulating films 29 and 31 and phosphorus (P) ions are not implanted.

Next, as shown in FIG. 5D, a source / drain wiring 32 made of a laminated film of aluminum (Al) 32a and titanium (Ti) 32b is formed by etching by a fifth photolithography. . Thereafter, a passivation film 33 made of a silicon nitride (SiNx) film is formed, a predetermined position is etched and opened by photolithography for the sixth time, and a 40
By performing a heat treatment at 0 ° C., the TFT of this embodiment is completed.

In this embodiment, similarly to the first embodiment, the temperature of the heat treatment in the hydrogen atmosphere is increased from 350 ° C. to 40 ° C.
By setting the temperature to 0 ° C., activation of phosphorus (P) ions in the source region and the drain region can be performed simultaneously with hydrogenation of the semiconductor layer without performing heat treatment after ion implantation as in the related art. .

As described above, the TFT of the present embodiment is
By reducing the formation of the DD region, the SiOx film forming process, the SiOx etching process, and the heat treatment process can be simplified as compared with the conventional case, and the photolithography process can be reduced from eight times to six times.

In the above embodiment, an n-type TFT in which a semiconductor layer containing impurities is formed by implanting P ions by an ion doping method has been mainly described. Instead of P ions, boron (B) ions are used. If a p-type TFT having an LDD structure can be manufactured by ion-implanting the same, the same effect can be obtained.

[0035]

According to the thin film transistor and the method of manufacturing the same according to the first structure of the present invention, an inverted stagger type TFT having an LDD structure with simplified photolithography and heat treatment steps can be obtained. In addition, since the manufacturing process is simplified, a TFT having a small variation in the characteristics of the LDD region can be obtained.

Further, according to the thin film transistor and the method of manufacturing the same according to the second configuration of the present invention, it is possible to manufacture an inverted stagger type TFT in which photolithography, etching, film formation, and heat treatment steps are simplified. Can be.

According to each of the above configurations of the present invention,
Since the manufacturing process can be simplified, a liquid crystal display device with reduced manufacturing cost can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a thin film transistor according to Embodiment 1 of the present invention.

FIG. 2 is a sectional view showing a method of manufacturing the thin film transistor according to Embodiment 1 of the present invention in the order of steps;

FIG. 3 is a diagram illustrating mobility of a thin film transistor with respect to a heat treatment temperature in a hydrogen atmosphere in Embodiment 1 of the present invention.

FIG. 4 is a cross-sectional view of a thin film transistor according to Embodiment 2 of the present invention.

FIG. 5 is a sectional view showing a method of manufacturing a thin film transistor according to Embodiment 2 of the present invention in the order of steps;

FIG. 6 is a sectional view showing a conventional method of manufacturing a thin film transistor in the order of steps.

[Explanation of symbols]

Reference Signs List 1 glass substrate 2 undercoat film (silicon oxide film) 3 first conductor layer (gate electrode) 4 first insulator layer (gate insulating film) 5 non-single-crystal semiconductor layer (polycrystalline silicon layer) 6 insulator Layer 7 LDD region (n ^-- Si) 8a Source region (n ⁺ -Si) 8b Drain region (n ⁺ -Si) 9 First interlayer insulating film 10 Pixel electrode 11 Second interlayer insulating film 12a, 12b Second conductivity Body layer (source / drain wiring) 13 Passivation film 15 Opening 21 Glass substrate 22 Undercoat film (silicon oxide film) 23 First conductor layer (Gate electrode) 24 First insulator layer (Gate insulating film) 25 Non-single-crystal semiconductor layer (polycrystalline silicon layer) 28a Source region (n ⁺ -Si) 28b Drain region (n ⁺ -Si) 29 First interlayer insulating film 30 Pixel electrode 31 Second interlayer Insulating films 32a, 32b Second conductor layer (source / drain wiring) 33 Passivation film 35 Opening

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Claims (6)

[Claims] 1. A first conductor layer is selectively formed on one principal surface of a substrate, and is formed so as to partially overlap with the first conductor layer via a first insulator layer. A single-crystal semiconductor layer is deposited and formed on a part of the non-single-crystal semiconductor layer so as to overlap the first conductor layer or in a self-aligned manner with respect to the end of the first conductor layer. Forming a low-concentration impurity region, further covering the entire surface with a second insulator layer, forming an opening in the second insulator layer over the non-single-crystal semiconductor layer, A thin film transistor, wherein a high-concentration impurity region is formed in the non-single-crystal semiconductor layer, and a second conductor layer is formed so as to be connected to the high-concentration impurity region. 2. A step of selectively forming a first conductor layer on one principal surface of a substrate; a step of depositing a first insulator layer; and a step of depositing a non-single-crystal semiconductor layer. A third insulator layer is coated on a part of the non-single-crystal semiconductor layer so as to overlap with the first conductor layer or in a self-aligned manner with respect to the edge of the first conductor layer. Forming a non-single-crystal semiconductor layer using the third insulator layer as a mask, implanting an impurity into the non-single-crystal semiconductor layer, depositing a second insulator layer, Forming an opening in the upper second insulator layer; implanting impurities directly into the non-single-crystal semiconductor layer through the opening; selectively forming a second conductor layer And a heat treatment step. 3. A first conductor layer is selectively formed on one principal surface of a substrate, and is formed so as to partially overlap with the first conductor layer via a first insulator layer. A single-crystal semiconductor layer is formed on the non-single-crystal semiconductor layer; an opening is formed in the second insulating layer on the non-single-crystal semiconductor layer; A thin film transistor, wherein a high-concentration impurity region is formed in the non-single-crystal semiconductor layer, and a second conductor layer is formed by being connected to the high-concentration impurity region. 4. A step of selectively forming a first conductor layer on one main surface of a substrate; a step of depositing a first insulator layer; and a step of depositing a non-single-crystal semiconductor layer. A step of applying a second insulator layer; a step of forming an opening in the second insulator layer over the non-single-crystal semiconductor layer; and the non-single-crystal semiconductor through the opening. A method for manufacturing a thin film transistor, comprising: a step of directly injecting an impurity into a layer; a step of selectively forming a second conductor layer; and a heat treatment step. 5. The method of manufacturing a thin film transistor according to claim 2, wherein the heat treatment is performed in a hydrogen atmosphere. 6. The heat treatment step is performed at 380 ° C. or more and 420
The method for manufacturing a thin film transistor according to claim 2, wherein the method is performed in a temperature range of not more than ℃.