JP2000228095A - Read-out circuit for non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an one chip microcomputer having an on-screen display function compact and general purpose, and to make characters of the computer large and fine. SOLUTION: This circuit has constitution that program data or data to be operated for performing control operation such as various logical operation and the like are stored in a storage region A of a flash memory L1 and a storage region B of a flash memory R2, also, data for display are stored in a storage region A1 of the flash memory L1 and a storage region B1 of a flash memory R1. Thereby, a chip can be miniaturized by sharing a memory core. Also, the circuit has constitution in which data for display of four bytes are held en bloc in a latch circuit 9. Thereby, making the circuit general purpose, making characters large and fine can be performed as the number of dots of character font in the horizontal direction is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a read circuit of a nonvolatile memory.

[0002]

2. Description of the Related Art A one-chip microcomputer for performing on-screen display on a screen such as a CRT, a liquid crystal, etc.
It is necessary to incorporate a character generator ROM.
The character generator ROM stores data corresponding to display dots on a screen such as a CRT and a liquid crystal. For example, a logical value “1” is stored to turn on a dot, and a logical value “0” is stored to turn off a dot. If the character font is m * n dots in length and width, the character generator ROM stores m * n bits corresponding to characters formed by lighting or extinguishing a predetermined position on the character font for each address. The display data is stored.

Also, a one-chip microcomputer needs to incorporate a nonvolatile program ROM for controlling its own logical operation.

Therefore, in a one-chip microcomputer related to such an on-screen display, a character generator ROM and a program ROM are integrated on the same chip independently.

[0005]

However, in order to make the character generator ROM and the program ROM independent,
There is a problem that the chip area is increased due to the duplication of the control circuit and the increase in the number of wirings.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem, and has been described as a program data or an object to be operated for executing various logical operations on a first storage area. A non-volatile memory in which data related to display is written in the second storage area;
A first address circuit for designating a first storage area of the nonvolatile memory in one address unit, a second address circuit for simultaneously designating a second storage area of the nonvolatile memory in a plurality of predetermined address units, A switching circuit for switching between the first and second address circuits at a timing of operation control and display control of a computer, and a holding circuit for collectively holding data relating to the display simultaneously read from a second storage area of the nonvolatile memory Wherein the number of bits of the data relating to the display is set to be equal to or larger than the number of dots constituting one direction of the display font.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a read circuit of a nonvolatile memory according to the present invention. The circuit shown in FIG. 1 is built in a one-chip microcomputer.

The one-chip microcomputer has a built-in program memory having non-volatile characteristics. The program memory stores program data for causing the one-chip microcomputer to perform various logical operations, table data to be subjected to various logical operations, and the like. It is memorized.

In FIG. 1, a flash memory L (1)
And the flash memory R (2) have a nonvolatile property that data can be electrically erased in a specific block unit and data can be repeatedly written and read. Evenly divided. The flash memory L (1) and the flash memory R (2) store program data for causing the one-chip microcomputer to perform various logical operations, and table data to be subjected to various logical operations. The flash memory L (1) and the flash memory R (2)
For example, the total storage capacity is 64 Kbytes (byte is a unit of 8 bits per word), and a 2-byte unit is a small block and a 64-byte unit is a large block. Flash memory L (1) and flash memory R
(2) alternately repeats even-numbered large blocks EVEN and odd-numbered large blocks ODD (0, 2, 4... Are even-numbered, 1, 3, 5... Are odd-numbered). Further, small block data in units of 2 bytes is alternately stored in the flash memories L (1) and R (2). For example, the flash memory L
The address values in the first even-numbered large block constituting the flash memory R (2) are “00H,
01H, 04H, 05H, ... 78H, 79H, 7C
H, 7DH "," 02H, 03H, 06H, 07H, ...
7AH, 7BH, 7EH, 7FH ". The address values in the first odd-numbered large blocks constituting the flash memory L (1) and the flash memory R (2) are “80H, 81H, 84H, 85H,.
F9H, FCH, FDH "," 82H, 83H, 86H,
87H,..., FAH, FBH, FEH, FFH ”. Here, H represents hexadecimal hexadecimal. still,
The storage area A1 of the flash memory L (1) has a CRT,
Display data for displaying in units of dots is stored on a liquid crystal screen or the like, and program data for controlling the operation of the one-chip microcomputer is stored in the storage area A2. Similarly, the storage area B1 of the flash memory R (2)
Stores display data for performing display in dot units on a CRT, a liquid crystal screen, or the like, and program data for controlling the operation of the one-chip microcomputer is stored in the storage area B2.

[0011] The row decoder L (3) has a capacity of 64 in one of the storage areas A1 and A2 of the flash memory L (1).
One of the large blocks is selected in byte units. The column decoder L1 (4)
Select any one small block in units of 2 bytes from any one large block in units of 64 bytes selected in (3) and read from the storage area A1 of the flash memory L (1). Is what you do. The sense amplifier L (5) amplifies current of 2-byte data selectively output from the column decoder L1 (4).

The row decoder R (6) stores 64 bits in one of the storage areas B1 and B2 of the flash memory R (2).
One of the large blocks is selected in byte units. The column decoder R1 (7)
Select one small block in units of 2 bytes from any one large block in units of 64 bytes selected in (6) and read from the storage area B1 of the flash memory R (2). Is what you do. The sense amplifier R (8) amplifies current of 2-byte data selectively output from the column decoder R1 (7).

The latch circuit (9) includes a sense amplifier L
(5) and a total of 4 output from the sense amplifier R (8)
This latches byte data. The display control circuit (10) performs character display on a CRT, a liquid crystal screen, or the like based on 32-bit display data representing lighting and extinguishing, latched by the latch circuit (9).

The column decoder L2 (14) selects one of the 64-byte units selected by the row decoder L (3) and read from the storage area A2 of the flash memory L (1).
One byte is selected from the large blocks.
The column decoder R2 (15) is a row decoder R (6)
And selects one byte from any one of the large blocks in units of 64 bytes read from the storage area B2 of the flash memory R (2). The sense amplifier (16) amplifies current of 1-byte unit program data which is selectively output complementarily from the column decoder L2 (14) or the column decoder R2 (15). The latch circuit (17) latches the current amplification output of the sense amplifier (16). The output of the latch circuit (17) is decoded by the instruction decoder (18) in synchronization with the operation timing of the one-chip microcomputer. The one-chip microcomputer executes various logical operation operations and the like according to the decoding result at this time.

Storage area A1 of flash memory L (1)
The address data specifying the storage area B1 of the flash memory R (2) is generated from a video RAM (VRAM). Address data specifying the storage area A2 of the flash memory L (1) and the storage area B2 of the flash memory R (2) is generated from a program counter (PC).

The address selection circuit (19) is a video RAM
Or the value of one of the program counters as the switching signal C
/ O is selected and output. FIG. 2 is a diagram illustrating an example of one machine cycle of a one-chip microcomputer. One machine cycle includes six states S1 to S6, and CPU operations are performed only in states S1 and S4. That is, the switching signal C / O is a high-level signal only in the states S1 and S4. Therefore, the address selection circuit (19)
Selects and outputs the value of the program counter when the switching signal C / O is at a high level, and selectively outputs the value of the video RAM when the switching signal C / O is at a low level.

The 17-bit value PAR16-0 of the video RAM selectively output from the address selection circuit (19) addresses the storage area A1 of the flash memory L (1) and the storage area B1 of the flash memory R (2). This is the data for Here, since the flash memory L (1) and the flash memory R (2) have a regularity of storing program data alternately in units of 2 bytes, the lower second bit PAR1 of the address data is the flash memory L
Bits XADL0 and XADR0 for selecting either (1) or flash memory R (2). However, in the embodiment of the present invention, the flash memory L (1)
This is a configuration in which simultaneous reading is performed in units of 2 bytes from the storage area A1 and the storage area B1 of the flash memory R (2).

Lower 7-3 bits PAR of address data
6-2 and the least significant bit PAR0 are the flash memory L
Any one set of 2 in a large block constituting the storage area A1 of (1) and the storage area B1 of the flash memory R (2)
Bits YADL5-0, Y for selecting byte data
Used as ADR5-0.

Lower 8 bits of address data PAR7
Is used to select even-numbered or odd-numbered large blocks in the storage areas A1 and B1 because the lower bits PAR7-3 and PAR0 are bits for selecting the inside of the large blocks in the storage areas A1 and B1. Bits YADL6, YAD
Used as R6. That is, YADL6 = 0, YAD
When R6 = 0, the selection operation of the even-numbered large block in the storage areas A1 and B1 is executed, while YADL6 = 1 and Y
When ADR6 = 1, the operation of selecting an odd-numbered large block in the storage areas A1 and B1 is executed.

Upper 9 bits of address data PAR16
-8 is a bit XADL9-1, XADR for selecting any one large block constituting the storage areas A1 and B1.
Used as 9-1.

The address circuit ADSINC (11)
7-bit address data PAR16-0 is supplied,
The upper 9 bits PAR16-8 are XADL9-1.
And the lower 8 bits PAR7-0 of the PAR7-0
Output as −0. Address circuit ADSINC (1
The upper 9 bits XADL9-1 passed through 1) are supplied to the row decoder L (3). The upper 9 bits PAR16-8 of the address data are directly supplied to the row decoder R (6) as XADR9-1.

The address circuit CROSS (12) outputs the lower 8 bits F passed through the address circuit ADSINC (11).
AL7-0 is supplied. Address circuit CROSS (1
2) indicates that the lower second bit FAL1 is the flash memory L
Since this is a bit for identifying (1) and the flash memory R (2), the output of the FAL1 is prohibited, and the most significant bit FAL7 is set to the even and odd numbers of the flash memory L (1) and the flash memory R (2). FAL7 is output as YADL6 because it is a bit for identifying the second large block. YADL6 is supplied to the row decoder L (3). Row decoder L (3) is XADL9-1, YA
Decodes a total of 10 bits of DL6 to flash memory L
(1) Large block selection of the storage area A1 is performed. That is,
The row decoder L (3) is composed of XADL9-1, YADL6
1024 large blocks can be selected according to the value of. Further, the address circuit CROSS (12)
6-2, FAL0 is output as YADL5-0. Y
ADL5-0 is supplied to the column decoder L1 (4). The column decoder L1 (4)
From among the large blocks selected in (3), YADL5-
The 2-byte data corresponding to the value of 0 is selected.

In the address circuit CROSS (13), the lower 8 bits PAR7-0 of the address data are stored in the FAR7-0.
Supplied directly as. Address circuit CROSS (1
3) indicates that the lower second bit FAR1 is the flash memory L
Since these bits are for identifying (1) and the flash memory R (2), the output of FAR1 is prohibited, and the most significant bit FAR7 is set to the even-numbered and odd-numbered bits of the flash memory L (1) and the flash memory R (2). FAR7 is output as YADR6 because it is a bit for identifying the second large block. YADR6 is supplied to the row decoder R (6). Row decoder R (6) is XADR9-1, YA
Decodes a total of 10 bits of DR6 to flash memory R
The large block selection of the storage area B1 in (2) is performed. That is,
The row decoder R (3) is XADR9-1, YADR6
1024 large blocks can be selected according to the value of. Further, the address circuit CROSS (13)
6-2, Output FAR0 as YADR5-0. Y
ADR5-0 is supplied to the column decoder R1 (7). The column decoder R1 (7)
From among the large blocks selected in (6), YADR5-
The 2-byte data corresponding to the value of 0 is selected.

The address circuit ADSINC (11) stores the address data PAR16-0 in the flash memory R
It is detected whether the value is a value for selecting the last two bytes in the large block constituting the storage area B1 of (2). There is no problem in reading two-byte data from the same even-numbered or the same odd-numbered large block in the storage areas A1 and B1, but there is no problem. Last two of the block
To read the byte data and the first 2-byte data of the odd-numbered large block immediately following the even-numbered (or even-numbered immediately following the odd-numbered) large block in the storage area A1 of the flash memory L (1), use XADL9- 1, XAD
R9-1 cannot be executed with the same value. Therefore, the address circuit ADSINC (11) sets the flash memory L
When the address data PAR16-0 is generated according to the data read operation from the storage area A2 of (1) or the storage area B2 of the flash memory R (2), the address data PAR16-0 at this time is stored in the flash memory R (2).
Of the selected block in the storage area B1 of the flash memory L (1), and if so, a bit XADL9-1 for selecting a block of the storage area A1 in the flash memory L (1). Is incremented by +1 to invert FAL7, which is a bit YADL6 for identifying an even or odd block. Thus, for example, the storage area B1 of the flash memory R (2)
Last two bytes of the odd-numbered block "FEH, FF
H "is read out, the flash memory L
First two bytes "100H, 101H" of the even block immediately after the odd block in the storage area A1 of (1).
Is read out. That is, the latch circuit (9) latches continuous 4-byte display data in the storage areas A1 and B1, and the display control circuit (10) displays a dot at a display designated position on a CRT, a liquid crystal screen, or the like based on the display data. Let it. According to the embodiment of the present invention, since the latch circuit (9) collectively holds 4-byte display data, the horizontal direction of the character font can correspond to a character of up to 32 dots. It has the effect of enabling the definition of characters and the like.

The 17-bit value PC16-0 of the program counter selectively output from the address selection circuit (19)
Is data for addressing the storage area A2 of the flash memory L (1) and the storage area B2 of the flash memory R (2). PC16-6 is a row decoder L
(3) and the row decoder (6).
Are the column decoder L2 (14) and the column decoder R2
(15).

Sense amplifier L (5), sense amplifier R
(8), address circuit ADSINC (11), address circuit CROSS (12), address circuit CROSS (1
3) operates when the switching signal C / O is at a low level, and the sense amplifier (16) operates when the switching signal C / O is at a high level.

In the embodiment of the present invention, the flash memory L (1) and the flash memory R (2) store data in units of 2 bytes alternately, but generally store data in units of power of 2 bytes. A configuration in which the data is stored alternately can be adopted.

[0028]

According to the present invention, the first nonvolatile memory can be used.
The storage area stores program data or data to be operated on, and the second storage area stores display data. Thus, the size of the chip can be reduced by sharing the memory core. Further, the configuration is such that the holding circuit collectively holds display data of a plurality of addresses.
Thus, as the number of dots in the horizontal direction of the character font increases, generalization, enlargement of characters, and refinement of characters can be achieved. Further, since the character generator ROM and the program ROM are provided in one memory space, the memory space can be arbitrarily divided, and versatility is improved. Such advantages can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a read circuit of a nonvolatile memory of the present invention.

FIG. 2 is a diagram showing an example of one machine cycle of a one-chip microcomputer.

[Explanation of symbols]

 (1) Flash memory L (2) Flash memory R (3) Row decoder L (4) Column decoder L1 (6) Row decoder R (7) Column decoder R1 (9) Latch circuit (10) Display control circuit (11) Address circuit ADSINC (12) (13) Address circuit CROSS (14) Column decoder L2 (15) Column decoder R2 (17) Latch circuit

Claims (1)

[Claims] A non-volatile memory in which program data for performing various logical operations or data to be operated is written in a first storage area, and data relating to display is written in a second storage area; A first address circuit that specifies a first storage area of the nonvolatile memory in units of one address, a second address circuit that simultaneously specifies a second storage area of the nonvolatile memory in units of a plurality of predetermined addresses, A switching circuit for switching between the first and second address circuits at a timing of operation control and display control of a computer; and a holding circuit for collectively holding data relating to the display simultaneously read from a second storage area of the nonvolatile memory. The number of bits of data related to the display is set to be equal to or more than the number of dots constituting one direction of a display font. Readout circuit of the nonvolatile memory, wherein the door.