JP2000224753A - Power protective circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small power productive circuit with small power consumption for protecting a DC power supply against an overcurrent. SOLUTION: A power protective circuit includes a breaking circuit 1 for supplying power from a DC power supply 4 to a load 3 by turning on a power switch SW1 and a rush-current limiting circuit 2. A voltage by turning on the power switch SW1 is divided with resistors R1 and R2 to apply the divided voltage as a gate voltage to a breaking transistor Q1 and turn on the breaking transistor Q1. A current detecting resistor R3 is connected in serial with a breaking transistor Q1. Through a first auxiliary transistor Q2 that is turned on with a voltage in an overcurrent state, a gate voltage of a breaking transistor Q1 is bypassed. An on-state of the first auxiliary transistor Q2 is held through a second auxiliary transistor Q3 that is turned on by the on-state of the first auxiliary transistor Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply protection circuit including an inrush suppression circuit and a cutoff circuit. An on-board power supply provided with a power supply unit for supplying DC power from a DC power supply to a plurality of panels and small devices and converting the power to a voltage required for each panel and small devices is relatively frequently employed. In such a case, if an overcurrent flows due to the occurrence of a failure in one panel or small device, the voltage of the DC power supply drops, adversely affecting other panels or small devices, and in the worst case, all operations stop. May be. Therefore, it is necessary to provide reliable protection when an overcurrent occurs.

[0002]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional example.
21-n are fuses, 22-1 to 22-n are inrush suppression circuits, 23-1 to 23-n are loads, 24 is a DC power supply, S
W is a power switch. Fuses 21-1 to 21-n
And inrush suppression circuits 22-1 to 22-n and loads 23-1 to 2
Reference numeral 3-n denotes a panel or a small device, and the load 23 includes various electronic circuits including an on-board power supply such as a switching power supply.

In such a configuration, a power switch S
W is turned on and the DC power supply 24 is
When the operating power is supplied from the
−n, when an excessive current flows through each fuse 21
-1 to 21-n are blown to protect the DC power supply 24.

When an overcurrent flows through the loads 23-1 to 23-n, the voltage of the DC power supply 24 decreases. In an extreme case, if the voltage drop due to the failure of the load of one individual panel or individual device becomes large, the voltage drops below the allowable input voltage of another individual panel or individual device, and all operations stop. Therefore, it is necessary to quickly disconnect the individual panel or the individual device of the faulty load from the DC power supply 24. Therefore, fuses 21-1 to 21-1 that blow when an excessive current flows
21-n are provided.

[0005] However, the operating time of the fuses 21-1 to 21-n is 10 m corresponding to the current magnification with respect to the rated value.
s to about 1 s. Therefore, it has been difficult to quickly separate the load of failure occurrence. Also blown fuse 21
-1 to 21-n need to be replaced.

Therefore, it has been proposed to use a thermistor or a conductive polymer which does not need to be replaced in place of the fuses 21-1 to 21-n. However, there is a disadvantage that the time until the shutoff is long, and it is difficult to protect the DC power supply 24 by providing it on an individual panel or an individual device as described above.

FIG. 9 is an explanatory view of a conventional example provided with a cutoff circuit, wherein 31 is a cutoff circuit, 32 is an inrush suppression circuit, 33 is a load, 34 is a DC power supply, SW is a power switch, C11 is a capacitor, D11, D11, D12 is a diode, ZD11 to ZD
D13 is a Zener diode, S1 and S2 are solid state relays, PD1 and PD2 are phototransistors, P
T1 and PT2 are phototransistors, and R11 to R14 are resistors.

The solid state relay S2 of the inrush suppression circuit 32 has a configuration in which a resistor R14 and a Zener diode ZD13 are connected to the phototransistor PD2 and operates at a lower speed than the solid state relay S1 of the cutoff circuit 31. Therefore, when the power switch SW is turned on,
A current flows through the photodiode PD2 of the solid state relay S2 via the Zener diode ZD13 and the resistor R14, and the phototransistor PT2 gradually shifts to the ON state. That is, the state shifts from the high resistance state to the low resistance state. Thereby, the rush current can be suppressed.

The solid-state relay S1 of the cutoff circuit 31 includes a Zener diode ZD11 and a resistor R11.
Then, a current flows through the photodiode PD1 via the diode D11 and the capacitor C11. Therefore, when the power switch SW is turned on, the phototransistor PT1 is turned on. When the charging of the capacitor C11 is completed, the photodiode PD1
Since current flows through the Zener diode ZD11 and the resistor R12, the solid state relay S1 keeps on.

When the power switch SW is turned off, the solid state relays S1 and S2 are turned off, and the capacitor C11 is connected to the diode D13, the load 33,
It is discharged through the path of the resistor R13 and the diode D12 and returns to the initial state. The resistance R13 is relatively high, and is set so that when the power switch SW is turned on and the solid state relays S1 and S2 are turned off, the current flowing through the load 33 has a small value.

When an overcurrent flows through the load 33 and the voltage between its terminals decreases, the current flowing through the photodiodes PD1 and PD2 of the solid-state relays S1 and S2 of the shut-off circuit 31 decreases, and the phototransistor PT2 gradually turns off. An attempt is made to shift from the on-state to the off-state, but the phototransistor PT1 is turned off sufficiently earlier than the phototransistor PT2 due to a decrease in the current flowing through the photodiode PD1. Therefore, the photodiode PD2 of the solid state relay S2 is not affected by the voltage drop, so that the on state can be continued. Thereby, the load 33 can be disconnected from the DC power supply 34. In this state, the capacitor C11 has a small current flowing through the path of the Zener diode ZD1, the photodiode PD1, the resistor R11, the diode D11, and the capacitor C11 so that the solid state relay S1 is not turned on. Will not do. As a result, a trigger for turning on the solid state relay S1 cannot be generated again, and the disconnection of the load by the solid state relay S1 is continued.

[0012]

A configuration for separating a load in an overload state from a DC power supply using a conventional fuse is as follows.
The time required for disconnection is long, there is a problem of spreading to other individual panels and individual devices, and there is a problem that a blown fuse needs to be replaced.

Further, in the conventional example using the solid state relay S1, the load 33 in the overload state can be separated at a relatively high speed. However, solid state relay S1,
In S2, it is necessary to always supply a current to the photodiode in order to maintain the ON state, and power consumption increases. Further, there is a problem that it is not easy to reduce the size. An object of the present invention is to provide a configuration that can be reduced in power consumption and reduced in size.

[0014]

A power supply protection circuit according to the present invention comprises an inrush suppression circuit 2 for suppressing an inrush current to a load 3 when a power switch SW1 is turned on, and a cutoff current supplied to the load when an overload occurs. A power supply protection circuit including a shutoff circuit 1 for turning on a power supply switch SW1 to apply a voltage to a resistor R1,
A voltage is divided by R2 to obtain a gate voltage, a shutoff transistor Q1 which is turned on by the gate voltage to supply a current to the load 3, a current detecting resistor R3 connected in series with the shutoff transistor Q1, and Resistance R
3 turns on when the voltage across both ends corresponds to the load current at the time of overload: a first auxiliary transistor Q2 that bypasses the gate voltage of the shutoff transistor Q1 and turns off the shutoff transistor Q1, When the first auxiliary transistor Q2 is turned on, a gate voltage is applied to turn on the first auxiliary transistor Q2, and a second auxiliary transistor Q is applied to the first auxiliary transistor Q2 to apply a gate voltage for maintaining the ON state.
3 is provided.

Further, by connecting a resistor for suppressing an inrush current in parallel with the blocking transistor Q1, the blocking circuit and the inrush suppression circuit can be shared.

[0016]

FIG. 1 is an explanatory view of a first embodiment of the present invention, wherein 1 is a cutoff circuit, 2 is an inrush suppression circuit,
Is a load, 4 is a DC power supply, SW1 is a power switch, Q1 is a shutoff transistor (n-channel FET), and Q2 is a first
Auxiliary transistor (n-channel FET), Q3 is the second
Auxiliary transistors (p-channel FETs), D1, D2
Is a diode, ZD1 to ZD4 are Zener diodes,
R1 to R6 indicate resistance. The DC power supply 4 shows a case where the positive electrode (+) is grounded (GND).
The operation is performed by applying the ground GND and -V.

Further, the shut-off transistor Q1 and the current detecting resistor R3 are connected in series, the voltage from the DC power supply 4 when the power switch SW1 is turned on is divided by the resistors R1 and R2, and the cut-off transistor is connected via the diode D1. This is applied as the gate voltage of Q1. The voltage across the current detection resistor R3 is set as the gate voltage of the first auxiliary transistor Q2 via the resistor R4. Also, the second auxiliary transistor Q
3 is connected between the positive and negative power supply lines via resistors R4 and R6, and the gate thereof is connected to a Zener diode ZD3 and a diode D3.
2, a diode D1 and a blocking transistor Q
A resistor R5 connected to the gate of the first transistor and the drain of the first auxiliary transistor Q2 and connected in parallel with a Zener diode ZD4 is connected between the gate and the source.

When the power switch SW1 is turned on as shown by the dotted line, the divided voltage by the resistors R1 and R2 is applied to the gate of the shut-off transistor Q1 as a gate voltage through the path. Is turned on. As a result, power is supplied from the DC power supply 4 to the load 3 via the inrush suppression circuit 2. In this case, the rush current when the load 3 has a capacitor-input configuration or the like is suppressed by the rush suppression circuit 2, and a voltage drop due to the rush current can be prevented.

The voltage across the current detecting resistor R3 is applied as a gate voltage to the gate of the first auxiliary transistor Q2. When no overcurrent flows through the load 3, the first auxiliary transistor Q2 is turned on. The off state is continued. When the first auxiliary transistor Q2 is off, the Zener voltages of the resistors R1, R5, R6 and the Zener diode ZD3 are set so that the cathode voltage of the diode D1 is higher than the cathode voltage of the diode D2. As a result, no gate voltage is applied to the gate of the second auxiliary transistor Q3, so that the off state is maintained.

The Zener diode ZD1 is for preventing the gate voltage of the blocking transistor Q1 from becoming excessive. The Zener diode ZD2 is for preventing the gate voltage of the first auxiliary transistor Q2 from becoming excessive. It is for preventing. Zener diode Z
D4 is for preventing the gate voltage of the third auxiliary transistor Q3 from becoming excessive. When the power switch SW1 is turned off, no gate voltage is applied to the shutoff transistor Q1, so that the transistor is turned off. That is,
It will be in the initial state.

FIG. 2 is an explanatory diagram of an overload according to the first embodiment of the present invention. When a current I flowing through a load 3 exceeds a set value, a voltage across a resistor R3 for current detection increases. ,
The gate voltage is applied through the path to the gate of the transistor Q2 via the resistor R4, so that the first auxiliary transistor Q2 is turned on. As a result, a current flows through the first auxiliary transistor Q2 through a path through the resistor R1 and the diode D1, and the gate voltage of the blocking transistor Q1 is bypassed. Thereby, the cutoff transistor Q1 is turned off. That is, the overcurrent caused by the overload state of the load 3 is detected, and the power supplied from the DC power supply 4 can be instantaneously cut off.

When the first auxiliary transistor Q2 is turned on, the path in FIG. 3, that is, R6 → R5
Current flows through the path of → ZD3 → D2 → Q2.
Thereby, the second auxiliary transistor Q3 is turned on. When the second auxiliary transistor Q3 is turned on, a current flows through the path shown in FIG. 4, that is, the path of R6 → Q3 → R4, and the divided voltage by the resistors R6 and R4 is applied to the gate of the first auxiliary transistor Q2. Applied as a voltage
Since the auxiliary transistor Q2 continues to be on, the second auxiliary transistor Q3 also keeps on, so that the shutoff transistor Q1 can be kept off.

After the shutoff transistor Q1 is turned off, the power can be returned to the initial state by turning off the power switch SW1. In general, the load 3 includes an on-board power supply as described above, and includes a shutoff circuit 1 and an inrush suppression circuit 2 and can be inserted into and removed from slots called cards, panels, boards, packages, and the like. Since the configuration is connected to the DC power supply 4 by insertion, the load 3 in the overloaded state is in the case of a failure, so it must be removed, repaired and inserted, and reset. There is no need to provide a function. Note that a reset switch corresponding to the power switch SW1 can be provided as needed.

FIG. 5 is an explanatory view of a second embodiment of the present invention, wherein the same reference numerals as those in FIG. 1 denote the same parts. This embodiment has a configuration in which the negative electrode (-) of the DC power supply 4 is grounded. Therefore, the load 3 has a voltage application configuration of the ground GND and + V. In this case, the circuit configuration of FIG. 1 may be inverted in accordance with the polarity. However, in FIG. 5, according to the inversion of the polarity of the DC power supply 4, the shutoff transistor Q1 and the first The auxiliary transistor Q2 is changed from an n-channel FET to a p-channel FET, and the second auxiliary transistor Q3 is changed from a p-channel FET to an n-channel FET.
And the connection polarities of the diodes D1 and D2 and the Zener diodes ZD1 to ZD4 are inverted. Further, the operation when the power switch SW1 is turned on is the same as that of the above-described embodiment, and the duplicated description will be omitted.

FIG. 6 is an explanatory view of the third embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same parts, R7 is a resistor, and C1 is a capacitor. In this embodiment, a resistor R7 for suppressing an inrush current is connected in parallel with the blocking transistor Q1.
Are connected, so that the cutoff circuit and the rush suppression circuit can be used together.

That is, when the power switch SW1 is turned on, the voltage divided by the resistors R1 and R2 becomes equal to the voltage of the capacitor C1.
Rise according to the charging time constant of. That is, since the gate voltage of the cutoff transistor Q1 gradually increases, it does not immediately turn on even when the power switch SW1 is turned on. As a result, a current flows to the load 3 via the resistor R7, so that an inrush current can be suppressed. And
When the gate voltage rises to a predetermined value, the shutoff transistor Q1 turns on, and a current flows to the load 3 via the shutoff transistor Q1.

When an overcurrent flows due to a failure in the load 3 or the like, the voltage across the current detecting resistor R3 increases as in the case described above, and the first auxiliary transistor Q2 is turned on. The gate voltage of the blocking transistor Q1 is bypassed. As a result, the cutoff transistor Q1 is turned off, and the overcurrent can be cut off to protect the DC power supply 4.

FIG. 7 is a schematic explanatory view of an embodiment of the present invention, in which a DC power supply 4 as a power supply source and a power switch S
In the case where the load 3 is mounted on W1 and the individual panel or the individual device, (A) the load 3 is connected to the DC power supply 4 via the cutoff circuit 1 and the inrush suppression circuit 2, and the power switch SW1 is turned on. By doing so, the case where power is supplied from the DC power supply 4 to the load 3 is shown, which corresponds to the embodiment shown in FIG. It is also possible to adopt a configuration in which the polarity of the DC power supply 4 is inverted as shown by a dotted line.
Corresponds to the embodiment shown in FIG.

FIG. 3B shows a case where the load 3 is connected to the DC power supply 4 via the inrush suppression circuit 2 and the cutoff circuit 1. In this configuration, as shown by the dotted line, 4 can be inverted. 6C shows the case where the load 3 is connected to the DC power supply 4 via the rush suppression and cutoff circuit 5, and corresponds to the embodiment shown in FIG. Also in this case, the polarity of the DC power supply 4 can be inverted as shown by a dotted line.

[0030]

As described above, according to the present invention, when the power switch SW1 is turned on, a gate voltage is applied to turn off the switching transistor Q1 and the current detecting resistor R3. A first auxiliary transistor Q2 that is connected in series and is turned on with a voltage at the time of an overcurrent by the current detecting resistor R3 as a gate voltage, and a cutoff transistor Q2 that is turned on by the first auxiliary transistor Q2.
1 to bypass the gate voltage,
1 is rapidly turned off, and a gate voltage is applied via a first auxiliary transistor Q2 to turn on the second auxiliary transistor Q2, and a second auxiliary transistor Q3 for continuously applying a gate voltage to the first auxiliary transistor Q2. And

Therefore, since the cutoff circuit 1 can be configured using a field effect transistor, power consumption can be reduced. Transistor Q
Since only the control transistor is required except for 1 and the current detection resistor R3, the size can be easily reduced. Further, by connecting a resistor for suppressing inrush current in parallel to the blocking transistor Q1, the blocking circuit 1 can be used also as the inrush suppression circuit 2.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram at the time of overload according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an overload according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram at the time of overload according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a third embodiment of the present invention.

FIG. 7 is a schematic explanatory diagram of an embodiment of the present invention.

FIG. 8 is an explanatory diagram of a conventional example.

FIG. 9 is an explanatory diagram of a conventional example provided with a cutoff circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 cutoff circuit 2 inrush suppression circuit 3 load 4 DC power supply SW1 power switch Q1 cutoff transistor Q2 first auxiliary transistor Q3 second auxiliary transistor R3 current detection resistor D1, D2 diode ZD1 to ZD4 Zener diode

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (2)

[Claims] 1. A power supply protection circuit comprising: a rush suppression circuit for suppressing a rush current to a load when a power switch is turned on; and a cutoff circuit for cutting a supply current to the load when an overload occurs. A switching transistor that divides a voltage resulting from the switch-on into a gate voltage and that is turned on by the gate voltage to supply a current to the load; a current detection resistor connected in series with the interruption transistor; A first auxiliary transistor that is turned on when a voltage across both ends of the use resistor corresponds to a load current at the time of overload to bypass a gate voltage of the cutoff transistor and turns off the cutoff transistor; A second auxiliary transistor for applying a gate voltage to the first auxiliary transistor so as to continue the ON state by applying a gate voltage when the auxiliary transistor is turned on. Power supply protection circuit comprising the transistor. 2. The power supply protection circuit according to claim 1, wherein a rush current suppressing resistor is connected in parallel with said cutoff transistor.