JP2000224476A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously display plural images by simple constitution at the time of multiplexing each image data so as to display multiple screens on a master screen. SOLUTION: This image processor is provided with a switching device 8 for multiplexing the plural image data in data for one image and a main controller 5 for controlling the switching device 8. In image data demultiplex parts 3 and 4, the multiplexed image data 18 which are the output of the switching device 8 are received and each image data is extracted. Thus, without increasing the number of signal lines such as connection cables, the plural image data are efficiently transmitted and the images are simultaneously displayed on the master screen in synchronism with the scanning screen of master screen signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and in particular, when displaying a plurality of images on a parent screen, displays a plurality of screens simultaneously on the parent screen in synchronization with the scanning screen of the parent screen. The present invention relates to an image processing apparatus having a function of performing

[0002]

2. Description of the Related Art In recent years, various image processing apparatuses for displaying an image on a main screen have been proposed. The following is one of the conventional examples.
As an example, an image superposition apparatus having a configuration for superposing two images described in Japanese Patent Application Laid-Open No. 6-138860 will be described with reference to FIG.

The image superimposing apparatus shown in FIG. 8 has an image memory 801 for storing one image to be superimposed, and digital image data 807 outputted based on scanning in the image memory 801 is stored. , Are converted to analog RGB signals 806 by the D / A converter 802 and input to the selector 805. Also, an analog R obtained by scanning the other image to be superimposed is obtained.
The GB signal 806 is directly input to the selector 805.
Here, it is assumed that the screen scanning of the display device (not shown) or the image memory 801 on which the two analog RGB signals 806 and 808 are based is performed synchronously and in parallel. These two analog RGB signals 806 and 80
8 is selected for each horizontal line by a select signal 811 output in synchronization with a horizontal synchronization signal 810 of a display device (not shown), and is output as a newly superimposed analog RGB signal 812.

The selector memory 803 stores analog RGB signals 8 for each horizontal line of a display device (not shown).
Is a memory for storing 1-bit data for determining whether to select 06 or the analog RGB signal 808. The data of the selector memory 803 is sequentially read out for each horizontal line, An AND condition between this data and the high active horizontal synchronizing signal 810 is given to the selector 805 as the above-described select signal 811.

When the data in the selector memory 803 is “1”, the selector 805 outputs an analog RGB signal 806 as an output analog RGB signal 812. On the other hand, the data in the selector memory 803 is “0”.
, The selector 805 outputs the analog RGB signal 806
As an output analog RGB signal 812. As described above, the bit information in the selector memory 803 is
By being used for the superimposition process of two images, the superimposition process of two images is performed.

Another conventional example is disclosed in Japanese Patent Laid-Open No.
A video signal processing device described in Japanese Patent Application Publication No. 992 will be described with reference to FIG. In FIG. 9, reference numeral 901 denotes Y /
The Y / C separation circuit 901 separates the input NTSC composite signal 909 into a luminance signal 911 and a chrominance signal, and outputs the luminance signal 911 to the switcher 907. Also, the chroma decoder 9
02 receives the color signal separated by the Y / C separation circuit 901 as input, reproduces it as a color difference signal (RY signal 912 and BY signal 913), and
7 is output.

On the other hand, a Y / C separation circuit 903 receives an NTSC composite signal 910 from a source different from the composite signal 909, separates it into a luminance signal and a chrominance signal, and compresses the luminance signal. 905, and outputs a color signal to the chroma decoder 904. The chroma decoder 904 reproduces the input color signals into color difference signals (RY signal and BY signal) and outputs the color difference signals to the compression processing circuit 905.

The compression processing circuit 905 receives the luminance signal and the color difference signal (RY signal and BY signal), thins them out, writes them in the memory 906, and reads them out of the memory 906. , And outputs a luminance signal 914 and a color difference signal (RY signal 915 and BY signal 916) to the switcher 907.

When the main screen is to be displayed, the switcher 907 outputs a luminance signal 911 and an RY signal 91.
2, the BY signal 913 is selected and output to the RGB matrix circuit 908 at the subsequent stage. In the case of an image to be inserted into the parent image, the luminance signal 914 and the RY signal 915, and the
The Y signal 916 is selected and output to the subsequent RGB matrix circuit 908.

That is, the switcher 907 outputs a luminance signal, an RY signal, and a BY signal in which an image has been inserted into the parent screen to the RGB matrix circuit 908. Then, the RGB matrix circuit 908 receives the input luminance signal 917, RY918 signal, and BY signal 919.
, R signal 920 and G signal 921, B signal 92
2 is reproduced and output to the picture tube.

[0011]

The conventional image processing apparatus is configured as described above, and is capable of superimposing and displaying a plurality of images on the main screen. In the conventional image superimposing apparatus, since the superimposition is performed in units of lines, the superimposed images are always displayed side by side. For example, two images are displayed side by side. Screen composition is not possible. In addition, a part of each image is cut off due to the superposition of the images. As described above, the above-described conventional image superposition apparatus realizes a function required for recent multimedia devices, such as displaying an image at an arbitrary position and an arbitrary size. Was not possible.

In the video signal processing apparatus shown as another conventional example, an image to be superimposed on a main screen is obtained by performing overall reduction processing on an image and superimposing the image on the main screen. Although the image is not partly cut off, the number of images that can be superimposed is limited to one.

Further, there is an image processing apparatus in which an image is simultaneously displayed in a main screen in synchronization with a scan screen of the main screen and incorporated in a PC (personal computer) system. This is composed of a graphic board built in a PC. A board for generating image data and a video overlay board for inputting the image data and displaying the image on a parent screen such as a VGA are provided. It has a configuration in which two sheets are provided independently. In this case, it is necessary to transmit the image data to the video overlay board, and the number of signal lines of the connection cable used for that purpose increases in proportion to the number of images, thereby increasing the size of the apparatus and reducing the cost. It becomes a factor of up. Therefore, in such an image processing apparatus, a plurality of image data are efficiently transmitted without increasing the number of signal lines such as connection cables, and an image to be superimposed is displayed on a scanning screen of a main screen signal. Synchronous simultaneous display on the parent screen is required.

The present invention has been made in order to solve the above problems, and multiplexes a plurality of image data without increasing the number of signal lines such as connection cables and transmits the multiplexed information. Transmit without any special addition,
It is an object of the present invention to provide an image processing apparatus capable of simultaneously displaying a plurality of images on a main screen in synchronization with a scanning screen of a main screen signal.

[0015]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: a switch for multiplexing and outputting at least two pieces of image data; and a switch based on the attribute of the image before being multiplexed. The in-line multiplexing method of multiplexing the image data in each line by performing multiplexing by switching in pixel units is used, or the multiplexing by performing switching by a minimum of one line unit divides the image data. A main controller for controlling the switching of the switch so that the multiplexing method between lines is used.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect,
The main controller uses the intra-line multiplexing method when the aspect ratio of the image area having the larger display area is smaller than or equal to the aspect ratio of the image before multiplexing, among the plurality of images. When the aspect ratio of the image area having the larger display area is larger than the aspect ratio of the image before multiplexing, the switching control of the switching unit is performed so that multiplexing is performed using the inter-line multiplexing method. It is like that.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect,
The image processing apparatus further includes an image data separation unit that receives multiplexed image data output from the switching unit as input, and separates and extracts pixels of the plurality of image data from the multiplexed image data.

[0018]

(Embodiment 1) An image processing apparatus according to Embodiment 1 will be described below with reference to FIGS. FIG. 1 is a configuration diagram of an image processing apparatus according to the first embodiment.
And an image data generating unit 2 for generating and outputting an interlaced image signal of NTSC system which is YUV digital data according to CCIR601 standard which is a signal level standard of digital image data. Has a function of A / D converting an analog video signal into a digital signal, while the image data generating unit 2 has a function of decoding an MPEG-compressed video stream.

A switch 8 receives the outputs of the image data generator 1 and the image data generator 2 and selects and outputs one of the data (image data). The switches 3 and 4 are multiplexed. The multiplexed image data 18 receives the output of the image data 18 and the output of the image data generators 1 and 2 respectively.
Is an image data separation unit that extracts only the pixel data of the generated image data. Reference numerals 6 and 7 denote buffer memories for temporarily storing the outputs of the image data separation units 3 and 4, respectively. Reference numerals 9 and 10 denote the buffer memories 6 and 7, respectively.
An image enlargement processing unit for enlarging the read image data, a switch 11 receiving the image data output from the image enlargement processing units 9 and 10 and selecting and outputting one of the image data; Reference numeral 5 denotes a main controller that controls the operation of each unit described above. Reference numeral 12 denotes a D / A converter for converting digital image data output from the switch 11 into analog image data, and 13 denotes a display device for displaying the D / A converted analog signal. It is.

Next, the operation will be described. FIGS. 2 and 3 are diagrams showing the image data output by the image data generation unit 1 and the image data generation unit 2, and the timing relationship between the horizontal synchronization signal, the vertical synchronization signal, and the pixel clock, respectively. Image data generator 1 and image data generator 2
Scans are equally synchronized. This scanning synchronization can be realized by using the synchronization signal generated by the image data generation unit 1 for the image data generation unit 2 to generate the image data 17. When the operation of the image data generation unit 1 is stopped, the image data generation unit 2
A necessary synchronization signal is generated using a clock. In general, the synchronization signal generation of such an image data generation unit can be generated by either external synchronization or internal synchronization, so that the two image data generation units 1 and 2 can easily scan. Equal synchronization can be achieved.

The switching unit 8 generates multiplexed image data 18 by switching the image data 15 and the image data 17 by a switching signal 29 from the main controller 5.

The following describes how the main controller 5 controls the switching unit 8 to multiplex image data. The main controller 5
The switching unit 8 and the switching unit 11 are controlled with reference to the following items (1-1) to (1-4).

(1-1) Aspect ratio of a rectangular area (hereinafter, referred to as a display area A) for displaying an image (hereinafter, referred to as an image A) generated by the image data generating unit 1. (1-2) Area of the display area A. (1-3) An image generated by the image data generation unit 2 (hereinafter, referred to as an image)
A rectangular area for displaying an image B (hereinafter referred to as a display area B)
The aspect ratio). (1-4) Area of display area B

Here, the aspect ratio is a value represented by "length of image in the horizontal direction / length of image in the vertical direction". The main controller 5 controls the switching unit 8 by using the intra-line multiplexing method and the inter-line multiplexing method described in the following (3-1) and (3-2). (2-1) and (2-2).

(2-1) Area of display area A and display area B
When the relationship between the aspect ratio D having the larger display area and the aspect ratio S of the image output from the image data generating unit is D ≦ S, the image A and the image A are compared by the intra-line multiplexing method. The image B is multiplexed. (2-2) If D> S, the image A and the image B are multiplexed by the inter-line multiplexing method.

That is, if the aspect ratio of the larger image area is smaller than or equal to the aspect ratio of the original image data, the intra-line multiplexing method is used.
If the aspect ratio of the larger image area is larger than the aspect ratio of the original image data, the inter-line multiplexing method is used. However, the comparison of the aspect ratio and the calculation of the area are performed by a CPU (central processing unit) or a microcomputer connected to the host bus 36. Hereinafter, the intra-line multiplexing method and the inter-line multiplexing method will be described.

(3-1) Intra-line multiplexing method The intra-line multiplexing method is, as shown in FIG.
And image B for each pixel (in the case of Y data) and 2
This is a method of alternately switching and interleaving multiplexing for each pixel (in the case of UV data). The image data in FIG.
The output of the switching unit 8, “A− *” indicates a pixel of the image A, and “B− *” indicates a pixel of the image B. The reason that UV data is multiplexed every two pixels is that it is necessary to process U data and V data in pairs. The multiplexing by this switching control is performed by the main controller 5 referring to the timing signal 14 or 16 to
The switching is performed for each pixel by the pixel clock in the middle or the pixel clock in the timing signal 16. This switching control is possible because the scans of the image data generation unit 1 and the image data generation unit 2 are equally synchronized as described above. The switching device 8
Can be easily configured by using a low-cost bus switch whose switching time is, for example, 5 ns or less. In addition, the propagation delay due to this switching operation does not hinder the operation of other processing systems of the present apparatus, for example, the image data separation unit 3 in practice. Further, the switching circuit can be easily realized by using the pixel clock output from the image data generation unit 1 or the pixel clock output from the image data generation unit 2.

(3-2) Inter-Line Multiplexing Method The inter-line multiplexing method is a method in which image data of image A and image data of image B are alternately switched line by line and interleaved. FIG. 6 shows the switching time for the horizontal synchronizing signal. During the period “A”, the pixel data of the image A becomes the output (image data 18) of the switch 8 and during the period “B”, The pixel data of B becomes the output (image data 18) of the switch 8.
The multiplexing by the switching control is performed by the main controller 5 referring to the timing signal 14 or the timing signal 16 and using the horizontal synchronization signal in the timing signal 14 or the pulse of the horizontal synchronization signal in the timing signal 16.
This is performed by switching every line. This switching control is possible because the scanning of the image data generating unit 1 and the scanning of the image data generating unit 2 are equally synchronized as described above. Further, the switching circuit can be easily realized by using the horizontal synchronization signal output from the image data generation unit 1 or the horizontal synchronization signal output from the image data generation unit 2, and has a configuration in which switching is performed for each pulse.

The switching unit 8 can be easily configured by using a low-cost multiplex-type bus switch whose switching time is, for example, 5 nsec or less. The propagation delay is practically caused by another processing system, for example, the image data separation unit 3
It does not hinder the operation of such as. Since the output of the switch 8 is input to the image data separation unit 3 and the image data separation unit 4, for example, when the operation of the image data generation unit 2 is stopped, the output of the image data generation unit 1 is stopped. The image data 15 can be sent to two separation units, the image data separation unit 3 and the image data separation unit 4, and the same image can be displayed on two screens.

The image data separating unit 3 receives the multiplexed image data 18 output from the switching unit 8 and outputs image data 15 (image A) generated by the image data generating unit 1 from the image data 18. Is extracted using the control signal 21 including the same signal as the switching signal 29. By this extraction, the input image data 18
Is an intra-line multiplexed image, the horizontal size of the image A is reduced to half. On the other hand, if the input image data 18 is inter-line multiplexed, the vertical size of the image A is half. The image has been reduced. In addition,
Assuming that the number of pixels in the area displaying the image A is horizontal XA and vertical YA, if XA or YA is smaller than the above-mentioned extracted image size, further reduction processing is generally performed by pixel thinning or line thinning. Will be performed.

That is, the image data separating section 4 receives the multiplexed image data 18 output from the switch 8 and outputs the image data 17 (image B) generated by the image data generating section 2 from the image data 18. ), The control signal 2 including the same signal as the switching signal 29
Extract using 2. As a result of this extraction, when the input image data 18 is intra-line multiplexed, the image A is an image whose horizontal size has been reduced by half, and when the input image data 18 is inter-line multiplexed, The image A is an image whose vertical size has been reduced by half.
Here, the number of pixels in the area for displaying the image B is represented by XB in the horizontal direction and Y
Assuming B, if XB or YB is smaller than the extracted image size, further reduction processing is performed by pixel thinning or line thinning which is generally performed.

The buffer memory 6 is composed of a frame memory having an input terminal for inputting image data 19 and an output terminal for outputting image data written in the memory. It is arranged in a rectangular shape indicated by a value, and can sufficiently store image data for one frame. Further, the writing operation and the reading operation of the image data in the buffer memory 6 are as follows.
These operations are performed asynchronously and controlled by the main controller 5. When the image data is output from the buffer memory 6, the image data for one line to be read is issued from the control signal 23 by a transfer command, and the image data for one line to be read is transferred to the static memory called SAM inside the buffer memory 6. Thereafter, by sending a read clock, the image data can be easily extracted sequentially from the SAM. The reading of the image data by issuing the transfer command is synchronized with the screen scanning of the external synchronization signal 33, and does not prevent the writing operation of the image data.

The buffer memory 7 is composed of a frame memory having an input terminal for inputting image data 20 and an output terminal for outputting image data written in the memory. It is arranged in a rectangular shape indicated by a value, and can sufficiently store image data for one frame. Further, the writing operation and the reading operation of the image data to the buffer memory 7 are as follows.
These operations are performed asynchronously and controlled by the main controller 5. When the image data is output from the buffer memory 7, the image data for one line to be read is issued from the control signal 24 by the transfer command, and the image data for one line to be read is transferred to the static memory called SAM inside the buffer memory 7. Thereafter, the image data can be easily sequentially extracted from the SAM by sending the read clock. The reading of the image data by issuing the transfer command is synchronized with the screen scanning of the external synchronization signal 33 and does not prevent the writing operation of the image data.

The image enlargement processing section 9 enlarges the input image, enlarges the image data 25 sent from the buffer memory 6 according to an instruction from the main controller 5, and outputs it to the switch 11. . When displaying the image in the buffer memory 6 within the scan screen of the main screen signal 33, the main controller 5 transfers the image data in the buffer memory 6 immediately before the display time in synchronization with the main screen signal 33. Send instructions. When receiving the transfer command, the buffer memory 6 converts the image data in the memory into an image enlargement processing unit 9.
Output to If the number XA of display area pixels and the number YA of display area pixels are larger than the image size input to the image enlargement processing section 9, the image enlargement processing section 9 performs pixel interpolation and line processing generally performed. Enlargement processing is performed by interpolation or the like and output to the switch 11.

The image enlargement processing section 10 enlarges an input image. The image enlargement processing section 10 enlarges the image data 26 sent from the buffer memory 7 in accordance with an instruction from the main controller 5, and performs an enlargement process. Output to
When displaying the image in the buffer memory 7 within the scan screen of the main screen signal 33, the main controller 5 transfers the image data in the buffer memory 7 immediately before the time of displaying the image data in the buffer memory 7 in synchronization with the main screen signal 33. Send instructions. Upon receiving the transfer command, the buffer memory 7 outputs the image data in the memory to the image enlargement processing unit 10. Image enlargement processing unit 10
Are the number of display area pixels XB and the number of display area pixels YB
Is larger than the image size input to the image enlargement processing unit 10, enlargement processing is performed by pixel interpolation, line interpolation, or the like, which is generally performed, and output to the switch 11.
The main controller 5 controls the switch 11 with reference to the following parameter groups (4-1) to (4-6).

(4-1) Position of Display Area for Image A (Relative Position with respect to Main Screen Signal 33) (4-2) Horizontal Size of Display Area for Image A (4-3) Display Area for Image A Vertical size (4-4) Position of display area for image B (relative position to parent screen signal 33) (4-5) Horizontal size of display area for image B (4-6) Display area for image B The parameter group is provided in the main controller 5 as a register, and is set by a CPU, a microcomputer, or the like via the host bus 36. FIG. 4 shows the timing relationship between the horizontal synchronizing signal, the vertical synchronizing signal, and the pixel clock, which are non-interlaced parent screen signals 33. The size of the image scanned by the main screen signal 33 is
The screen size is 800 pixels per line, 525 lines per frame, and 59.94 frames per second.

The time required for a series of processes from the issuance of a transfer instruction by the memory controller 5, the output of image data by the buffer memory, and the D / A conversion by the D / A converter is performed by, for example, a general video processor. The time required for a series of processes, which is achieved by performing the process, is described in parameters (5-1) and (5-4).
This is avoided by using a value obtained by subtracting the value of the horizontal position of the display area set in (1) by the delay time required for the processing.

As described above, the main controller 5
Is image data 34 obtained by combining two interlaced images on one non-interlaced parent screen.
Is generated using a clock having the same frequency synchronized with the pixel clock of the main screen signal 33 and having the same frequency.
Send to

Then, the D / A conversion section 12 D / A converts the digital YUV format image data input from the switch 11 into analog RGB signals, and sends the analog RGB signals to a display device 13 such as a VGA display. Display device 13
Displays a non-interlaced analog RGB signal and presents it to the viewer.

FIG. 7 shows an example in which two images are simultaneously displayed on the scanning screen of the parent screen 33. In FIG. 7, the aspect ratio of the image B before multiplexing is 858/525,
The area of the display area for image B (500 × 500 pixels) is larger than the area of the display area for image A (200 × 300 pixels), and the aspect ratio D of the display area for image B (500/5)
00) is the aspect ratio S (858) of the image B before multiplexing.
/ 525) (D <S), an intra-line multiplexing method is adopted and multi-screen display is performed.

As described above, according to the present embodiment, the two images are multiplexed into the data of one image using the switch 8 and output, and the multiplexed images are multiplexed in the image data separation units 3 and 4. Only the pixel data of each image data is separated / extracted from the image data 18, and the separated / extracted images are enlarged in the image enlargement processing units 9, 10. Multiplexed multiple image data and added the multiplexed information without increasing the number of signal lines such as connection cables. In addition, the image can be transmitted, and a plurality of images can be simultaneously displayed on the main screen in synchronization with the scanning screen of the main screen signal.

In the above embodiment, the image input to the switching unit 8 has been described by taking the NTSC image as an example. However, the configuration may be such that a non-interlace image is input. . In the above embodiment, the aspect ratio S used when selecting the multiplexing method is the aspect ratio of the original image data of the image output from the image data generating units 1 and 2. An aspect ratio of an image or the like obtained by cutting off image data during the ranking period may be used.

Further, in the above embodiment, the multiplexing method is determined based on the magnitude relationship between the aspect ratio of the display area having the larger display area and the aspect ratio of the image data output by the image data generator. In the main controller 5, the switching unit 8 is set under the same conditions according to a specific method set in advance.
May be controlled.

Further, in the above embodiment, in the intra-line multiplexing method, two image data are one in which the Y signal data is one.
Although an example in which the UV signal data is multiplexed every pixel and the UV signal data is multiplexed every two pixels is shown, the method of the intra-line multiplexing method is not limited to this. For example, two image data in one line are In order to use a multiplexing method, multiplexing may be performed every M pixels (M = 1, 2, 3,...).

In the above-described embodiment, an example has been shown in which two image data are multiplexed for each line in the inter-line multiplexing method. Every N lines (N = 1,
2, 3,. . . ) May be multiplexed.

In the above embodiment, the case where the number of image data to be multiplexed is two has been described. However, the operation of the main controller 5 is changed to multiplex three or more pieces of image data. The present invention can also be applied to

[0047]

As described above, according to the image processing apparatus of the first aspect of the present invention, a switch for multiplexing and outputting at least two pieces of image data and an attribute of the image before being multiplexed are provided. Multiplexing by switching on a pixel-by-pixel basis is used to multiplex the image data in each line.
A main controller that controls the switching of the switch is provided so that an inter-line multiplexing method that multiplexes the image data by performing multiplexing by switching in line units is used. There is an effect that a plurality of image data can be transmitted efficiently without increasing the number of signal lines, and images can be simultaneously displayed on the main screen in synchronization with the scanning screen of the main screen signal.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the main controller includes a plurality of images among the plurality of images.
If the aspect ratio of the image area with the larger display area is smaller than or equal to the aspect ratio of the image before multiplexing, the above-described in-line multiplexing method is used, while the aspect ratio of the image area with the larger display area is used. Is larger than the aspect ratio of the image before multiplexing, the switching control of the switch is performed so that multiplexing is performed using the inter-line multiplexing method. There is an effect that an image can be displayed simultaneously in an appropriate size.

According to a third aspect of the present invention, in the image processing apparatus according to the first aspect,
Since the multiplexed image data that is the output of the switch is input, the image data separation unit that separates and extracts the pixels of the plurality of image data from the multiplexed image data is provided. The pixels of each image data can be separated and extracted from the multiplexed image data with a simple configuration, and there is an effect that the configuration of the apparatus can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing relationship among YUV image data, an input clock, and a horizontal synchronization signal.

FIG. 3 is a diagram showing a timing relationship between a horizontal synchronization signal and a vertical synchronization signal.

FIG. 4 is a diagram illustrating a relationship between an image clock for scanning a main screen, a horizontal synchronization signal, and a vertical synchronization signal.

FIG. 5 is a timing chart for explaining an intra-line multiplexing method.

FIG. 6 is a timing chart for explaining an inter-line multiplexing method.

FIG. 7 is a schematic diagram showing a state in which two interlaced images are simultaneously displayed on a non-interlaced parent surface (one frame).

FIG. 8 is a configuration diagram for explaining a conventional image display device having an image superimposing function.

FIG. 9 is a configuration diagram for explaining another conventional video signal processing device having an image superimposing function.

[Explanation of symbols]

1, 2 image data generation unit 3, 4 image data separation unit 5 main controller 6, 7 buffer memory 8, 11 switch unit 9, 10 image enlargement processing unit 12 D / A conversion unit 13 display device 14 horizontal synchronization signal and vertical synchronization Signal, timing signal having pixel clock 15 image data A 16 horizontal synchronization signal and vertical synchronization signal, timing signal having pixel clock 17 image data B 18 multiplexed image data 19 separated and extracted image data A 20 separated and extracted Image data B 21 control signal for image data separating unit 3 22 control signal for image data separating unit 4 23 control signal for buffer memory 6 control signal for buffer memory 7 25 image data output from buffer memory 6 26 buffer memory 7 Output image data 27 Control for image enlargement processing unit 9 Control signal 28 Control signal for image enlargement processing unit 10 29 Switching signal for switch 8 30 Switching signal for switch 11 31 Enlarged image data 32 Enlarged image data 33 Horizontal synchronization signal, vertical synchronization signal, display clock Main screen signal having 34 image data and pixel clock, 35 analog RGB signal 36 host bus 801 image memory 802 D / A converter 803 memory for selector 804 AND circuit 805 selector 806 analog RGB signal 807 digital image data 808 analog RGB signal 809 selector data 810 Horizontal synchronization signal 811 Selector signal 812 Analog RGB signal 901 Y / C separation circuit 902 Chroma decoder 903 Y / C separation circuit 904 Chroma decoder 905 Compression circuit 906 Moly 907 Switcher 908 RGB matrix 909 Composite signal 910 Composite signal 911 Luminance signal 912 RY signal 913 BY signal 914 Luminance signal 915 RY signal 916 BY signal 917 Luminance signal 918 RY signal 919 BY signal

Claims (3)

[Claims] A switching unit that multiplexes and outputs at least two pieces of image data; and performs multiplexing by switching on a pixel basis based on an attribute of an image before being multiplexed, so that the multiplexing is performed within each line. The switching unit is switched so that an intra-line multiplexing method for multiplexing image data is used or an inter-line multiplexing method for multiplexing the image data by performing multiplexing by switching at least in units of one line. An image processing apparatus, comprising: a main controller that performs control. 2. The image processing apparatus according to claim 1, wherein the main controller determines whether an aspect ratio of an image region having a larger display area among the plurality of images is smaller than an aspect ratio of an image before multiplexing. If they are equal to each other, the above-described intra-line multiplexing method is used. On the other hand, if the aspect ratio of the image area having a larger display area is larger than the aspect ratio of the image before multiplexing, multiplexing is performed using the above-described inter-line multiplexing method. An image processing apparatus, comprising: performing switching control of the switching device so that the switching is performed. 3. The image processing apparatus according to claim 1, wherein multiplexed image data output from the switch is input, and pixels of the plurality of image data are respectively extracted from the multiplexed image data. An image processing apparatus, comprising: an image data separating unit for separating and extracting.