JP2000224443A - Noise reduction device, noise reduction method and recording medium recorded with noise reduction program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise reduction device capable of reducing noise components while reflecting the slight change on output video signals even in the case that video signals slightly changed between frames. SOLUTION: A multiplier A multiplies input video signals 101 for every pixel by (1-K) and outputs them to an adder 102. The multiplier B multiplies the corresponding output video signals of one frame before outputted from a frame memory 105 by K and outputs them to the adder 102. The frame memory 105 stores the output video signals 106 for every frame and outputs the output video signals of one frame before corresponding to the input video signals 101 to the multiplier B. A rounding processor 103 rounds up the decimal places of the video signals outputted from the adder 102 and outputs them as the output video signals 106. A round-down processor 104 rounds down the decimal places of the video signals outputted from the adder 102 and outputs them to the frame memory 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal noise reduction apparatus, and more particularly, to a digital video signal noise reduction apparatus using a frame memory and a recursive filter, a noise reduction method, and a recording medium on which a noise reduction program is recorded. .

[0002]

2. Description of the Related Art In general, a noise component included in a video signal of a video captured by a surveillance camera, a home camera, or the like is high-frequency so-called triangular noise, and exists near a color subcarrier frequency. If this noise component is not removed before A / D conversion, it remains as a digital video signal as it is, resulting in image degradation.

[0003] In addition, since the video signal is a signal obtained by capturing a video to be captured every frame period of several tens of milliseconds, its signal component has strong correlation between frames. On the other hand, noise components included in video signals are often mixed irregularly into video signals, and there is a tendency that this correlation hardly exists. For this reason, when the video signal is temporally averaged for each frame period, only the noise component can be reduced. On the other hand,
When a video signal is temporally averaged for each frame period in a moving image, a noise component is reduced, but a so-called afterimage phenomenon occurs. Therefore, a noise reduction device for reducing a noise component included in a video signal needs to balance the conflicting phenomena of reducing the noise component and avoiding the afterimage phenomenon.

[0004] Many systems have been proposed for such a noise reduction device utilizing the frame correlation of a video signal.
l.33 No. 4 (1979) PP40-44 ". FIG.
It is a schematic block diagram of the conventional noise reduction device 800.
The apparatus 800 combines the input video signal 801 for each pixel and the output video signal of one frame before output from the frame memory 804 corresponding thereto at a ratio of 1: 1 and rounds off the decimal part to output video signal. Output as signal 805. Note that the input video signal 801 in this case is, for example, N
An 8-bit luminance signal of the TSC system is used.

The multiplier A in the conventional noise reduction device 800 multiplies the input video signal 801 for each pixel by (1−K) and outputs the result to the adder 802. Also, the multiplier B multiplies the output video signal stored in the frame memory 804 for the corresponding pixel one frame before by K, and outputs the multiplied image signal to the adder 802. The frame memory 804 delays the output video signal 805 related to the corresponding pixel by one frame, and
Output to

Here, the coefficient K has a range of 0 <K <1 and is a coefficient for determining a ratio of two input video signals when forming a video signal output from the adder 802. is there. More specifically, the coefficient K is obtained by dividing the input video signal 801 input to the multiplier A and the corresponding output video signal one frame before input to the multiplier B by (1-K) versus K Is a coefficient for synthesizing at a ratio of In general, this coefficient K is determined to be a large value so that the ratio of the output video signal one frame before increases in the case of a still image or an image with a small motion, and in the case of an image with a large motion, the input video signal 801 Is determined to be a small value so that the ratio of (1) becomes large (that is, the ratio of the output video signal one frame before becomes small). For convenience of explanation, it is assumed that the value of the coefficient K in the present apparatus 800 is set to 0.5.

[0007] The adder 802 combines the video signals output from the multipliers A and B and outputs them to the rounding processor 803. The rounding processor 803 performs “rounding processing” on the video signal output from the adder 802, and outputs the result as an output video signal 805. Here, the “rounding process” is a method of quantizing digital data.
For example, a process corresponding to rounding in a decimal number, a process corresponding to rounding up, etc. correspond to data after a decimal point. Note that the rounding device 80 in the apparatus 800
In 3, it is assumed that a process corresponding to rounding in decimal notation is performed on data after the decimal point.

As described above, the conventional noise reduction device 800
Is used, it is possible to reduce noise components having no correlation between frames included in the input video signal.

[0009]

By the way, the conventional noise reduction device 800 has a problem that, when the input video signal changes minutely between frames, the small change cannot be reflected on the output video signal. This problem will be specifically described with reference to FIG. 9 and Table 1.

FIGS. 9A and 9B are views showing the state of the ball before and after hitting the wall for 2/30 seconds. In FIG. 9A, the ball 901 at the position P is 1/30
It shows a state of hitting the wall 902 after 1 second and returning to the original position P after 1/30 second (note that deformation of the ball due to hitting the wall is not considered). FIG.
In (a), the brightness distribution of the ball 901 is shown concentrically, with the brightest central portion corresponding to a luminance value of 128, and the peripheral portions becoming darker one by one in the following order.

Attention is paid to the luminance value of the pixel i. When the ball 901 is at the position P, the luminance value of the pixel i is 127. When the ball 901 moves to the position Q, the luminance value is Changes to 128. Further, when returning to the original position P, the luminance value is considered to be 127. However, when the image is displayed on the screen based on the output video signal 805 in which the noise is reduced by using the noise reduction device 800, as shown in FIG. 9B, the brightness of the ball 901 to be concentric is determined. The distribution is distorted. This means that an error has occurred in the luminance value of the pixel i. The reason for this error will be described with reference to Table 1.

[0012]

[Table 1]

Table 1 shows the noise reduction when the noise reduction device 800 is applied to the input video signal 801 related to the pixel i when the state of the ball 901 before and after hitting the wall 902 is photographed in FIG. 9 is a table showing output values of each unit in the device 800. N frames to N in Table 1
The relationship between the +2 frame and the position of the ball 901 in FIG. 9 is such that the N frame corresponds to the image at the first position P,
This corresponds to the image at the position Q at the moment when the N + 1 frame hits the wall 902, and corresponds to the image at the moment when the N + 2 frame bounces back to the original position P.

As shown in Table 1, assuming that the luminance value of the input video signal 801 relating to the pixel i in the N frame is 127, the luminance value of the output video signal 805 is 127.
Next, the luminance value of the input video signal 801 relating to the pixel i in the N + 1 frame becomes 128 because the ball 901 has moved to the position Q, and the luminance value of the output video signal 805 is also 12
It becomes 8. Further, in the N + 2 frame, the ball 901
Is returned to the position P, the luminance value of the input video signal 801 for the pixel i should be 127, and the luminance value of the output video signal 805 should also be 127. However, as shown in Table 1, by using the conventional noise reduction device 800, the output video signal 805 related to the pixel i of the N + 2 frame is obtained.
Of the luminance value of 127.
5 is rounded off to 128.

As described above, the conventional noise reduction device 800
In this case, even if the input video signal 801 has a slight change between the previous and next frames, the small change is detected by the rounding processor 8.
03 is rounded, and a minute change cannot be reflected on the output video signal. Therefore, the present invention has been made in view of the above problems, and even when the video signal changes slightly between frames, while reflecting a signal component related to the minute change in the output video signal, An object of the present invention is to provide a noise reduction device capable of reducing a noise component.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is an apparatus for reducing noise contained in a moving image represented by a continuous frame, comprising: N-bit pixel value and 1
Synthesizing means for synthesizing a pixel value consisting of n bits relating to a corresponding pixel before a frame, first means for performing processing of discarding a predetermined lower-order bit with respect to the pixel value after synthesis, and On the other hand, there is provided a second means for rounding up a predetermined lower-order bit, and a delay means for delaying a pixel value which has undergone one of the first means and the second means by one frame. The first means or the second means is input to the means as a pixel value related to the corresponding pixel one frame before, and outputs the pixel value subjected to the other processing of the first means or the second means as a noise-reduced pixel value from the other means. I do.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a noise reduction device according to the present invention will be described with reference to the drawings. Embodiment 1 FIG. 1 is a schematic block diagram of a display device 20 including a noise reduction device 100. As shown in FIG. 1, the display device 20 is a device that receives a signal 11 from, for example, the surveillance camera 10 and displays it on a screen based on the signal. Here, the signal 11 is a digital signal and includes a digital video signal, a control code, and the like.

The display device 20 includes a signal separation unit 21, a frame synchronization control unit 22, a signal synthesis unit 23, and a noise reduction device 100. The display device 20 shown in FIG.
In the above configuration, a configuration irrelevant to the noise reduction device 100 is omitted. The signal separation unit 21 extracts a control code from the signal 11 received from the monitoring camera 10 and outputs the extracted control code to the frame synchronization control unit 22. In addition, the signal separation unit 21 extracts an effective pixel signal identification code (hereinafter, referred to as an “identification code”) from the extracted control code.
Is determined.

Here, the "control code" refers to various control codes included in the signal 11, and corresponds to a vertical synchronization code, a horizontal synchronization code, an identification code, and the like. In this case, it is assumed that either the vertical synchronization code or the horizontal synchronization code includes information indicating the head of the first field in the frame. The “identification code” refers to a code used to extract an input video signal input to the device 100.

Further, the signal separating section 21 separates a video signal to be output to the noise reduction apparatus 100 from other video signals based on the determined identification code. The video signal output to the noise reduction device 100 in this case is a video signal related to a pixel of a portion that is effectively displayed to the user, for example, a video signal related to 490 × 720 pixels. These “490 × 720 pixels” are NTSC
Of the 525 scanning lines in the scanning method,
This means the product of the number of scanning lines and 720 pixels, which are effective pixels, out of 858 pixels per scanning line. In the present embodiment, it is assumed that a video signal related to an effective pixel exists between two identification codes.

FIG. 2 is a diagram showing the number of pixels in a portion effectively displayed to the user. As shown in FIG. 2, 490 scanning lines in a portion 202 that is effectively displayed to the user in a screen 201 of one frame,
The number of pixels per scanning line is 720. As described above, the signal separation unit 21 determines the identification code, and extracts the video signal existing between the identification codes, thereby separating the video signal output to the noise reduction device 100 from the other video signals. .

The frame synchronization control unit 22 includes the signal separation unit 2
1 is used as it is by the signal combining unit 23.
At the same time, and identifies whether the control code is a vertical synchronization code, a horizontal synchronization code, an identification code, or the like. Further, when detecting the information indicating the head of the first field from the identified vertical synchronization code or horizontal synchronization code, the frame synchronization control unit 22 outputs the switching control code to the frame memory of the noise reduction device 100. The “switch control code” will be described later.

The signal synthesizing section 23 includes a noise reduction device 100
And the control code output from the frame synchronization control unit 22 to generate a signal 24. The “signal 24” is a signal having the same form as the signal 11, and is a signal after the noise component of the signal 11 is reduced. Next, the noise reduction device 10 according to the present embodiment
0 will be described.

FIG. 3 is a functional block diagram of the noise reduction device 100. The noise reduction device 100 includes a multiplier A, a multiplier B, an adder 102, a rounding processor 103, a truncation processor 104, and a frame memory 105. Characteristic parts of the apparatus 100 are a rounding processor 103 and a truncation processor 104. For convenience of description, the “video signal” in the following refers to a luminance signal. In particular, the input video signal 101 and the output video signal 106
Is composed of 8 bits.

The multiplier A receives the input video signal 101 corresponding to each pixel, multiplies the input video signal 101 by (1-K), and adds the input video signal 101 to the adder 10.
Output to 2. The multiplier B receives the output video signal of the previous frame related to the pixel corresponding to the input video signal 101 output from the frame memory 105, multiplies the output video signal by K, and outputs it to the adder 102. The value of the coefficient K in the multiplier A and the multiplier B is in a range of (0 <K <1). The adder 102 adds the video signals output from each of the multipliers A and B, and outputs the sum to the rounding processor 103 and the truncation processing unit 104.

The frame memory 105 has a storage area for video signals for two frames inside, and the truncation processor 10
The video signal output from the storage unit 4 is stored in a frame unit by selecting a storage area of any one of the frames. Further, the frame memory 105 sets the multiplier B so as to match the input timing of the input video signal 101 received by the multiplier A.
The video signal of one frame before corresponding to the input video signal is output.

Here, regarding the configuration of the frame memory 105, refer to FIG. 4 including the control of switching the storage area when receiving the video signal output from the truncation processor 104 and when outputting the video signal to the multiplier B. This will be described in more detail. FIG. 4 is a detailed functional block diagram of the frame memory 105. As shown in FIG. 4, the frame memory 105 includes an input control unit 111, a first storage unit 112, a second storage unit 113, and an output control unit 114.

The input control unit 111 controls the truncation processor 10
4 is output to the first storage unit 112 for each pixel.
Alternatively, switching control is performed on which of the second storage units 113 is stored. At this time, each time the input control unit 111 detects the switching control code output from the frame synchronization control unit 22, the input control unit 111 stores the storage destination of the video signal in the first storage unit 112 or the second storage unit 112.
Switching is performed alternately so as to become the storage unit 113. When the first switching control code is detected, the input control unit 111
Controls the video signal to be stored in the first storage unit 112.

Here, the "switching control code" is a code that the frame synchronization control unit 22 outputs to the input control unit 111 and the output control unit 114 of the frame memory 105. Storage unit 112
This is a code for switching between and the second storage unit 113. Further, as described above, when the frame synchronization control unit 22 detects information indicating the beginning of the first field from the vertical synchronization code or the horizontal synchronization code received from the signal separation unit 21 as described above, the frame synchronization This is a code output from the control unit 22.

The first storage unit 112 stores the frame memory 10
5 is a storage area for one frame of a storage area for video signals for two frames, and stores video signals output from the truncation processor 104 in the order of reception when selected by the switching control of the input control unit 111. . The second storage unit 113 is a storage area for the remaining one frame of the storage area of the video signal for two frames in the frame memory 105, and is rounded down when selected by the switching control of the input control unit 111. The video signals output from the processor 104 are stored in the order of reception.

The output control unit 114 reads a video signal related to a corresponding pixel in the next frame from the video signal stored in the first storage unit 112 or the second storage unit 113 and outputs the read video signal to the multiplier B. At this time, the output control unit 114
Are stored in the first storage unit 112 and the second storage unit 113 based on the switching control code output from the frame synchronization control unit 22.
, And outputs the video signal to the multiplier B.
When detecting the first switching control code, the output control unit 114 reads the video signal from the second storage unit 112 and outputs the video signal to the multiplier B.

As described above, in the frame memory 105, based on the switching control code output from the frame synchronization control unit 22, the storage of the video signal output from the truncation processor 104 and the correspondence to the input video signal 101 The video signal one frame before is output. The rounding processor 103 receives the video signal output from the adder 102, performs a process of rounding up the decimal portion, and outputs the result as an output video signal 106. For example, when a video signal “127.5” in decimal notation is received from the adder 102, a process of rounding up the decimal point is performed and “17.5”
28 ".

The truncation processor 104 receives the video signal output from the adder 102, performs a process of truncating the decimal part, and outputs the result to the frame memory 105. For example, when a video signal “127.5” in decimal notation is received from the adder 102, a process of rounding down the decimal point is performed, and the video signal “127” is output to the frame memory 105.

Next, how the input video signal 101 is processed in the apparatus 100 will be described with reference to FIG. FIG. 5 is a diagram illustrating a video signal in each unit of the noise reduction device 100. FIG. 5 mainly shows video signals output from the respective units when the input video signal 101 is input to the multiplier A. It is assumed that the input video signal 101 is output to the multiplier A at a timing corresponding to the clock signal (CLK) in FIG.

First, the multiplier A takes in the video signal of the first pixel at the timing of time T1, multiplies it by (1-K),
The video signal S2 is output at time T2. The video signal S2 in this case is a video signal including a value below the decimal point. Further, the multiplier B takes in the video signal S1 output from the frame memory 105 at the timing of the time T1, multiplies it by K, and outputs the video signal S3 at the time T2.

Thus, the adder 102 takes in the video signals S2 and S3 output from the multipliers A and B at the timing of the time T2, adds these two video signals, and adds the two video signals to the video signal S4 at the time T3. Is output. Further, the rounding processor 103 takes in the video signal S4 output from the adder 102 at the timing of time T3, performs rounding processing, that is, rounds up, and performs video signal S5 (ie, the output video signal 106) at the timing of time T4. ) Is output. on the other hand,
The truncation processor 104 similarly takes in the video signal S4 output from the adder 102 at the timing of time T3, performs a truncation process, and outputs the video signal S6 at the timing of time T4.

Further, the frame memory 105 stores the time T
The video signal S6 output from the truncation processor 104 at the timing of 4 is fetched and stored in the first storage unit 112. When a video signal related to the first pixel of the second frame is input as the input video signal 101, the frame memory 105 converts the video signal S7 (that is, the video signal S8) captured at the time T4 into a time. Output to the multiplier B at the timing of TN + 1. Here, “N” is the number of clocks required for noise reduction processing of a video signal relating to valid 490 × 720 pixels in one frame.

The timing of the switching control code output from the frame synchronization control unit 22 is also shown in FIG. In FIG. 5, information indicating the head of the first field is included in the vertical synchronization code, and the frame synchronization control unit 22 detects this information at time Ta,
The example in which the switching control code is output at the time Tb is shown. Note that the same processing as described above is performed on the video signals related to the other pixels. In FIG. 5, the vertical synchronization code, the horizontal synchronization code, and the identification code are signals that are not output to the multiplier A, and are therefore shown in parentheses.

Next, the operation of the noise reduction device 100 will be described with reference to Tables 2 to 4.

[0040]

[Table 2]

Table 2 is a table summarizing the values of the video signal of each unit in the noise reduction device 100 when the input video signal 101 is input. In Table 2, N frames to N + 4
The case where the present apparatus 100 is applied to the input video signal 101 of five frames is shown. In Table 2, the value of the coefficient K is set to 0.5. Table 2 shows that even if the input video signal 1
It can be seen that even if 01 changes minutely alternately like "127" and "128", this minute change can be directly reflected in the output video signal 106. This is because the effect of the video signal one frame before is reduced by truncating the decimal part in the truncation processing unit 104, and the minuteness of the newly input video signal is smaller than the processing of rounding up the decimal part in the rounding processing unit 103. It is because they make the most of change.

[0042]

[Table 3]

Table 3 is a table summarizing the values of the video signal of each part when the value of the coefficient K in the noise reduction device 100 is set to 0.1. Table 3 also shows that, similarly to Table 2, a minute change in the input video signal 101 can be directly reflected on the output video signal 106.

[0044]

[Table 4]

Table 4 is a table summarizing the values of the video signal of each part when the value of the coefficient K in the noise reduction device 100 is set to 0.9. Also in Table 4, Table 2
It is shown that a minute change in the input video signal 101 can be directly reflected on the output video signal 106 in the same manner as in FIG. As described above, by using the noise reduction device 100 according to the present embodiment, even when the input video signal 101 slightly changes, the noise is reflected while reflecting the small change of the input video signal in the output video signal. Can be reduced. (Embodiment 2) The noise reduction device of this embodiment is different from the noise reduction device 100 of Embodiment 1 in that a rounding processor and a truncation processor are replaced. Hereinafter, the points different from the first embodiment will be mainly described.

FIG. 6 is a functional block diagram of the noise reduction device 600 according to the second embodiment. Noise reduction device 60
0 is less than the noise reduction device 100 and the rounding processor 103
And a rounding processor 602 in place of the truncation processor 104. The output video signal 106 is output from the rounding processor 1
The difference is that the data is output from the truncation processing 601 instead of the data from 03.

The rounding processor 103 and the rounding processor 60
2 has the same rounding function, and the truncation processing unit 104 and the truncation processing unit 601 have the same truncation processing function. Next, the operation of the noise reduction device 600 will be described with reference to Tables 5 to 7. The contents of Tables 5 to 7 will be described focusing on the differences while comparing them with the contents of Tables 2 to 4 in the first embodiment.

[0048]

[Table 5]

Table 5 is a table summarizing the values of the video signal of each unit in the noise reduction device 600 when the input video signal 101 is input. In Table 5, as in Table 2,
The value of the coefficient K is set to 0.5. Also in Table 5,
As in the case of the noise reduction device 100, even if the input video signal 101 changes minutely alternately, such as "127" and "128", this small change can be directly reflected in the output video signal 106. I understand. This is because the rounding processor 602 rounds up the decimal point and thereby inputs a large amount of the effect of the video signal one frame before, and the truncation processing unit 601 rounds off the decimal point and cancels the effect one frame before. This is because a minute change in the newly input video signal is extracted.

[0050]

[Table 6]

Table 6 is a table summarizing the values of the video signal of each part when the value of the coefficient K in the noise reduction device 600 is set to 0.1. Table 6 also shows that, similarly to Table 5, a minute change in the input video signal 101 can be directly reflected on the output video signal 106.

[0052]

[Table 7]

Table 7 is a table summarizing the values of the video signal of each part when the value of the coefficient K in the noise reduction device 600 is set to 0.9. Also in Table 7, Table 5
It is shown that a minute change in the input video signal 101 can be directly reflected on the output video signal 106 in the same manner as in FIG. As described above, the noise reduction device 600 according to the second embodiment
As described above, even when the input video signal 101 slightly changes, the noise is reduced while reflecting the small change of the input video signal in the output video signal, similarly to the noise reduction device 100 described above. be able to.

In the above embodiment, an 8-bit luminance signal is exemplified as an input video signal, but the present invention is not limited to an 8-bit luminance signal. Further, the input video signal may be a color difference signal or the like. In the above embodiment,
Although either the vertical synchronization code or the horizontal synchronization code includes information indicating the start of the first field in each frame, the 1 or 2 fields are included in either the vertical synchronization code or the horizontal synchronization code. May be included, and the above-described switching control may be performed when the first field is first determined.

In the above embodiment, the noise reduction device has a hardware configuration. However, the noise reduction device can be configured by software. FIG.
It is a flowchart which shows the flow of a noise reduction process as such an example. In the flowchart of FIG. 7, the multiplier A, the multiplier B, the adder 102, the rounding processor 103, and the truncation processing unit 104 use the numbers used in the above-described embodiment. Can be realized by software, and this is obvious to those skilled in the art. Therefore, naturally, the multiplier A, the multiplier B, the adder 102, the rounding processor 103,
It should be considered that each of the truncation processors 104 is configured by software. Therefore, all except the frame memory can be realized by a program.

Hereinafter, the flowchart of FIG. 7 will be briefly described. First, the multiplier A takes in the input video signal 101 output from the signal separator 21. At the same time,
The multiplier B fetches the corresponding one-frame previous video signal output from the frame memory 105 (S701).
Next, the multiplier A multiplies the input video signal 101 by (1−K) and outputs it to the adder 102. At the same time, the multiplier B multiplies the video signal corresponding to the immediately preceding frame fetched from the frame memory 105 by K and outputs it to the adder 102 (S702).

Thereafter, the adder 102 outputs the (1-K) multiplied input video signal output from the multiplier A and the multiplier B
Is added to the corresponding output video signal of the previous frame multiplied by K and output to the rounding processor 103 and the truncation processing unit 104 (S703). As a result, the truncation processing unit 104 performs truncation processing on the video signal output from the adder 102 to a decimal point.
Output to the frame memory 105. In addition, rounding processor 1
03 rounds up the decimal point of the video signal output from the adder 102 and outputs it as an output video signal 106. The frame memory 105 performs the truncation processing 1
04 are stored in the order of reception (S
704).

Finally, the multiplier A waits until the time when the next input video signal should be input, and continues this processing while the next input video signal is being input (S705, S70).
6). Step S704 in the flowchart of FIG.
, The rounding processor rounds up the decimal portion of the video signal output from the adder 102 and outputs the result to the frame memory 105.
It is also possible to configure so that the video signal output from 2 is rounded down to the decimal point and output (in this case, the frame memory 105 stores the video signal output from the rounding processor in the order of reception). ).

The above-described noise reduction method according to the present invention can be implemented as a program executed on a general-purpose computer system, and stored and distributed on a recording medium such as a CD-ROM.

[0060]

As described above, the noise reduction device according to the present invention is a device for reducing noise included in a moving image expressed by a continuous frame, and relates to one target pixel in a processing target frame. synthesizing means for synthesizing a pixel value composed of n bits and a pixel value composed of n bits relating to a corresponding pixel one frame before, and a first means for performing processing of discarding a predetermined lower-order bit from the pixel value after composition And second means for performing a process of rounding up a predetermined lower-order bit with respect to the pixel value after synthesis, and delay means for delaying the pixel value that has undergone one of the first means and the second means by one frame, The pixel value after the delay is input to the synthesizing unit as the pixel value of the corresponding pixel one frame before, and the pixel value that has undergone the other process of the first unit or the second unit is set as the noise-reduced pixel value. hand of Configured to output from.

Accordingly, when outputting a video signal obtained by performing a process of rounding up a predetermined lower-order bit with respect to a video signal relating to a target pixel, the video signal subjected to a process of rounding down a predetermined lower-order bit is stored, and conversely. When outputting a video signal that has been subjected to a process of rounding down predetermined lower bits, the video signal that has undergone the process of rounding up the predetermined lower bits is stored and noise reduction is performed. Therefore, it is possible to realize a noise reduction device that can reflect the change in the output video signal even when the input video signal is slightly changed even if the error caused by the change is cancelled.

The synthesizing means multiplies one of the pixel value of the pixel of interest in the frame to be processed and the pixel value of the corresponding pixel one frame before by (1-K) times (K
Can be configured as 0 <K <1), a means for multiplying the other by K and then adding. Thereby, the input video signal relating to the pixel of interest is (1)
-K) times, and even if the corresponding video signal one frame before is multiplied by K, it is possible to realize a noise reduction device capable of reflecting a minute change in the input video signal to the output video signal.

Further, the first means may be a means for cutting off the decimal part from the pixel value after synthesis, and the second means may be a means for rounding up the decimal part from the pixel value after synthesis. it can. Thereby, for the video signal relating to the pixel of interest, when outputting a video signal rounded down to the decimal point, storing the video signal rounded down to the decimal point, and conversely, when outputting a video signal rounded down to the decimal point Since the noise reduction is performed by storing the video signal rounded up to the decimal point, errors occurring with each of the processing of rounding up and the processing of rounding down are offset, and even if the input video signal is slightly changed,
It is possible to realize a noise reduction device that can reflect the change in the output video signal.

On the other hand, the noise reduction method according to the present invention is a noise reduction method in an apparatus for reducing noise included in a moving image expressed by a continuous frame, and relates to a pixel of interest in a frame to be processed. a first receiving step of receiving an n-bit pixel value, a second receiving step of receiving an n-bit pixel value of a pixel one frame before corresponding to one target pixel in the processing target frame, a first receiving step, A combining step of combining the pixel values received by the second receiving step, a truncation step of performing a process of truncating a predetermined lower bit on the pixel value after the synthesis, and a predetermined lower order with respect to the pixel value after the synthesis. A round-up step for rounding up bits, and a delay mode for delaying a pixel value after one of the round-down or round-up steps by one frame. And output from the other step as a noise-reduced pixel value the pixel value that has undergone the other processing of the round-off step or the round-up step, and one pixel of interest in the second receiving step Is characterized in that the pixel value of the pixel one frame before corresponding to is a corresponding pixel value delayed by one frame in the delay step.

According to the noise reduction method of the present invention, when outputting a video signal obtained by performing a process of rounding up a predetermined lower-order bit with respect to a video signal related to a target pixel, a process of discarding the predetermined lower-order bit is performed. In the case of outputting a video signal that has been subjected to processing for rounding down predetermined lower bits, the video signal that has been processed to round up predetermined lower bits is stored and noise reduction is performed. Errors caused by each of the round-up process and the round-down process are cancelled, and even if the input video signal changes slightly, it is possible to realize noise reduction that can reflect the change in the output video signal. .

Further, a recording medium on which the noise reduction program according to the present invention is recorded is a computer-readable recording medium on which a noise reduction program for an apparatus for reducing noise contained in a moving image represented by continuous frames is recorded. A first receiving step of receiving an n-bit pixel value of one pixel of interest in the frame to be processed, and an n-bit pixel value of one pixel before the frame corresponding to one pixel of interest in the frame to be processed. A second receiving step of receiving a pixel value, a synthesizing step of synthesizing the pixel values received by the first and second receiving steps, and a process of cutting off a predetermined lower-order bit from the synthesized pixel value. A discarding step, a rounding-up step of rounding up a predetermined lower-order bit with respect to the pixel value after synthesis, and a rounding-down step. A delay step of the pixel value that has undergone one of the processing flop or round-up step is one-frame delay,
And causing the computer to execute a pixel value that has undergone the other processing of the round-down or round-up step as a noise-reduced pixel value, and an output step that outputs the pixel value from the other step. A program is recorded, wherein the pixel value of the corresponding pixel one frame before is the corresponding pixel value delayed by one frame in the delay step.

Thus, the recording medium on which the noise reduction program according to the present invention has been recorded, when outputting a video signal obtained by performing a process of rounding up a predetermined lower-order bit for a video signal relating to a target pixel, outputs the predetermined lower-order bit. When the video signal subjected to the process of rounding down the predetermined lower bits is stored and the video signal subjected to the process of rounding down the predetermined lower bit is output, the video signal subjected to the process of rounding up the predetermined lower bit is stored and the noise is stored. Since the program for reduction is stored, the error caused by the processing of rounding up and the processing of rounding down are canceled out, and even if the input video signal slightly changes, noise that can reflect the change in the output video signal can be reflected. The computer can execute the reduction program.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a display device 20 including a noise reduction device 100.

FIG. 2 is a diagram illustrating an example of the number of scanning lines in one frame and the number of pixels in one scanning line.

FIG. 3 is a functional block diagram of the noise reduction device 100.

FIG. 4 is a detailed functional block diagram of a frame memory 105.

FIG. 5 is an example of a video signal of each unit when the present device 100 is applied to a video signal related to a first pixel in a first frame and a second frame.

FIG. 6 is a functional block diagram of the noise reduction device 600.

FIG. 7 is a flowchart illustrating a flow of processing of a noise reduction method.

FIG. 8 is a functional block diagram of a conventional noise reduction device 800.

FIG. 9A is an example of an image showing a state immediately before a ball hits a wall. (b) is an example of an image showing a state immediately after a ball hits a wall.

[Explanation of symbols]

 Reference Signs List 10 surveillance camera 11 signal 20 display device 21 signal separation unit 22 frame synchronization control unit 23 signal synthesis unit 100, 600 noise reduction device 800 noise reduction device 101, 801 input video signal 102, 802 adder 103, 602 rounding processor 803 rounding Processor 104, 601 Truncation processor 105, 804 Frame memory 106, 805 Output video signal 111 Control unit input 112 First storage unit 113 Second storage unit 114 Output control unit

Claims (5)

[Claims] 1. An apparatus for reducing noise included in a moving image represented by a continuous frame, comprising: a pixel value consisting of n bits relating to one pixel of interest in a processing target frame and a corresponding pixel value of one frame before Synthesizing means for synthesizing a pixel value composed of n bits relating to a pixel; first means for performing a process of discarding a predetermined lower bit from the pixel value after synthesis; and a predetermined lower order for the pixel value after synthesis. A second means for rounding up bits; and a delay means for delaying the pixel value after one of the first means and the second means by one frame, wherein the pixel value after the delay is one frame before the synthesizing means. Noise reduction, wherein a pixel value which has been input as a pixel value relating to a corresponding pixel of the first means or has undergone the other processing of the first means or the second means is output as a noise-reduced pixel value from the other means. apparatus. 2. The method according to claim 1, wherein one of the pixel value of the pixel of interest in the frame to be processed and the pixel value of the corresponding pixel one frame before is multiplied by (1-K) (where K is 2. The noise reduction device according to claim 1, wherein the noise reduction device is means for performing 0 <K <1), multiplying the other by K times, and adding the result. 3. The method according to claim 1, wherein the first unit is a unit that rounds down the decimal point from the pixel value after the synthesis, and the second unit is a unit that rounds up the decimal point from the pixel value after the synthesis. Item 3. The noise reduction device according to Item 2. 4. A noise reduction method in a device for reducing noise included in a moving image represented by continuous frames, comprising: a first method for receiving an n-bit pixel value of one pixel of interest in a frame to be processed; A receiving step; a second receiving step of receiving an n-bit pixel value of a pixel one frame before corresponding to one target pixel in the processing target frame; and a pixel received by the first receiving step and the second receiving step. A combining step of combining values, a truncating step of performing a process of truncating predetermined lower bits on a pixel value after combining, and a rounding-up step of performing a process of rounding up predetermined lower bits of a pixel value after combining. A delay step of delaying the pixel value that has undergone one of the truncation step and the round-up process by one frame; and a round-down step or round-up An output step of outputting, from the other step, a pixel value that has undergone the other processing of the step as a noise-reduced pixel value. The pixel value is a corresponding pixel value delayed by one frame in the delay step. 5. A computer-readable recording medium recording a noise reduction program for an apparatus for reducing noise included in a moving image represented by continuous frames, wherein the program comprises one of a frame to be processed. A first receiving step of receiving an n-bit pixel value of the target pixel of the first and a second receiving step of receiving an n-bit pixel value of a pixel one frame before corresponding to one target pixel in the processing target frame; A combining step of combining the pixel values received by the first receiving step and the second receiving step, a truncating step of performing a process of truncating predetermined lower bits on the pixel value after the combining, On the other hand, a round-up step of rounding up a predetermined lower-order bit and one of a round-down step and a round-up step A delay step of delaying the prime value by one frame, and an output step of outputting, from the other step, a pixel value that has undergone the other processing of the truncation step or the round-up step as a noise-reduced pixel value, A recording medium on which a program is recorded, wherein a pixel value of a pixel one frame before corresponding to one target pixel in the two receiving steps is a corresponding pixel value delayed by one frame in the delaying step.