JP2000224208A - Packet transfer controller and packet transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet transfer controller that adopts a direct memory access transfer system and conducts another packet transfer processing when a packet storing direct memory access data is continuously transferred. SOLUTION: A header identification circuit 13 compares header information of a received packet with storage information of a header information storage circuit 16 so as to discriminate whether or not a received packet is a packet storing direct memory access data. When the packet is a packet storing the direct memory access data, a buffer 14 stores the direct memory access data and a DMA controller 19 controls DMA transfer. On the other hand, when the received packet is not a packet storing the direct memory access data, a header information storage circuit 17 stores the header information of this packet. An MPU 20 issues a transmission packet on the basis of the information stored in the header information storage circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a packet transfer control device and method for transferring a large amount of data at high speed.

An interface device as a transfer control device for transferring a large amount of data at high speed, for example, IEEE139
An interface device that adopts the four standards needs to operate as efficiently as possible. In other words, the interface device is controlled by a microprocessor unit (hereinafter, referred to as MPU) or the like, but in order to transfer data efficiently, it is necessary to minimize the access from external devices as much as possible and realize the transfer operation efficiently. There is. However, in practice, while one large data is being transferred, a plurality of data may be transferred from another device.
A mechanism for efficiently using a control device such as an MPU is required.

[0003]

2. Description of the Related Art A packet transfer method defined in the IEEE 1394 standard or the like is a format in which header information is added in addition to data to be transferred.
The PU decodes the header information of the packet and decides to handle data following the header information. The size of data that can be stored in one packet is defined by a protocol. However, when this transfer method is employed, when handling data having a large amount of information such as image information, the data cannot be accommodated in one packet, and the original data is divided into a plurality of blocks to perform data transfer. ing. That is, large data is transferred by generating a packet storing header information for each divided block (data) and transferring the plurality of packets continuously. Of course, on the receiving side, the original data is reproduced by the MPU sequentially storing the data divided into a plurality of packets in the memory. Since such a packet is used for displaying an image (for example, a moving image) and the like, it is continuously transmitted in a short time, so that the load of an MPU processing the packet increases.

[0004] The direct memory access (DMA) transfer method is a method developed for handling a large amount of data, and by applying this method, data from an external device can be taken into a memory without passing through an MPU. it can.

More specifically, as shown in FIG. 2, a packet transfer control device (node) 30 adopting the DMA transfer method
Is an interface 31, a buffer 32, an MPU 33,
DMA controller 34 and memory 35 are included. The interface 31 takes in a packet including a header and data from the network.

[0006] The interface 31 outputs the header separated from the received packet to the MPU 33 and the data to the buffer 32. When the MPU 33 determines that the received data is DMA transfer data based on the information of the header, the MPU 33 outputs an enable signal to the DMA controller 34.
5 starts data transfer.

The packet transfer control device 30 fetches DMA transfer data continuously transferred from the network into the buffer 32, and
4, the data is stored in the memory 35. That is, MP
After U33 detects the DMA transfer addressed to itself (own node), the DMA controller 34 mediates between the buffer 32 storing the received data and the memory 35, thereby releasing the MPU 33 from the data transfer processing.

[0008]

As described above, since the load on the MPU 33 is reduced by employing the DMA transfer method, the MPU 33 can perform other processing (for example, data processing). . In other words, the input / output of the buffer 32 and the memory 35 is D
It is occupied by the MA controller 34 and the MPU 33 cannot do so during that time.

For this reason, as shown in FIG.
Continuously transfers packets to the node 30,
Is performing the data processing, even if another device (node) 41 on the network issues a packet for an access request to the node 30 as described above,
Since the MPU 33 does not intervene during the transfer, the node 30
MPU 33 cannot accept the packet issued from the node 41. Therefore, the node 30 cannot return a response to the issued packet to the node 41. In this case, since the issued packet becomes invalid, the node 41 reissues (retry) the access request until receiving a response from the node 30.
In other words, if this method is adopted, the processing efficiency of other devices connected to the network will decrease.

[0010] If there is a response of "access denied" to the access request, the node 41 which has made the access request can discard the process and execute another process, thereby suppressing a decrease in processing efficiency. be able to. However, when the response to the access request does not return as described above, the node 41 normally suspends the processing, and cannot perform other processing, or can perform only limited processing. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to employ a direct memory access transfer method and continuously transfer packets holding data for direct memory access. It is an object of the present invention to provide a packet transfer control device and a packet transfer method capable of performing another packet transfer when the packet transfer is performed.

[0012]

According to the first aspect of the present invention, it is determined whether a received packet is a continuous transfer packet holding data for direct memory access by a packet identification unit or a non-continuous packet other than a continuous packet. Is determined. If the packet is a continuous transfer packet holding the data for direct memory access, the data of the packet is stored in the buffer and transferred to the memory by the direct memory access control means. On the other hand, if the received packet is a discontinuous packet that does not hold the data for direct memory access, the header information of the packet is stored in the header storage unit. Then, a response packet to the non-consecutive packet is transmitted based on the header information stored in the header storage means.

Therefore, when a packet for direct memory access is continuously received, and when a packet from another device is received at that time, the packet is received based on the header information stored in the header storage means. Can be responded to. Specifically, even when a packet holding data for direct memory access from an external device is continuously received, an access reject command is issued in response to an access request command from another device. For this reason, another device that receives the access reject command can stop the communication retry process and execute another process. As a result, the processing efficiency including other devices connected to the packet transfer control device via the network is improved.

According to the present invention, the data held by the non-consecutive packets is stored in a buffer provided separately from the buffer in which the data for direct memory access is stored. In this case, even during the processing of the data for DMA transfer, the processing of the data held in a non-consecutive packet different from the data for DMA transfer can be performed.

When data is divided into a plurality of blocks and packets storing the blocks are continuously transferred,
This continuous transfer packet has regularity, and it can be easily determined whether or not the packet is the same packet.

Therefore, according to the third aspect of the present invention, whether or not a packet is a continuous transfer packet is determined by the packet identification means based on the type of packet (TCODE) held as header information in the packet.

According to the fourth aspect of the present invention, node identification information held as header information in a packet,
That is, based on the node ID (Physical ID), the packet identification unit determines whether or not the packet is a continuous transfer packet.

According to the fifth aspect of the present invention, the enable signal is issued when the packet identifying means receives the packet for notifying the direct memory access. By the direct memory access control means based on the enable signal,
A direct transfer of data between the memory and the buffer is prepared.

According to the present invention, an interrupt signal is generated by the direct memory access control means when the direct transfer of the data divided into a plurality of blocks is completed. Thus, the end of the transfer of the continuous transfer packet is determined.

According to the present invention, it is determined whether or not the received packet is a packet holding data for direct memory access, and if the received packet is a packet for holding data for direct memory access, the packet is Is stored in the buffer, and the stored data is transferred to the memory. That is, direct memory access transfer is performed. On the other hand, if the packet does not hold the data for direct memory access, the header information held by the packet is stored in the header storage unit. Therefore, when a packet for direct memory access is continuously received and a non-held packet is received, a command held by the non-held packet is processed based on the header information stored in the header storage unit.

According to the eighth aspect of the present invention, when a packet notifying of direct memory access transfer is received, header information of the packet is stored. Then, the header information is compared with the header information of the received packet, and it is determined whether or not the received packet is a packet holding data for direct memory access.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. FIG. 1 shows an IEEE1 for a network.
FIG. 3 is a block circuit diagram of a packet transfer control device 1 connected to a 394 bus.

The packet transfer control device 1 includes interfaces (I / F) 2, 3, 4, physical layer processing circuits 5, 6, 7,
Link layer processing circuits 8, 9, 10, packet generation circuit 1
1, 12, header identification circuit 13, data storage buffer 1
4, 15; header information storage circuits 16, 17; memory 1
8, DMA controller (DMAC) 19, MPU 20
Contains.

The packet transfer control device 1 of the present embodiment employs a DMA transfer method for transferring data such as image data, which has a large data amount and needs to be transferred continuously, between the buffer 14 and the memory 18. I have. The data is stored in a plurality of packets in a divided state.
Asynchronous packets (Asynchronous) on the 394 bus
Packet). Therefore, in the packet transfer control device 1 according to the present embodiment, recognition between nodes, negotiation for transferring large data, a command, a status, and the like are performed by other circuits except the MPU 20. The data may be transferred as an isochronous packet.

The packet includes a header for storing header information and data. The header information includes (1) destination node ID (Physical ID), and (2) source node ID (P
hysical ID), (3) Packet type (Transaction co
de: TCODE), and the header information for performing continuous transfer includes (4) a storage location of transfer data (offset of data storage area: destination offset).

However, the packet transfer control device 1 also transfers packets other than the packet storing the data. As a type of this packet, for example, there is a type including a command such as a read request, a read response, a write request, a write response, and a command requested from another external device by the packet is determined by the MPU 20, and The corresponding processing is performed.

In the present embodiment, a packet that is continuously transferred while holding the data for DMA transfer is called a continuous transfer packet, and the other packets are called non-continuous packets. Specifically, the interfaces 2, 3, and 4 are connected to an IEEE 1394 bus for exchanging packets with other devices. The interface 2 is a reception port for receiving a packet, and the interfaces 3 and 4 are transmission ports for transmitting a packet.

The physical layer processing circuit 5 is connected to the interface 2 and receives a received packet from the interface 2. The physical layer processing circuit 5 is connected to the link layer processing circuit 8 and outputs a received packet to the link layer processing circuit 8. At this time, the physical layer processing circuit 5 plays a role of converting an electrical signal into a logical signal handled by the link layer processing circuit 8.

The physical layer processing circuits 6 and 7 are connected to link layer processing circuits 9 and 10, respectively.
10. A transmission packet is input from 10. The physical layer processing circuits 6 and 7 are connected to the interfaces 3 and 4, respectively, and transmit transmission packets to the interfaces 3 and 4.
At this time, the physical layer processing circuits 6 and 7 play a role of converting logical signals handled by the link layer processing circuits 9 and 10 into electrical signals.

The link layer processing circuit 8 performs a packet format check and the like to assure reliable packet transfer. Specifically, if the link layer processing circuit 8 is a packet addressed to itself, the link layer processing circuit 8
To supply. If the packet is not addressed to itself, the packet is sent to the physical layer processing circuits 6 and 7 and the interface 3 and
4 to be transmitted to other external devices.

The packet generation circuits 11 and 12 are connected to the link layer processing circuits 9 and 10,
The transmission packets generated in steps 1 and 12 are output to link layer processing circuits 9 and 10. That is, the packet generation circuit 11,
Reference numeral 12 adds, to input data from the data storage buffer 14 and the MPU 20, header information suitable for a packet to be transmitted.

The header identification circuit 13 is connected to the link layer processing circuit 8 and receives a received packet from the link layer processing circuit 8 addressed to itself. Also, the header identification circuit 13
It is connected to a data storage buffer 14 and a header information storage circuit 16 for MA transfer, that is, continuous transfer. Further, the header identification circuit 13 performs packet transfer other than DMA transfer, that is, the data storage buffer 1 for non-continuous transfer.
5 and a header information storage circuit 17.

The header identification circuit 13 identifies the received packet based on the header information of the received packet input from the link layer processing circuit 8. More specifically, the header identification circuit 13 determines the type of packet included in the header information,
Determine whether the packet is for continuous transfer based on TCODE. Based on the determination result, the header identification circuit 1
3 outputs the header information included in the continuous transfer packet to the header information storage circuit 16 and the data included in the packet to the buffer 14. On the other hand, if the received packet is a non-consecutive packet, the header identification circuit 13 outputs the header information included in the packet to 17 and the data included in the packet to the buffer 15.

When a packet holding a command for notifying the DMA transfer is received and the packet is identified by the header identification circuit 13, the header information storage circuit 1
6 stores the header information of the packet. This header information includes the first place (address) of the transfer data,
It includes the total data length to be transferred continuously.

The buffer 14 is connected to the memory 18 and the DMA controller 19. When the data for DMA transfer is stored in the buffer 14, the DMA controller 19
Thus, the transfer of the data in the buffer 14 to the memory 18 is controlled. The buffer 15 and the header information storage circuit 17
The MPU 20 is connected, and the MPU 20 is connected to the DMA controller 19 and the packet generation circuit 12.

The MPU 20 executes each process according to a command included in the header information stored in the header information storage circuit 17. Specifically, the MPU 20 controls the buffer 1
5 is output to the packet generation circuit 12 for processing the data stored in No. 5 and issuing non-consecutive packets. Alternatively, the MPU 20 outputs an enable signal ENB for starting the DMA transfer to the DMA controller 19. The data transfer control between the buffer 14 and the memory 18 by the DMA controller 19 is started by the enable signal ENB. When the DMA transfer is completed, the DMA controller 19 sends the MPU 20
An interrupt signal INT is output to the MPU 20
Determines the end of the DMA transfer.

The data storage buffer 14 is connected to the packet generation circuit 11 and outputs data for transmitting a continuous transfer packet to the packet generation circuit 11. In the case of continuously transmitting continuous transfer packets, DMA
Data stored in the memory 18 is transferred to the data storage buffer 14 based on a control signal of the controller 19. When transmission of this continuous transfer packet is completed,
An interrupt signal INT is output from the MA controller 19 to the MPU 20, and the MPU 20 determines the end of the DMA transfer.

As described above, in this embodiment, during the transfer of the continuous transfer packet holding the data for DMA transfer, the MP
It is configured not to report an interrupt to U20. When large data is divided into a plurality of blocks and continuously transferred, that is, when continuously transferred packets are transferred, since the packets have regularity, it is possible to easily determine whether or not the packets are continuously transferred packets. In the present embodiment, this determination is made based on the TCODE included in the header information. However, the present invention is not limited to this. For example, the determination may be made based on the node ID, or depending on the storage location of the transfer data. It may be determined.

The data amount held in the continuous transfer packets is larger than the data amount held in the non-consecutive packets, and the capacity for storing the data in the buffer 14 is designed to be larger than the capacity of the buffer 15. .

In the present embodiment, the header identification circuit 13 and the header information storage circuit 16 correspond to packet identification means.
The header information storage circuit 17 corresponds to a header storage unit.
The MPU 20, the packet generation circuit 12, the link layer processing circuit 10, the physical layer processing circuit 7, and the interface 4 correspond to a transmission unit, and the DMA controller 19 corresponds to a direct memory access control unit.

Next, the operation of the packet transfer control device 1 configured as described above will be described. First, a case where a continuous transfer packet is continuously received will be described. Now, a packet including a command for notifying the DMA transfer as header information is sent from another device. Then, the packet is supplied to the header identification circuit 13 via the interface 2, the physical layer processing circuit 5, and the link layer processing circuit 8. And
The header identification circuit 13 determines that the packet includes a command for notifying the DMA transfer, and the command of the packet is transferred to the header information storage circuit 17.
At this time, information such as the first location (storage start address or offset address) of the transfer data held in the received packet and the total data length to be continuously transferred are stored in the header information storage circuit 16. Then, the MPU 20 outputs a DMA transfer enable signal to the DMA controller 19 based on the command stored in the header information storage circuit 17. Further, the MPU 20 outputs the storage start address and the total data length to the DMA controller 19.
Thus, direct transfer of data between the buffer 14 and the memory 18 is prepared.

Next, when a continuous transfer packet holding DMA transfer data is sent, the type of the packet (TC
The header information of the received packet is identified by the header identification circuit 13 based on the ODE), and the data held in the packet is stored in the buffer 14. After that, the data stored in the buffer 14 is transferred to the memory 18 by the DMA controller 19.

Subsequently, when a continuous transfer packet holding the data for DMA transfer is received, the same processing as described above is executed, and the data of the received packet is stored in the buffer 14.
Via the memory 18. Thus, the MPU
The data stored in the buffer 14 is sequentially transferred to the memory 18 by the DMA controller 19 without involvement of the memory 20.

Thereafter, when the last data of the DMA transfer data is stored in the memory 18, the DMA controller 19 determines the end of the DMA transfer based on the start address and the total data length, and sends an interrupt signal INT to the MPU 20.
Is output. This completes the DMA transfer of the data divided into a plurality of blocks.

As described above, when continuous transfer packets are continuously received, another process is performed because the MPU 20 does not participate in the DMA transfer. In the present embodiment, a data storage buffer 15 and a header information storage circuit 17 for non-continuous transfer are provided separately from the data storage buffer 14 and the header information storage circuit 16 for DMA transfer, that is, for continuous transfer. While the DMA transfer is being performed, another packet transfer process is performed.

Here, a case where an access request command is sent from another device to the device 1 while the packet transfer control device 1 is continuously receiving continuous transfer packets as described above. explain.

Specifically, for example, when a packet holding an access request for DMA transfer is sent, the header information of the received packet is stored in the header information storage circuit 16 by the header identification circuit 13. A comparison is made to determine that the packet is not a continuous transfer packet that is currently undergoing DMA transfer processing. The header information of the received packet is stored in the header information storage circuit 1 by the header identification circuit 13.
7 is stored. Then, based on the access request command stored in the header information storage circuit 17, the MPU 20 issues a response packet holding the access rejection command. That is, a packet holding the access rejection command is generated by the packet generation circuit 12 based on the data from the MPU 20. And the packet is
The data is transferred onto the IEEE 1394 bus via the link layer processing circuit 10, the physical layer processing circuit 7, and the interface 4.

As described above, when the response packet holding the access reject command is transferred from the device 1 to the other device that has issued the access request, the other device that has received the access reject command is Then, the DMA transfer process is stopped and another process is performed.

When a non-consecutive packet holding write data addressed to itself is received instead of a continuous transfer packet, the data is stored in the buffer 15 by the header identification circuit 13 and then received by the MPU 20. The data of the packet is processed.

Further, when the continuous transfer packet is continuously received, the MPU 20 does not participate in the DMA transfer, so that the transmission packet is transmitted to a device different from the device performing the DMA transfer process. It is also possible. That is, a transmission packet is generated by the MPU 20 using the packet generation circuit 12, and the packet is transmitted to the link layer processing circuit 10, the physical layer processing circuit 7, the interface 4
Over the IEEE 1394 bus.

Next, a case where the continuous transfer packets are continuously transmitted using the packet transfer control device 1 will be described. First, the MPU 20 sends a DM
The area of the memory 18 for the A transfer (the head address of the data, the data length, etc.) is designated. Then, the data stored in the memory 18 is transferred to the buffer 14 by the DMA controller 19. Predetermined data is buffer 1
4, the data is transmitted to the packet generation circuit 11 to generate a continuous transfer packet. Then, the packet is transmitted to an external device via the link layer processing circuit 9, the physical layer processing circuit 6, and the interface 3. afterwards,
Until all data in the area of the memory 18 specified by the DMA controller 19 is transferred, a transmission packet is generated and transferred continuously. In this way, transmission processing of large data such as image data is performed without involving the MPU 20.

In the packet transfer control device 1, even when continuous transfer packets are continuously transmitted, the MP
Another process is performed by U20. Specifically, DM
When the packets are continuously transferred by the A controller 19, for example, the packet transfer processing is performed to a device other than the partner device that is currently performing the DMA transfer. In this case, the MPU 20 generates a transmission packet using the packet generation circuit 12, and the packet is issued to another device via the link layer processing circuit 10, the physical layer processing circuit 7, and the interface 4.

Further, when the continuous transfer packets are continuously transmitted, the processing of the packet received from the other device other than the partner device which is currently performing the DMA transfer is performed. In this case, the header information of the received packet is stored in the header information storage circuit 17, and the MPU 20 performs the receiving process. At this time, if data is held in the received packet, the data is stored in the data storage buffer 15 and processed by the MPU 20.

As described above, DMA transfer data, that is,
The data held in the continuous transfer packets is efficiently transferred without the intervention of the MPU 20, and the other transfer packets are transferred by the MPU 20.

The interfaces 3 and 4, the physical layer processing circuits 6 and 7, the link layer processing circuits 9 and 10, and the packet generation circuits 11 and 12 shown in FIG. Functionally related parts are shown. Therefore, each of the circuits 3 to 12 may be configured to perform a process for packet output by one of the circuits 3, 6, 9, and 11 (or 4, 7, 10, and 12).

As described above, the present embodiment has the following advantages. (1) When a continuous transfer packet is continuously received, another packet reception process can be performed. Specifically,
The packet transfer control device 1 can now issue an access rejection response to an access request from a device different from the device performing the DMA transfer. Therefore, another device can receive the packet holding the access rejection command, and there is no need to repeat the retry of the transfer process for the packet transfer control device 1. Therefore, the present device 1 and the IEEE 139
The processing efficiency of the entire system including other devices connected via four buses can be improved.

(2) When a packet for notifying the DMA transfer is received, the MPU 20 controls the DMA controller 1
9 when the enable signal ENB is issued.
Transfer starts. Based on the information stored in the header information storage circuit 16, the header identification circuit 13 determines that the received packet is a continuous transfer packet holding the data for DMA transfer, and the data for DMA transfer is stored in the data storage buffer 14. Thereafter, the data is transferred to the memory 18 by the DMA controller 19. When all the DMA transfer data divided into a plurality of pieces are stored in the memory 18, the DMA
An interrupt signal is generated in the MPU 20 by the controller 19, and the DMA transfer ends. Therefore, MPU20
Irrespective of this, it is possible to carry out a process of receiving DMA transfer data that is continuously transferred.

(3) In addition to the buffer 14 for DMA transfer data, a buffer 15 for storing data other than DMA transfer data is provided, and the data held by the received packet is sorted by the header identification circuit 13. Thereby, the DMA transfer data can be stored in the memory 18 via the buffer 14 without interruption of other data. In addition, during processing of DMA transfer data that is continuously transferred, processing of data other than DMA transfer can also be performed.

(4) The buffer 14 is configured to have a larger capacity than the buffer 15 in accordance with the amount of data held by the packet. In this way, when the packet transfer control device 1 is embodied as a semiconductor chip, the chip cost can be improved, which is advantageous in terms of cost.

(5) When a non-consecutive packet holding data other than the data for DMA transfer is received, the header and data are separated by the header identification circuit 13 and the header information is stored in the header information storage circuit 17. At the same time, the data is stored in the data storage buffer 15. That is, the MPU 20 does not need to perform the process of separating the header information from the received packet holding the data. Therefore, M
The processing load on the PU 20 can be reduced.

Each of the above embodiments may be implemented in the following manner. When a continuous transfer packet is continuously received, the packet received at that time is not necessarily limited to a packet including data for DMA transfer. For example, the packet may include a request command for returning the state of the DMA transfer, or may include a request command for stopping the DMA transfer. In this case, the header identification circuit 1
3, the request command is recognized, and the packet generation circuit 11
And the like to transmit the transmission packet. With this configuration, even when a packet including a request command for returning or canceling the state of the DMA transfer is received, the MPU 20 can execute other processing without being concerned with the DMA transfer processing.

In the above embodiment, the configuration includes the header information storage circuit 17, but this may be omitted. Specifically, header information is also stored in the buffer 15 at the same time,
The MPU 20 processes the header information.
In this case, the buffer 15 corresponds to a header storage unit.
Even in this case, when continuous transfer packets are continuously received, another packet from another device can be received, so that the processing efficiency of the entire system including the device connected to the IEEE 1394 bus is improved. It is possible to do. However, the MPU 20 needs to process the data after separating the header information of the received packet.
Since the processing load of the PU 20 increases, it is more preferable to include the header information storage circuit 17 as in the above embodiment.

In the above-described embodiment, the configuration including the buffer 15 has been described. In this case, when a non-consecutive packet is transferred from another device to the device 1 while the packet transfer control device 1 is performing the DMA transfer process, only the header information is stored in the header information storage circuit 17. The MPU 20 causes the MPU 20 to issue a packet including the access reject command. If data is stored in the non-consecutive packet received when the DMA transfer process is not performed, the data is stored in the buffer 14 and the header information is stored in the header information storage circuit 1.
7 is stored. Then, the MPU 20 performs the data processing stored in the buffer 14 based on the header information of the header information storage circuit 17. Even in this case, the IEEE
The processing efficiency of the entire system including the devices connected to the 1394 bus can be improved.

In the above embodiment, the command for notifying the DMA transfer is analyzed by the MPU 20.
The enable signal to the MA controller 19 may be issued by the header identification circuit 13, the header information storage circuit 16, and the like. This eliminates the need for the processing of the MPU 20 at the start and end of the DMA transfer, so that the processing load on the MPU 20 can be further reduced.

In the above embodiment, the packet transfer control device 1 connected to the IEEE 1394 bus is embodied. However, the present invention is not limited to this. For example, SCSI bus, U
The present invention may be embodied in a packet transfer control device connected to the SB. In short, what is necessary is just to embed a packet transfer control device that divides large data such as image data, stores the divided data in a plurality of packets, and continuously transfers the packets.

In the above embodiment, the header information is stored in the header information storage circuit 16 when the packet holding the command for notifying the DMA transfer is received, but the present invention is not limited to this. For example, when the ID, data length, address, and the like of the partner to be DMA-transferred are determined, the information may be set in the header information storage circuit 16 in advance. That is, any information that can determine the data for DMA transfer, such as the node ID of the partner of the DMA transfer and the type of packet, may be stored in the header information storage circuit 16.

[0067]

As described in detail above, according to the present invention,
When packets holding data for direct memory access are continuously transferred, another packet transfer can be performed. Therefore, it is possible to improve the processing efficiency including other devices connected to the present packet transfer control device via the network.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a packet transfer control device according to an embodiment.

FIG. 2 is a block circuit diagram of a conventional packet transfer control device.

FIG. 3 is a block diagram for explaining conventional data transfer.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 packet transfer control device 13 header identification circuit constituting packet identification means 14, 15 buffer 17 header information storage circuit as header storage means 18 memory 19 DMA controller as direct memory access control means

Claims (8)

[Claims] 1. A packet transfer control device for dividing data into a plurality of blocks and continuously transferring a continuous packet storing each block between two devices, wherein the plurality of blocks are stored. A memory, a buffer for storing the blocks stored in the continuous transfer packet, and a direct memory access control means for controlling the direct transfer of data between the memory and the buffer, in a transfer control device comprising: A packet for determining whether the packet is a continuous transfer packet or a non-continuous packet other than the continuous packet, storing a block stored in the continuous transfer packet in the buffer, and storing header information of the non-continuous packet in header storage means A response packet for the non-consecutive packet based on the header information of the header storage means; A packet transfer control device, comprising: a transmission unit for transmitting a packet. 2. The packet transfer control device according to claim 1, further comprising a buffer separate from the buffer,
A packet transfer control device for storing data held in non-consecutive packets. 3. The packet transfer control device according to claim 1, wherein the packet identification unit determines whether or not the packet is a continuous transfer packet based on a type of the packet held as header information in the packet. A packet transfer control device characterized by the above-mentioned. 4. The packet transfer control device according to claim 1, wherein the packet identification unit determines whether or not the packet is a continuous transfer packet based on node identification information held as header information in the packet. A packet transfer control device characterized by the above-mentioned. 5. The packet transfer control device according to claim 1, wherein said direct memory access control means is based on an enable signal issued when said packet identification means receives a packet for announcing direct memory access. Preparing a direct transfer of data between said memory and said buffer;
A packet transfer control device characterized by the above-mentioned. 6. The packet transfer control device according to claim 1, wherein the direct memory access control means generates an interrupt signal when the direct transfer of the data divided into the plurality of blocks is completed. Packet transfer control device. 7. It is determined whether the received packet is a packet holding data for direct memory access, and if the received packet is a packet holding data for direct memory access,
The data held by the packet is stored in a buffer to be transferred to a memory. If the packet is a non-holding packet of direct memory access data, the header information held by the packet is stored in a header storage unit. A packet transfer method for processing a command held by a non-held packet based on header information stored in the header storage means when receiving the non-held packet during reception. 8. The packet transfer method according to claim 7, wherein, when a packet for notifying direct memory access transfer is received, header information of the packet is stored, and the header information and the header information of the received packet are stored. A packet transfer method for determining whether the received packet is a packet holding data for direct memory access by comparing