JP2015119255A - Transmission device and transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the speed of data transmission with a small size of memory.SOLUTION: A transmission device 1 includes a header merge circuit 110 and a header queue 120. The header queue 120 stores a header to be added to data in association with the control information of the header. The header merge circuit 110 obtains one or more data sets in a sequence from a data storage part in which one or more data sets are stored, add the header to the obtained data in accordance with the control information of the header obtained from the header queue 120, and output them.

Description

  The present invention relates to a transmission apparatus and a transmission method, and more particularly, to a transmission apparatus and a transmission method for transmitting data with a header added.

  In recent years, speeding up of serial interfaces (or serial buses) such as USB (Universal Serial Bus) 3.0 has been promoted.

  In a transmission apparatus having such a high-speed serial interface, the expected throughput may not be obtained when a header is added for each transmission packet. For example, when DMA (Direct Memory Access) is used for processing packet data in the device, a CPU (Central Processing Unit) that once terminates DMA in units of transmission packets, adds a header, and then starts DMA again. Processing occurs. In this case, due to the latency and processing time generated by the CPU interrupt, a larger interval than the transfer rate occurs between packets, and the expected throughput cannot be obtained.

  Furthermore, in a transmission apparatus equipped with a high-speed serial interface, the CPU occupancy rate due to such header addition processing may increase, and the processing performance of the system may decrease. For example, USB 3.0 has a transfer rate about 10 times that of USB 2.0. For this reason, the CPU must perform header addition processing about 10 times that of USB 2.0, which inevitably increases the CPU occupancy rate and affects the processing of other applications.

  As a technique for realizing high-speed serial interface, a method of adding a header to a packet not by a CPU but by hardware is known. For example, Patent Literature 1 discloses a data transmission device that combines a header and data stored in a memory with hardware to assemble a transmission packet.

  As a related technique, Patent Document 2 discloses a technique for generating an isochronous packet according to the IEEE 1394 standard. Patent Document 3 discloses a transmission / reception system that divides data into a plurality of packets, adds a subheader, and transfers the packets via a plurality of ports.

Japanese Patent No. 3543648 Japanese Patent Laid-Open No. 11-27301 JP 2006-109314 A

  However, in the data transmission device disclosed in Patent Document 1 described above, since it is necessary to prepare a header for each packet, a large-sized memory is required to store the header when the number of packets is large. There is a problem.

  An object of the present invention is to solve the above-described problems, and to provide a transmission apparatus and a transmission method therefor that can increase data transfer speed with a small memory size.

  Each of the one or more data is transmitted from a header information storage unit that stores a header to be added to the data in association with control information related to the header, and a data storage unit that stores one or more data. Header merging means for adding the header to the obtained data and outputting the data according to the control information relating to the header obtained from the header information storage means.

  In the transmission method of the present invention, a header to be added to data is stored in association with control information related to the header, and each of the one or more data is sequentially acquired from a data storage unit in which the one or more data is stored. In accordance with the control information related to the acquired header, the header is added to the acquired data and output.

  The effect of the present invention is that data transfer can be speeded up with a small memory size.

It is a block diagram which shows the characteristic structure of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the transmitter 1 in the 1st Embodiment of this invention. It is a flowchart which shows the process of the transmitter 1 in the 1st Embodiment of this invention. It is a figure which shows the example of a setting of the header queue 120 in the 1st Embodiment of this invention. It is a figure which shows the example of the packet transmitted from the transmitter 1 in the 1st Embodiment of this invention. It is a flowchart which shows the process of the transmitter 1 in the 2nd Embodiment of this invention. It is a flowchart which shows the interruption process of the header addition circuit 100 in the 2nd Embodiment of this invention. It is a figure which shows the example of a setting of the header queue 120 in the 2nd Embodiment of this invention. It is a figure which shows the example of the packet transmitted from the transmitter 1 in the 2nd Embodiment of this invention.

(First embodiment)
Next, a first embodiment of the present invention will be described.

  First, the configuration of the first exemplary embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the transmission apparatus 1 in the first embodiment of the present invention. The transmission device 1 is a device having a USB device function, such as a USB Web camera, and is connected to a device (not shown) having a USB host function, such as a personal computer, via a USB bus.

  Referring to FIG. 2, the transmission apparatus 1 according to the first embodiment of the present invention includes a header addition circuit 100, a DMA 200, a CPU 300, a USB core 400, a PHY (PHYsical Layer) chip 500, and a RAM (Random Access Memory). 600. The header addition circuit 100, the DMA 200, the CPU 300, the USB core 400, and the RAM 600 are connected by an internal bus (not shown).

  The header addition circuit 100 generates a packet by adding a header to the data acquired from the data storage unit 610 on the RAM 600. The header addition circuit 100 includes a header merge circuit 110 and a header queue 120. The header queue 120 stores a header to be added to data and control information related to the header. The header merge circuit 110 adds a header to the data acquired from the data storage unit 610 according to the control information.

  In the first embodiment of the present invention, the number of header repetitions is set in the control information. In the first embodiment of the present invention, one or more headers set in the header queue 120 are applied in order according to control information (repetition count).

  The DMA 200 transfers the packet generated by the header addition circuit 100 to the USB core 400. Thereby, the data in the data storage unit 610 can be transmitted to the USB bus without going through the CPU 300.

  The CPU 300 executes a program for realizing the functions of the data generation control unit 310, the header queue setting unit 320, the interrupt processing unit 330, and the transfer control unit 340.

  The data generation control unit 310 includes, for example, a data generation unit (not shown) such as a camera included in the transmission device 1 to generate data to be transmitted to the USB bus and store the data in the data storage unit 610. Instruct. For example, the data generation unit transfers the generated data to the data storage unit 610 via another DMA different from the DMA 200.

  The header queue setting unit 320 sets a header and control information corresponding to data to be transmitted to the USB bus in the header queue 120.

  The interrupt processing unit 330 processes an interrupt from the header addition circuit 100.

  The transfer control unit 340 controls the DMA 200 and the USB core 400.

  The data generation control unit 310, the header queue setting unit 320, the interrupt processing unit 330, and the transfer control unit 340 may be included in an application program that controls the transmission device 1.

  Next, the operation of the transmission apparatus 1 in the first embodiment of the present invention will be described.

  Here, the operation will be described by taking as an example the case of transmitting a video stream according to the USB Video Class (hereinafter referred to as UVC) isochronous transfer mode in USB 3.0 as data to be transmitted by the USB bus.

  FIG. 3 is a flowchart showing processing of the transmission apparatus 1 in the first embodiment of the present invention.

  The data generation control unit 310 on the CPU 300 instructs the data generation unit to generate video stream data (payload data including a time stamp and the like) and to store the generated data in the data storage unit 610 (step). A101). The data generation unit generates data and stores it in the data storage unit 610. Here, it is assumed that an address of an area in which data of the video stream is stored in the data storage unit 610 is set in advance in the data generation unit, and the data is stored in the area. Further, the address of the area where the video stream data is stored may be designated from the data generation control unit 310.

  For example, the data generation control unit 310 instructs generation and storage of data for two frames as a UVC video stream. The data generation unit generates two frames of 4098 data for one frame and stores them in the data storage unit 610. The data generation unit issues an interrupt (data generation completion interrupt) to the CPU 300.

  The header queue setting unit 320 sets the header and control information corresponding to the data transmitted through the USB bus in the header queue 120 (step A102).

  FIG. 4 is a diagram illustrating a setting example of the header queue 120 according to the first embodiment of this invention.

  In UVC, the header includes an FID (Frame Identifier) and an EOF (End Of Frame). The FID is a bit that toggles at 1/0 for each frame. The EOF is a bit indicating the last data of the frame. Here, since 4098 pieces of data are generated for each frame, the header queue setting unit 320 controls four types of headers (headers 1 to 4) having different FID and EOF values as shown in FIG. It is set in the header queue 120 together with information (number of repetitions). In FIG. 4, FID = 0 and EOF = 0 are set in the header 1, and the number of repetitions of the header 1 is 4097. In the header 2, FID = 0 and EOF = 1 are set, and the number of repetitions of the header 2 is 1. In the header 3, FID = 1 and EOF = 0 are set, and the number of repetitions of the header 3 is 4097. In the header 4, FID = 1 and EOF = 1 are set, and the number of repetitions of the header 4 is 1.

  For example, the header queue setting unit 320 sets the header and control information in FIG.

  The transfer control unit 340 instructs the DMA 200 to transfer a packet (step A103).

  For example, the transfer control unit 340 instructs transfer of packets of 4098 × 2 frames.

  The DMA 200 instructs the header addition circuit 100 to read data from the data storage unit 610 (step A301).

  The header merge circuit 110 of the header addition circuit 100 reads the header and control information in order from the header queue 120 (step A201).

  The header merge circuit 110 of the header addition circuit 100 reads data from the data storage unit 610 in order (step A202). Here, it is assumed that the header merge circuit 110 is preset with an address of an area where data of the video stream is stored in the data storage unit 610, and the header merge circuit 110 reads data from the area. Also, the address of the area where the video stream data is stored may be specified from the transfer control unit 340 via the DMA 200.

  The header merge circuit 110 adds a header to the read data and generates a packet (step A203).

  The header merge circuit 110 transmits the generated packet to the DMA 200 (step A204).

  The DMA 200 transfers the packet generated by the header merge circuit 110 to the USB core 400 (step A302).

  The USB core 400 transmits the packet transferred by the DMA 200 to the USB bus via the PHY chip 500 (step A401).

  The header merge circuit 110 repeats the processing from step A202 to A204 for the number of repetitions indicated by the control information (step A205).

  The header merge circuit 110 repeats the processing from step A201 to A205 for all the headers stored in the header queue 120 (step A206).

  Further, the DMA 200 repeats the process of step A302 until all the packets instructed by the transfer control unit 340 are transferred (step A303).

  FIG. 5 is a diagram illustrating an example of a packet transmitted from the transmission device 1 according to the first embodiment of the present invention.

  For example, the header merge circuit 110 reads the header 1 from the header queue 120 of FIG. 4, and adds the header 1 to the first 4097 pieces of data as shown in FIG. Next, the header merge circuit 110 reads the header 2 and adds the header 2 to the next piece of data. Further, the header merge circuit 110 reads the header 3 and adds the header 3 to the next 4097 pieces of data. The header merge circuit 110 reads the header 4 and adds the header 4 to the next piece of data.

  In this way, a header is added to the data for two frames, and the generated packet is transmitted to the USB bus.

  When processing has been completed for all headers stored in the header queue 120 (step A206 / Y), the header merge circuit 110 issues an interrupt (header completion interrupt) to the CPU 300 (step A207).

  When the interrupt processing unit 330 receives the header completion interrupt (step A104 / Y), the processing from step A101 is repeated.

  Thus, the operation of the first exemplary embodiment of the present invention is completed.

  Next, a characteristic configuration of the first exemplary embodiment of the present invention will be described. FIG. 1 is a block diagram showing a characteristic configuration of the first embodiment of the present invention.

  The transmission apparatus 1 includes a header merge circuit 110 (header merge unit) and a header queue 120 (header storage unit).

  The header queue 120 stores a header to be added to data in association with control information related to the header.

  The header merge circuit 110 sequentially acquires one or more pieces of data from the data storage unit 610 (data storage unit) in which one or more pieces of data are stored, and in accordance with the control information related to the header obtained from the header queue 120, Append the header to the acquired data and output it.

  According to the first embodiment of the present invention, data transfer can be speeded up with a small memory size. The reason is that the header queue 120 stores the header in association with the control information, and the header merge circuit 110 adds the header to the data acquired from the data storage unit 610 according to the control information.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  The second embodiment of the present invention is different from the first embodiment of the present invention in that the header to be applied is determined based on the header application conditions and priority.

  First, the configuration of the second exemplary embodiment of the present invention will be described.

  In the second embodiment of the present invention, the header queue 120 further stores application conditions and priorities of headers as control information. For example, an interrupt factor of an interrupt input to the header addition circuit 100 is set as the application condition. The header merge circuit 110 adds a header that matches the application condition and has a high priority to the data acquired from the data storage unit 610.

  Next, the operation of the transmission apparatus 1 in the second embodiment of the present invention will be described.

  Here, the operation will be described by taking as an example a case where three types of video streams D1, D2, and D3 having different priorities are transmitted on the USB bus. Assume that the priorities of these video streams are D1 <D3 <D2. In addition, when the video stream D1 is transmitted first and there is a transfer request for other video streams D2 and D3 from the outside of the transmission device 1, such as a USB host, the transmitted video stream is switched to the requested video stream. Assume that

  FIG. 6 is a flowchart showing processing of the transmission device 1 in the second embodiment of the present invention.

  The data generation control unit 310 instructs the data generation unit to generate video stream data and store the generated data in the data storage unit 610 (step B101). The data generation unit generates data and stores it in the data storage unit 610.

  For example, the data generation control unit 310 instructs generation and storage of data of the UVC video streams D1, D2, and D3. The data generation unit generates data of the video streams D1, D2, and D3 and stores the data in the data storage unit 610. The data generation unit issues an interrupt (data generation completion interrupt) to the CPU 300.

  The header queue setting unit 320 sets a header and control information corresponding to data transmitted through the USB bus in the header queue 120 (step B102).

  FIG. 8 is a diagram illustrating a setting example of the header queue 120 in the second embodiment of the present invention.

  In the example of FIG. 8, three headers 1 to 3 are set. The headers 1 to 3 correspond to the video streams D1 to D3, respectively. “None”, “3”, and “x times” are set in the application condition (interrupt factor), priority, and number of repetitions, which are the control information of the header 1, respectively. For the header 2, "switch request D2 (switch request to the video stream D2)", "1", and "y times" are set, respectively. For the header 3, "switching request D3 (switching request to the video stream D3)", "2", and "z times" are set, respectively. It is assumed that the lower the priority value, the higher the priority.

  For example, the header queue setting unit 320 sets the header and control information in FIG.

  The transfer control unit 340 instructs the DMA 200 to transfer a packet (step B103).

  For example, the transfer control unit 340 instructs transfer of the packets of the video streams D1, D2, and D3.

  The DMA 200 instructs the header addition circuit 100 to read data from the data storage unit 610 (step B301).

  The header merge circuit 110 of the header addition circuit 100 reads the header and control information from the header queue 120 (step B201). Here, the header merge circuit 110 determines a header having a higher priority among headers satisfying the application conditions as a header to be applied.

  The header merge circuit 110 of the header addition circuit 100 reads data from the data storage unit 610 in order (step B202). When the type of data to which the header is applied is different depending on the header determined in step B201 (for example, when the video stream is different), the header merge circuit 110 is set with the type of data to which the header is applied. Assume. In this case, the header merge circuit 110 reads data corresponding to the determined header. In this case, it is assumed that the header merge circuit 110 is preset with an address of an area in which various types of data are stored in the data storage unit 610, and the header merge circuit 110 reads data from the area. To do. Note that the address of an area in which various types of data are stored may be designated from the transfer control unit 340 via the DMA 200.

  The header merge circuit 110 adds a header to the read data and generates a packet (step B203).

  The header merge circuit 110 transmits the generated packet to the DMA 200 (step B204).

  The DMA 200 transfers the packet generated by the header merge circuit 110 to the USB core 400 (step B302).

  The USB core 400 transmits the packet transferred by the DMA 200 to the USB bus via the PHY chip 500 (step B401).

  The header merge circuit 110 repeats the processing from step B202 to B204 for the number of repetitions indicated by the control information (step B205).

  Further, the DMA 200 repeats the process of step A302 until all the packets instructed by the transfer control unit 340 are transferred (step B303).

  FIG. 7 is a flowchart showing interrupt processing of the header addition circuit 100 in the second embodiment of the present invention.

  Interrupt processing is performed when the header addition circuit 100 executes steps B201 to B205 described above, or when the interrupt processing is executed. Executed when entered. The interrupt is issued from the CPU 300 based on an instruction from an application on the CPU 300 when a transfer request for another video stream is input from the outside of the transmission device 1 such as a USB host.

  The header merge circuit 110 of the header addition circuit 100 reads the header and control information from the header queue 120 (step B251). Here, the header merge circuit 110 determines the header to be applied based on the application condition and the priority, as in step B201.

  Thereafter, similarly to steps B202 to B205, the header merge circuit 110 repeats the addition of the header for the number of repetitions indicated by the control information (steps B252 to B255).

  When the addition of the header for the number of repetitions is completed (step B255 / Y), the header merge circuit 110 returns from the interrupt process (step B256), and resumes the process that was being executed before the interrupt.

  FIG. 9 is a diagram illustrating an example of a packet transmitted from the transmission device 1 according to the second embodiment of the present invention.

  Here, it is assumed that D1, D2, and D3 are preset in the header merge circuit 110 as video streams to which the headers D1, D2, and D3 are applied, respectively.

  For example, at the first time, no interrupt is input to the header addition circuit 100. In this case, among the headers set in the header queue 120 in FIG. 8, the header satisfying the application condition is the header 1 corresponding to the interrupt factor “none”. Therefore, the header merge circuit 110 determines the header 1 as an applicable header. Then, the header merge circuit 110 adds the header 1 to the x pieces of data of the video stream D1, as shown in FIG.

  Next, it is assumed that an interrupt of the interrupt factor “transfer request D3” is input to the header addition circuit 100 when xm packets of the video stream D1 are transferred. In this case, the headers that satisfy the application conditions are the header 1 corresponding to the interrupt factor “none” and the header 3 corresponding to the interrupt factor “transfer request D3”. In the header merge circuit 110, the header 3 having a high priority is determined as the header to be applied. Then, the header merge circuit 110 adds the header 3 to z pieces of data of the video stream D3.

  Further, it is assumed that an interrupt of an interrupt factor “transfer request D2” is input to the header addition circuit 100 when z−n packets of the video stream D3 are transferred. In this case, the header that satisfies the application conditions is header 1 corresponding to the interrupt factor “none”, header 3 corresponding to the interrupt factor “transfer request D3”, and header corresponding to the interrupt factor “transfer request D2”. 2. In the header merge circuit 110, the header 2 having a high priority is determined as the header to be applied. Then, the header merge circuit 110 adds the header 2 to y pieces of data of the video stream D2.

  When the transfer of y packets of the video stream D2 is completed, the header merge circuit 110 adds the header 3 to the remaining n pieces of data of the video stream D3.

  When the transfer of z packets of the video stream D3 is completed, the header merge circuit 110 adds the header 1 to the remaining m pieces of data of the video stream D1.

  In this manner, the packets of the video streams D1, D2, and D3 are transmitted to the USB bus in response to the transfer request.

  Thus, the operation of the second exemplary embodiment of the present invention is completed.

  Note that the headers 1 to 3 in the header queue 120 may be further classified and set into a plurality of headers according to values such as FID and EOF as described in the first embodiment.

  Further, in the second embodiment of the present invention, the case where the headers of different video streams are switched according to the transfer request has been described as an example. However, if the headers are switched according to the application conditions of the control information, for example, You may apply to other cases, such as switching a header by the same video stream.

  In addition to the transfer request, the interrupt factor may be other factors such as switching of the type of the video stream detected in the transmission device 1 or a transfer stop request input from the outside of the transmission device 1.

  According to the second embodiment of the present invention, different types of headers can be applied while performing high-speed data transfer. The reason is that the control information includes an application condition related to the header, and the header merge circuit 110 adds a header that satisfies the application condition to the data acquired from the data storage unit 610.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 100 Header addition circuit 110 Header merge circuit 120 Header queue 200 DMA
300 CPU
310 Data Generation Control Unit 320 Header Queue Setting Unit 330 Interrupt Processing Unit 340 Transfer Control Unit 400 USB Core 500 PHY Chip 600 RAM
610 Data storage unit

Claims (10)

Header information storage means for storing a header to be assigned to data in association with control information related to the header;
Each of the one or more data is sequentially acquired from a data storage unit storing one or more data, and the header is added to the acquired data according to the control information relating to the header acquired from the header information storage unit And header merging means for outputting,
A transmission device comprising: The header information storage means stores each of the one or more headers in association with control information related to the header,
The control information includes the number of data to which a header corresponding to the control information is to be added,
The header merging unit sequentially acquires each of the one or more headers from the header information storage unit, and acquires the number of data related to the acquired header in the data acquired sequentially from the data storage unit. Add header,
The transmission device according to claim 1. The header information storage means stores each of the one or more headers in association with control information related to the header,
The control information includes a condition for adding a header corresponding to the control information, and the number of data.
The header merge means acquires a header satisfying the condition of the control information among the one or more headers stored in the header information storage means, and the data storage means of the number of data related to the acquired header Add the acquired header to the data acquired in order from
The transmission device according to claim 1. The control information further includes a priority of a header corresponding to the control information,
The header merging means acquires a header having a higher priority than other headers among the headers satisfying the condition of the control information.
The transmission device according to claim 3. The condition to be given the header includes an interrupt factor,
The header merging means switches a header to be given to data acquired from the data storage means to a header corresponding to the interrupt factor of the interrupt when an interrupt occurs.
The transmission device according to claim 3 or 4. Store the header to be attached to the data in association with the control information related to the header,
Sequentially acquiring each of the one or more data from a data storage means in which one or more data is stored, adding the header to the acquired data according to the control information relating to the acquired header, and outputting the data,
With a transmission method. When storing the header to be given to the data, each of the one or more headers is stored in association with the control information related to the header,
The control information includes the number of data to which a header corresponding to the control information is to be added,
When adding the header, each of the one or more headers is acquired in order, and the acquired header is added to the data acquired in order from the data storage unit of the number of data related to the acquired header.
The transmission method according to claim 6. When storing the header to be given to the data, each of the one or more headers is stored in association with the control information related to the header,
The control information includes a condition for adding a header corresponding to the control information, and the number of data.
When adding the header, the header that satisfies the condition of the control information among the one or more headers is acquired, and the number of data related to the acquired header is sequentially acquired from the data storage unit, Add the obtained header,
The transmission method according to claim 6. The control information further includes a priority of a header corresponding to the control information,
When adding the header, among the headers that satisfy the condition of the control information, obtain a header having a higher priority than other headers,
The transmission method according to claim 8. The condition to be given the header includes an interrupt factor,
In the case of adding the header, when an interrupt occurs, the header given to the data acquired from the data storage means is switched to the header corresponding to the interrupt factor of the interrupt,
The transmission method according to claim 8 or 9.

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