JP2000223489A - Wiring material and conductor wiring layer employing the same - Google Patents
Wiring material and conductor wiring layer employing the sameInfo
- Publication number
- JP2000223489A JP2000223489A JP2711599A JP2711599A JP2000223489A JP 2000223489 A JP2000223489 A JP 2000223489A JP 2711599 A JP2711599 A JP 2711599A JP 2711599 A JP2711599 A JP 2711599A JP 2000223489 A JP2000223489 A JP 2000223489A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- wiring
- wiring material
- alloy
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路等
の配線層に使用される再配線材料及び導体配線層に関す
る。The present invention relates to a rewiring material and a conductor wiring layer used for a wiring layer of a semiconductor integrated circuit or the like.
【０００２】[0002]
【従来の技術】従来、半導体集積回路等の配線層の配線
材料として下記の材料を使って導体配線層を形成してい
た。Ａｌ単体或いはＡｌ−Ｓｉ、Ａｌ−Ｃｕ−Ｓｉ等の
Ａｌ合金、Ｗ或いはＷ−Ｔｉ等のＷ合金、Ｃｕ−Ａｌ、
Ｃｕ−Ｓｉ、Ｃｕ−Ｔｉ、Ｃｕ−Ｚｎ、Ｃｕ−Ｓｎ，Ｃ
ｕ−Ｎｉ等の銅合金をスパッタ或いはＣＶＤにより導電
薄膜を形成し、パターニング処理して導体配線層を形成
していた。2. Description of the Related Art Conventionally, conductor wiring layers have been formed using the following materials as wiring materials for wiring layers of semiconductor integrated circuits and the like. Al alone or Al-Si, Al alloy such as Al-Cu-Si, W or W alloy such as W-Ti, Cu-Al,
Cu-Si, Cu-Ti, Cu-Zn, Cu-Sn, C
A conductive thin film is formed from a copper alloy such as u-Ni by sputtering or CVD, and is patterned to form a conductive wiring layer.
【０００３】しかし、上記配線材料の中で特にＡｌまた
はＡｌ合金及びＣｕまたはＣｕ合金を使った導体配線層
ではエレクトロマイグレーションによる断線が発生する
という問題がある。[0003] However, among the above-mentioned wiring materials, particularly, in a conductor wiring layer using Al or an Al alloy and Cu or a Cu alloy, there is a problem that disconnection due to electromigration occurs.
【０００４】ＷまたはＷ合金及びＣｕ−Ａｌ、Ｃｕ−Ｓ
ｉ等の銅合金からなる配線材料で導体配線層を形成した
場合配線抵抗が高くなるという問題がある。[0004] W or W alloy and Cu-Al, Cu-S
When the conductor wiring layer is formed of a wiring material made of a copper alloy such as i, there is a problem that the wiring resistance is increased.
【０００５】また、ＡｌまたはＡｌ合金及びＣｕまたは
Ｃｕ合金からなる導体配線層の表面または裏面にＷまた
はＷ合金からなる薄膜層を被接させ、上記エレクトロマ
イグレーションを防止する試みがなされているが、この
構成では配線抵抗が大きくなるという問題があり、さら
に材料、工程が増えるためコストの点で好ましくない。Attempts have been made to prevent the above electromigration by contacting a thin film layer made of W or a W alloy on the front or back surface of a conductor wiring layer made of Al or an Al alloy and Cu or a Cu alloy. In this configuration, there is a problem that the wiring resistance is increased, and furthermore, the number of materials and steps are increased, which is not preferable in terms of cost.
【０００６】さらにまた、Ａｌ、Ａｌ合金、Ｗ、Ｗ合
金、Ｃｕ、Ｃｕ合金からなる配線層のの表面は酸化しや
すく電気的コンタクト抵抗が増加するという問題もあ
る。Furthermore, there is a problem that the surface of the wiring layer made of Al, Al alloy, W, W alloy, Cu, Cu alloy is easily oxidized and the electrical contact resistance increases.
【０００７】[0007]
【発明が解決しようとする課題】本発明は上記問題点に
鑑みなされたもので、耐エレクトロマイグレーション性
を有し、且つ導電性の優れた配線層及び配線材料を提供
することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a wiring layer and a wiring material having electromigration resistance and excellent conductivity.
【０００８】[0008]
【課題を解決するための手段】本発明において上記問題
を解決するために、鋭意検討した結果Ａｇ元素にＡｕ元
素を添加したＡｇ−Ａｕ系合金配線材料を使った導体配
線層が耐エレクトロマイグレーション性と導電性に優れ
ていることを見出した。Means for Solving the Problems In order to solve the above-mentioned problems in the present invention, as a result of intensive studies, a conductor wiring layer using an Ag-Au-based alloy wiring material in which an Au element is added to an Ag element has an electromigration resistance. And excellent conductivity.
【０００９】具体的には、まず請求項１においては、半
導体集積回路等の配線層に使用される配線材料であっ
て、前記配線材料がＡｇ−Ａｕ系合金からなることを特
徴とする配線材料としたものである。More specifically, first, in claim 1, a wiring material used for a wiring layer of a semiconductor integrated circuit or the like, wherein the wiring material is made of an Ag-Au alloy. It is what it was.
【００１０】また、請求項２においては、前記Ａｇ−Ａ
ｕ系合金のＡｕの添加量が０.２〜４.０ａt％であるこ
とを特徴とする請求項１に記載の配線材料としたもので
ある。Further, in the second aspect, the Ag-A
2. The wiring material according to claim 1, wherein the amount of Au added to the u-based alloy is 0.2 to 4.0 at%.
【００１１】さらにまた、請求項３においては、請求項
１または２に記載の配線材料を用いて配線層を形成した
ことを特徴とする導体配線層としたものである。According to a third aspect of the present invention, there is provided a conductive wiring layer wherein a wiring layer is formed using the wiring material according to the first or second aspect.
【００１２】[0012]
【発明の実施の形態】以下本発明の実施の形態につき説
明する。一般にＡｇ単体配線材料を用いた導体配線層は
エレクトロマイグレーションによりＡｇが移動しやすく
断線不良を生じやすい特性を有している。しかしなが
ら、本発明ではＡｇ元素の導電性を生かしてＡｇ合金系
でエレクトロマイグレーションを防止する材料を見いだ
した。Ａｇへの添加元素は移動しやすいＡｇの動きを抑
制する観点からはＰｂ、Ａｕ、Ｐｔ等の重い元素が、導
電性を期待する観点からはＡｇ、Ａｕ、Ｎｉ、Ｚｎ、Ａ
ｌ等の元素が好ましく、両者を満足する元素としてＡｕ
元素が最も好ましいことが判明した。これは、Ａｇに重
金属を添加することによりＡｇの動きを抑制し、さらに
Ａｕは電気抵抗が小さい良導体であり、かつ最外周の電
子配置がＡｇと同様であるため合金化した際に導電性を
低下させ難いためである。Embodiments of the present invention will be described below. In general, a conductor wiring layer using a single Ag wiring material has a characteristic that Ag easily moves due to electromigration and a disconnection failure easily occurs. However, the present invention has found a material that prevents electromigration in an Ag alloy system by utilizing the conductivity of the Ag element. The element added to Ag is a heavy element such as Pb, Au, or Pt from the viewpoint of suppressing the movement of Ag which is likely to move, and Ag, Au, Ni, Zn, A from the viewpoint of expecting conductivity.
l and the like are preferable, and as an element satisfying both, Au
Elements have been found to be most preferred. This suppresses the movement of Ag by adding a heavy metal to Ag, and furthermore, Au is a good conductor having a small electric resistance, and the outermost electron arrangement is the same as that of Ag. This is because it is difficult to lower.
【００１３】Ａｕの添加量を多くすると導体配線層の電
気抵抗が大きくなり、少なすぎるとＡｇの動きを抑制す
る効果が小さくなり、Ａｕの添加量は０.２〜４.０ａt
％の範囲が好ましく、この範囲でＡｕを添加したＡｇ−
Ａｕ系合金配線材料で配線層を形成した場合、得られた
配線層は耐エレクトロマイグレーション性に優れ、且つ
配線抵抗も低い特性を示す。When the amount of added Au is increased, the electric resistance of the conductor wiring layer is increased, and when the amount is too small, the effect of suppressing the movement of Ag is reduced, and the amount of added Au is 0.2 to 4.0 at.
% Is preferable, and in this range, Ag-
When the wiring layer is formed of an Au-based alloy wiring material, the obtained wiring layer has excellent electromigration resistance and low wiring resistance.
【００１４】[0014]
【実施例】以下実施例により本発明を詳細に説明する。
図１はＩＣチップ上に本発明のＡｇ−Ａｕ系合金配線材
料を用いて配線層を形成したウェハーレベルパッケージ
の一実施例を示す断面図である。図２（ａ）〜（ｅ）は
ＩＣチップ上に本発明のＡｇ−Ａｕ系合金配線材料を用
いて配線層を形成したウェハーレベルパッケージの一実
施例を工程順に示す断面図である。The present invention will be described in detail with reference to the following examples.
FIG. 1 is a sectional view showing an embodiment of a wafer level package in which a wiring layer is formed on an IC chip by using the Ag-Au-based alloy wiring material of the present invention. 2A to 2E are cross-sectional views showing one embodiment of a wafer-level package in which a wiring layer is formed on an IC chip using the Ag-Au-based alloy wiring material of the present invention in the order of steps.
【００１５】まず、Ｓｉウェハー１１にＡｌ電極パッド
１２及びパッシベーション層１３が形成されたＩＣチッ
プ１０を用意する（図２（ａ）参照）。First, an IC chip 10 having an Al electrode pad 12 and a passivation layer 13 formed on a Si wafer 11 is prepared (see FIG. 2A).
【００１６】次に、上記ＩＣチップ１０上にスパッタ法
にて膜厚２０００ÅのバリアメタルＴｉＮ膜を、さら
に、Ａｕの添加量を０、０.２、０.５、１.０、２.０、
４.０、４.５、５.０at％（原子パーセント）の範囲で
変化させたＡｇ−Ａｕ系合金配線材料を用いてスパッタ
法にて膜厚５０００Åの導電膜を形成し、公知のフォト
エッチング方を用いてパターニング処理して導体配線層
１４を形成した（図２（ｂ）参照）。なお、導電膜の形
成方法としては本実施例ではスパッタリング法を用いた
が、真空蒸着法、イオンプレーティング法、ＣＶＤ法、
ゾルゲル法等いかなる方法でも良く、適宜選択されるも
のである。Next, a barrier metal TiN film having a thickness of 2000 .ANG. Is formed on the IC chip 10 by a sputtering method, and Au is added in an amount of 0, 0.2, 0.5, 1.0, 2.0. ,
A conductive film having a thickness of 5000 ° is formed by a sputtering method using an Ag—Au-based alloy wiring material changed in a range of 4.0, 4.5, and 5.0 at% (atomic percent), and is then subjected to known photoetching. The conductor wiring layer 14 was formed by patterning using the other method (see FIG. 2B). Although a sputtering method was used in this embodiment as a method for forming the conductive film, a vacuum evaporation method, an ion plating method, a CVD method,
Any method such as a sol-gel method may be used, and is appropriately selected.
【００１７】次に、導体配線層１４の所定位置にセミア
ディティブ法にてメタルポスト１５を形成した（図２
（ｃ）参照）。Next, metal posts 15 are formed at predetermined positions of the conductor wiring layer 14 by a semi-additive method.
(C)).
【００１８】次に、封止樹脂１６にてメタルポスト１５
を除いて樹脂モールドした（図２（ｄ）参照）。Next, a metal post 15 is formed with a sealing resin 16.
And resin molding (see FIG. 2D).
【００１９】最後に、メタルポスト１５に半田ボール１
７を形成してウェハーレベルパッケージ２０を得た（図
２（ｅ）参照）。Finally, solder balls 1 are placed on metal posts 15.
7 was formed to obtain a wafer level package 20 (see FIG. 2E).
【００２０】ここで、上記８種類の配線層で形成したウ
ェハーレベルパッケージ２０を温度２００℃、電流密度
１×１０7Ａ／ｃｍ2の高温通電試験を５００時間実施し
た結果を表１に示す。[0020] Here, it is shown above eight temperature 200 ° C. The wafer-level package 20 formed in the wiring layer, the current density 1 × 10 7 A / cm result of performing 500 hours burn-test 2 in Table 1.
【００２１】[0021]
【表１】 [Table 1]
【００２２】表１の結果からも分かるように、Ａｕの添
加量が０.２at％以上では導体配線層の断線は発生せ
ず、良好な耐エレクトロマイグレーション性を示すこと
が確認された。すなわち、Ａｕを添加したことにより導
体配線層のＡｇが動きにくくなりエレクトロマイグレー
ションに対する信頼性が向上したことになる。また、Ａ
ｕの添加量が０at％のサンプルではエレクトロマイグレ
ーションによる配線層の断線が発生し、耐エレクトロマ
イグレーション性がないことが確認された。As can be seen from the results shown in Table 1, when the added amount of Au is 0.2 at% or more, no disconnection of the conductor wiring layer occurs, and it is confirmed that good electromigration resistance is exhibited. In other words, the addition of Au implies that the Ag of the conductor wiring layer is less likely to move and the reliability against electromigration is improved. Also, A
In the sample in which the addition amount of u was 0 at%, disconnection of the wiring layer due to electromigration occurred, and it was confirmed that there was no electromigration resistance.
【００２３】さらに、Ａｇ−Ａｕ系合金配線材料のＡｕ
添加量が導体配線層の電気抵抗に及ぼす影響について調
べた。電気抵抗は導体配線層の表面抵抗を４端針式電気
抵抗測定器を用いて測定した。その測定結果を図３に示
す。Further, the Au—Au-based alloy wiring material Au
The effect of the added amount on the electrical resistance of the conductor wiring layer was examined. The electric resistance was measured by measuring the surface resistance of the conductor wiring layer using a four-point needle electric resistance meter. FIG. 3 shows the measurement results.
【００２４】図３に示すように、Ａｕの添加量が４at％
を超えると急激に電気抵抗が増加することが確認され
た。As shown in FIG. 3, the amount of Au added was 4 at%.
It was confirmed that the electrical resistance sharply increased when the value exceeded.
【００２５】以上の結果から、耐エレクトロマイグレー
ション性及び導電性を満足すＡｇ−Ａｕ系合金配線材料
のＡｕの添加量は０.２〜４.０at％の範囲が良好である
ことが確認された。From the above results, it has been confirmed that the addition amount of Au in the Ag-Au alloy wiring material satisfying the electromigration resistance and the conductivity is preferably in the range of 0.2 to 4.0 at%. .
【００２６】さらに、Ａｇ−Ａｕ系合金配線材料を用い
て形成した導体配線層の熱処理前後での表面酸化状態に
ついて調べた。Further, the surface oxidation state of the conductor wiring layer formed using the Ag-Au alloy wiring material before and after the heat treatment was examined.
【００２７】Ａｇ−Ａｕ系合金配線材料を用いて形成し
た導体配線層の加熱(３００℃×１ｈ)前後における表面
状態をＸ線光電子分光装置（ＶＧ Scientific社製：Ｅ
ＳＣＡＬＡＢ−２２０ＩＸＬ）を用いて以下の条件にて
測定した。 Ｘ線源：Ａｌ Ｋα モノクロＸ線（出力＝２００Ｗ） ＣＡＥ＝１０ｅＶ、Ｓｔｅｐ＝５０ｍｅＶ 測定レンズモード：ＬargeＡrea ＸＬ（約６００μｍφ
の面積を測定）The surface state of the conductor wiring layer formed using the Ag-Au alloy wiring material before and after heating (300 ° C. × 1 h) was measured using an X-ray photoelectron spectrometer (VG Scientific: E
(SCALAB-220IXL) under the following conditions. X-ray source: Al Kα Monochrome X-ray (output = 200 W) CAE = 10 eV, Step = 50 meV Measurement lens mode: Large Area XL (about 600 μmφ)
Measure the area of
【００２８】Ａｕを１.０at％添加したＡｇ−Ａｕ系合
金配線材料を用いてスパッタ法にて形成した膜厚１００
０Åの導電膜サンプルをＸ線光電子分光装置にて分析
し、加熱前におけるＸ線光電子分光スペクトルのＡｇ３
ｄ５／２ピークに関する波形分離結果を図４に示す。さ
らに、このサンプルを３００℃×１時間加熱後のＸ線光
電子分光スペクトル分析結果のＡｇ３ｄ５／２ピークに
関する波形分離結果を図５に示す。いずれも１本のピー
クにフィットされピーク幅(０．４９〜０．５１ｅＶ)、
ピーク位置（３６８．０ｅＶ）はＡｇ単体のピーク位置
(日本電子ＸＰＳハンドブック)と良く一致している。す
なわち、３００℃×１時間の加熱処理を施しても酸化さ
れていないことを示し、Ａｕを添加したＡｇ−Ａｕ系合
金配線材料を用いて形成した導電膜は酸化され難いと言
える。A film thickness of 100 formed by sputtering using an Ag-Au alloy wiring material containing 1.0 at% of Au.
A 0 ° conductive film sample was analyzed with an X-ray photoelectron spectrometer, and the Ag3 of the X-ray photoelectron spectroscopy spectrum before heating was analyzed.
FIG. 4 shows the waveform separation result for the d5 / 2 peak. FIG. 5 shows the results of waveform separation on the Ag3d5 / 2 peak in the results of X-ray photoelectron spectroscopy after heating the sample at 300 ° C. for 1 hour. Both are fit to one peak and the peak width (0.49 to 0.51 eV),
The peak position (368.0 eV) is the peak position of Ag alone.
(JEOL XPS Handbook). In other words, it shows that the film is not oxidized even after the heat treatment at 300 ° C. × 1 hour, and it can be said that the conductive film formed using the Ag-Au alloy wiring material to which Au is added is hardly oxidized.
【００２９】一方、Ａｕを添加しないＡｇ単体配線材料
を用いてスパッタ法にて形成した膜厚１０００Åの導電
膜サンプルを同様にＸ線光電子分光装置にて分析し、加
熱前におけるＸ線光電子分光スペクトルのＡｇ３ｄ５／
２ピークに関する波形分離結果を図６に示す。さらに、
このサンプルを３００℃×１時間加熱後のＸ線光電子分
光スペクトルのＡｇ３ｄ５／２ピークに関する波形分離
結果を図７に示す。図７のピークは３本に分離され各ピ
ークの位置は３６８.３ｅＶ、３６８.０ｅＶ、３６７.
４ｅＶとなりそれぞれ、Ａｇ2Ｏ、Ａｇ単体、ＡｇＯの
ピーク位置(日本電子ＸＰＳハンドブック)と良く一致し
ている。すなわち、３００℃×１時間の加熱処理を施す
ことにより酸化されていることを示し、Ａｕを添加しな
いＡｇ単体配線材料を用いて形成した導電膜は酸化され
やすいと言える。On the other hand, a conductive film sample having a thickness of 1000 Å formed by a sputtering method using an Ag single wiring material to which Au was not added was similarly analyzed by an X-ray photoelectron spectrometer, and the X-ray photoelectron spectroscopic spectrum before heating was obtained. Ag3d5 /
FIG. 6 shows the waveform separation results for the two peaks. further,
FIG. 7 shows the results of waveform separation on the Ag3d5 / 2 peak of the X-ray photoelectron spectroscopy spectrum after heating this sample at 300 ° C. × 1 hour. The peak in FIG. 7 is separated into three peaks, and the position of each peak is 368.3 eV, 368.0 eV, 366.7 eV.
4 eV, which are in good agreement with the peak positions of Ag 2 O, Ag alone, and AgO, respectively (JEOL XPS Handbook). In other words, the heat treatment at 300 ° C. for 1 hour indicates that the conductive film is oxidized, and it can be said that the conductive film formed using the Ag single wiring material to which Au is not added is easily oxidized.
【００３０】[0030]
【発明の効果】本発明によれば、Ａｇ−Ａｕ系合金配線
材料を用いてＩＣチップ上に導体配線層を形成すること
により、耐エレクトロマイグレーション性及び導電性に
優れたウェハーレベルパッケージが得られる。また、Ａ
ｇ−Ａｕ系合金配線材料を用いて形成した導体配線層は
耐熱性を有しているため、半導体集積回路、ビルドアッ
プ多層配線板の導体配線層及びビアホール形成用の配線
材料としても好適である。According to the present invention, a wafer level package having excellent electromigration resistance and conductivity can be obtained by forming a conductive wiring layer on an IC chip using an Ag-Au alloy wiring material. . Also, A
Since the conductor wiring layer formed using the g-Au-based alloy wiring material has heat resistance, it is also suitable as a semiconductor integrated circuit, a conductor wiring layer of a build-up multilayer wiring board, and a wiring material for forming via holes. .
【図１】ＩＣチップ上に本発明のＡｇ−Ａｕ系合金配線
材料を用いて導体配線層を形成したウェハーレベルパッ
ケージの一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a wafer level package in which a conductor wiring layer is formed on an IC chip by using the Ag—Au alloy wiring material of the present invention.
【図２】（ａ）〜（ｅ）は、ウェハーレベルパッケージ
の一実施例の製造工程を工程順に示す断面図である。FIGS. 2A to 2E are cross-sectional views illustrating a manufacturing process of an embodiment of a wafer level package in the order of processes.
【図３】本発明のＡｇ−Ａｕ系合金配線材料を用いて形
成した導体配線層のＡｕ添加量に対する電気抵抗の変化
を示す説明図である。FIG. 3 is an explanatory diagram showing a change in electric resistance with respect to an added amount of Au in a conductive wiring layer formed using the Ag—Au-based alloy wiring material of the present invention.
【図４】Ａｕを１at％添加したＡｇ−Ａｕ系合金配線材
料を用いて形成した導電膜をＸ線光電子分光装置にて分
析した結果を示す説明図である。FIG. 4 is an explanatory diagram showing a result of analyzing a conductive film formed using an Ag—Au alloy wiring material to which 1 at% of Au is added by an X-ray photoelectron spectrometer.
【図５】Ａｕを１at％添加したＡｇ−Ａｕ系合金配線材
料を用いて形成した導電膜を３５０℃１時間加熱した後
Ｘ線光電子分光装置にて表面分析した結果を示す説明図
である。FIG. 5 is an explanatory diagram showing the results of surface analysis performed by an X-ray photoelectron spectrometer after heating a conductive film formed using an Ag-Au-based alloy wiring material containing 1 at% of Au at 350 ° C. for 1 hour.
【図６】Ａｇ単体配線材料を用いて形成した導電膜をＸ
線光電子分光装置にて表面分析した結果を示す説明図で
ある。FIG. 6 shows that a conductive film formed by using an Ag simple wiring material is formed of X
It is explanatory drawing which shows the result of having performed the surface analysis with the linear photoelectron spectroscopy apparatus.
【図７】Ａｇ単体配線材料を用いて形成した導電膜を３
５０℃１時間加熱した後Ｘ線光電子分光装置にて表面分
析した結果を示す説明図である。FIG. 7 shows a conductive film formed by using a single Ag wiring material.
It is explanatory drawing which shows the result of surface analysis with the X-ray photoelectron spectroscopy after heating at 50 degreeC for 1 hour.
１０……ＩＣチップ １１……Ｓｉウェハー １２……Ａｌ電極パッド １３……パッシベーション層 １４……導体配線層 １５……メタルポスト １６……封止樹脂 １７……半田ボール ２０……ウェハーレベルパッケージ Reference Signs List 10 IC chip 11 Si wafer 12 Al electrode pad 13 Passivation layer 14 Conductor wiring layer 15 Metal post 16 Sealing resin 17 Solder ball 20 Wafer level package
Claims (3)
線材料であって、前記配線材料がＡｇ−Ａｕ系合金から
なることを特徴とする配線材料。1. A wiring material used for a wiring layer of a semiconductor integrated circuit or the like, wherein the wiring material is made of an Ag-Au alloy.
０.２〜４.０ａt％であることを特徴とする請求項１に
記載の配線材料。2. The wiring material according to claim 1, wherein the amount of Au added to the Ag—Au alloy is 0.2 to 4.0 at%.
て配線パターンを形成したことを特徴とする導体配線
層。3. A conductive wiring layer, wherein a wiring pattern is formed using the wiring material according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2711599A JP2000223489A (en) | 1999-02-04 | 1999-02-04 | Wiring material and conductor wiring layer employing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2711599A JP2000223489A (en) | 1999-02-04 | 1999-02-04 | Wiring material and conductor wiring layer employing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000223489A true JP2000223489A (en) | 2000-08-11 |
Family
ID=12212081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2711599A Pending JP2000223489A (en) | 1999-02-04 | 1999-02-04 | Wiring material and conductor wiring layer employing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000223489A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009014448A (en) * | 2007-07-03 | 2009-01-22 | Yamaha Corp | Magnetic sensor and its manufacturing method |
| US7851237B2 (en) | 2007-02-23 | 2010-12-14 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US7858406B2 (en) | 2007-02-06 | 2010-12-28 | Infineon Technologies Ag | Semiconductor device test structures and methods |
-
1999
- 1999-02-04 JP JP2711599A patent/JP2000223489A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7858406B2 (en) | 2007-02-06 | 2010-12-28 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US8633482B2 (en) | 2007-02-06 | 2014-01-21 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US9188625B2 (en) | 2007-02-06 | 2015-11-17 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US7851237B2 (en) | 2007-02-23 | 2010-12-14 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| US8847222B2 (en) | 2007-02-23 | 2014-09-30 | Infineon Technologies Ag | Semiconductor device test structures and methods |
| JP2009014448A (en) * | 2007-07-03 | 2009-01-22 | Yamaha Corp | Magnetic sensor and its manufacturing method |
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