JP2000223392A - Method and apparatus for electron beam lithography - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deflectional deviation of an electron beam for improving the writing positional accuracy by correcting the field magnification factor change due to the resist surface potential. SOLUTION: A step 1 of calculating stored charge quantity per chip from a desired pattern writing ratio and an effective dosage is executed to write a pattern 2 and is followed by a step 2 of writing a pattern on a chip 1, step 3 of calculating the field magnification factor change ΔR(i-1, i) of a chip i from a chip i-1, step 4 of feeding back the change ΔR(i-1, i) to a lithography apparatus, and step 5 of correcting the deflection voltage of this apparatus so that the offset value ΔR(i-1, i)=0. Next, in the patterning operation, corrections are made, starting from step 3 to write again a pattern on the next chip, and this is repeated until patterns are written on all the chips. Thus, the charge up is prevented effectively, without providing a conductive film, etc., on a photoresist to be exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electron beam lithography method and an electron beam lithography apparatus. The present invention relates to, for example, UL
The present invention provides an electron beam lithography method and an electron beam lithography apparatus which can be used as a means for performing electron beam lithography at a high precision when an electron beam lithography technique is used for the manufacture of miniaturized semiconductor devices such as SI. is there.

[0002]

2. Description of the Related Art Position accuracy deterioration due to the influence of charging in electron beam drawing is well known as a charge-up phenomenon. Since electrons have negative charges, the trajectories of successively incident electron beams are bent by an electric field generated by the staying charges, and a shift from a desired position occurs. Acceleration voltage 50
The charge-up phenomenon at kV has not so far been reported so far.
In patterning the ULSI fine circuit according to the rule, the pattern may be a factor of positional accuracy error such as pattern connection and alignment accuracy, and it is considered that the pattern has come to an area that can no longer be ignored.

As a measure for preventing charge-up, a method of providing a conductive film on a resist is generally used. By keeping the conductive film at the ground potential, even if electrons stay in the resist, the electric field does not leak outside due to the electrostatic shielding effect. Recently, conductive films have been commercially available from, for example, a plurality of chemical material manufacturers and have become available. However, when such a conductive film is used, there are problems that the process becomes complicated and that the resolution of the resist may be deteriorated due to the occurrence of interface mixing with the conductive film.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is intended to provide a charge-up preventing means which does not require a conductive film and can be effectively applied with only a single resist film. It is. That is, an object of the present invention is to prevent charge-up effectively without providing a conductive film on a resist to be exposed, thereby preventing the influence of charge-up occurrence without problems such as deterioration in resolution of the resist. An object of the present invention is to provide a line drawing method and an electron beam drawing apparatus.

[0005]

According to the present invention, there is provided an electron beam lithography method, comprising: a photoresist (for example, a chemically amplified resist);
An electron beam lithography method for patterning by electron beam lithography using a mask as a mask includes a step of correcting a change in field magnification due to a resist surface potential.

According to the present invention, by correcting the amount of change in the field magnification caused by the resist surface potential,
The deflection deviation of the electron beam can be suppressed, and the drawing position accuracy can be improved. Therefore, even if there is charge-up or the like and the resist surface potential changes, the amount of change in the field magnification is corrected, so that proper exposure can be achieved without necessarily requiring a conductive film, and accuracy can be improved. is there.

Further, according to the electron beam writing method of the present invention, in the electron beam writing method of performing patterning by electron beam writing using a photoresist as a mask, the correlation between the accumulated charge amount on the resist surface and the field magnification change amount of the writing chip is provided. The configuration includes a step of converting the relationship into a function.

In an electron beam lithography apparatus according to the present invention, there is provided an electron beam lithography apparatus which performs patterning by electron beam lithography using a photoresist as a mask. A configuration having a functioning mechanism for functioning the relationship is adopted.

In these inventions, even if the resist surface potential changes due to charge-up or the like, proper exposure can be achieved by correcting the amount of change in the field magnification.
Accuracy can be improved. Such an effect can be obtained without necessarily using a conductive film.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, and specific preferred embodiments of the present invention will be described. However, it goes without saying that the present invention is not limited to the embodiment described and illustrated below.

Basically, according to the present invention, a fine circuit such as a semiconductor integrated circuit is formed by electron beam lithography using a resist as a mask.
At the time of patterning, the amount of change in the field magnification caused by the resist surface potential is corrected, thereby suppressing the deflection deviation of the electron beam and improving the drawing position accuracy.

More specifically, for example, the correlation between the field magnification and the resist accumulated charge in the electron beam-photo alignment evaluation is preferably measured using a mask in which a positioning portion such as an alignment mark is dug by a stepper (projection exposure apparatus). The relationship is formed into a function, and the function is fed back to the drawing apparatus so as to improve the drawing accuracy.
Hereinafter, specific embodiments will be described.

Embodiment 1 In this embodiment, when patterning is performed by electron beam lithography using a photoresist as a mask, the correlation between the amount of accumulated charge on the resist surface and the amount of field magnification change of the lithography chip is determined. Make it a function. If such a function can be realized, it is possible to correct the field magnification change caused by the resist surface potential. Therefore, according to the present embodiment, when a fine circuit pattern of a semiconductor device circuit is patterned by an electron beam lithography apparatus having an electrostatic chuck stage using a resist, for example, a chemically amplified resist as a mask, it is caused by the resist surface potential. It is possible to correct the field magnification change amount. If drawing is performed based on such correction, it is possible to suppress deflection deviation of the electron beam and improve drawing position accuracy. In this embodiment, the processing up to the functioning of the correlation is performed.

Prior to the description of the function, an experiment for actually examining the degree of positional accuracy deterioration caused by resist charge-up when electron beam drawing is performed on a resist using a drawing apparatus will be described.

Referring to FIG. FIG. 8 schematically illustrates an optical system of a typical electron beam lithography apparatus of a variable shaping method or a partial batch exposure method. 8, reference numeral 8a denotes a charged beam source, 8b denotes an irradiation lens, 8c denotes a blanker, and 8d.
Is a first aperture mask, 8e is a shaping lens, 8f is a shaping deflector, 8g is a second aperture mask, 8h is a reduction lens, 8i is a sub deflector, 8j is an objective lens, 8k is a focus correction lens, and 8l is a main deflection. It is a vessel. In the general case, when performing electron beam lithography on a resist using such a lithography system, the following confirmation experiment was performed in order to identify the degree of positional accuracy degradation caused by resist charge-up. .

Referring to FIG. The three chips in the leftmost row of the wafer (the three chips in the leftmost row of FIG.
Dummy charge as shown in FIG. That is, the charge dummy cells 21 for drawing the dummy pattern are uniformly arranged so as to surround the overlay accuracy pattern (overlay measurement pattern) 23 as shown in the figure. In the figure, 16 cells are arranged so as to surround the overlapping measurement pattern 23 in a substantially square shape. In this case, the chip size is 25 mm square, and the dummy drawing rate is 5.5.
%, And the total accumulated charge amount is 52 μC / chip.
The charge dummy cell 21 is shown in FIG. Reference numeral 22 denotes a connection accuracy evaluation pattern. The main deflection field size is 5005 μm □, the sub deflection field size is 455 μm □, and the sub deflection field size is 65 μm.
Draw with m □. In the drawing, reference numeral 24 indicates a 455 μm subfield unit. The unit as shown in FIG. 2 is arranged at the center of the sub-field as required (that is, the overlay measurement pattern of FIG. 2 corresponds to the sub-field). As shown in FIG. 3, the area of the line-and-space pattern 31 and the area of the pad pattern 32 of the charge dummy cell 21 are the same, and either a pad-type pattern or a line-and-space-type pattern is used. .

Subsequently, in order from the lower left of the wafer to the upper direction,
Alignment accuracy measurement mark (main scale 20μ in the example shown)
m, a box-in-box mark of vernier 8 μm, which is a box mark arranged at the center of the dummy pattern in FIG. 2). At this time, the mark of the main scale used was a mark dug into a base silicon substrate in advance by a KrF stepper. Writing was performed at an exposure amount of the alignment mark of 10 μC / cm ² .

The resist process was performed as follows. First, a negative chemically amplified resist N containing polyvinylphenol resin as a main component is placed on an underlying silicon substrate with a main scale mark.
EB22 (Sumitomo Chemical Co., Ltd.) is applied in a thickness of 1.5 μm. Subsequently, after the dummy pattern and the alignment mark are drawn, PEB processing (heat treatment before exposure) is performed, and development processing is performed using a developing solution (TMAH (tetramethylammonium hydride) 2.38%) to complete the patterning.

The measurement of the overlay accuracy of the wafer prepared by the above method was performed as follows. The alignment accuracy measuring instrument is an optical measuring instrument LA2000 (manufactured by Hitachi, Ltd.)
The measurement conditions were as follows: the center of the chip center in a 5005 μm square field, and the center of each of a total of nine subfields arranged at peripheral corners, a total of nine points × 3
Performed with 7 chips.

FIG. 4 shows the measured values of the main deflection field magnification value in each chip. FIG. 4A shows an arrangement of chips on a wafer, and three chips T in the leftmost column are chips T to which a dummy charge is applied. FIG. 4B shows the measured value (pp) of the main deflection field magnification value in each chip.
m) is shown in each chip. From the main deflection field magnification value of the chip T to which the dummy charge has been given, the field magnification value decreases as the distance from the chip T increases.

FIG. 5 is a graph of the data of FIG. 4 in the form of a dependence on the distance from the dummy charge.
As can be clearly understood from FIG. 5, the field magnification is larger as the position is closer to the dummy charge, and the difference from the region not affected by the dummy charge is 20 ppm (500 ppm).
In the case of a 5 μm square field, a magnification difference of as much as 50 nm on one side was found to occur. At this time, it was found that the distance affected by the dummy charge was 50 mm, which was unexpectedly wide.

In this embodiment, the field magnification change amount which depends on the charge-up experimentally obtained in the above is obtained analytically. In the following,
It will be described in detail.

First, a model for analytically calculating the amount of change in field magnification depending on charge-up, introduction of an electric field function formula, and a correlation between an electric field distribution and a field magnification will be described.

FIG. 6 shows a surface potential model utilizing the concept of the electroimaging method in electromagnetism, which is used as a model for calculating the surface potential of the dummy charge. In the figure, reference numeral 61 denotes a conductor surface (V = 0), and reference numeral 62 denotes a wafer surface.

The calculation of the conductor surface electric field will be described. In the electric image model shown in FIG. 6, a charge density σ (y, z) is induced on the conductor surface by electrostatic induction due to the influence of the charge −Q existing on the wafer surface 62. σ (y,
The electric field E created by z) in the x-direction increases as the distance from the charge decreases, bending the deflected beam over time, thereby increasing the field magnification. The electric field function E (y) derived by the electric image method is shown below.

[0026]

Ex (y) = (− Q · d / 2πε ₀ ) [d ² + y ² ) ^−3/2 (1)

This can be obtained by solving the charge-up phenomenon in the EB lithography according to the basic solution of static electricity based on the knowledge of the present inventor assuming an electric image method.

Now, in the above-described confirmation experiment, the reason why the field magnification fluctuates due to charge-up will be considered as follows. Reference is made to the explanatory diagram of the mechanism for estimating the occurrence of field expansion shown in FIG. FIG. 7 shows a model of a single resist layer. In FIG. 7, reference numeral 71 denotes an electron beam (here, 50 kV), reference numeral 72 denotes an original trajectory of electrons, and reference numeral 73 denotes an trajectory of an electron having a positional shift. Reference numeral 74 denotes an equipotential surface, 75 denotes an objective lens, and 76 denotes a deflector.

Although the center beam is not bent by the electric field generated in the height direction of the wafer due to the resist charge-up, the deflection beam receives a Coulomb force in the direction of the wafer surface, causing a positional shift, thereby inducing a field expansion. You. That is, according to this model, as shown by the symbol B, the beam does not shift at the center of the field,
As indicated by the symbol A, the field expands around the field. Since it has been confirmed that the amount of the field expansion is proportional to the electric field shown in the above confirmation experiment, it will be described below.

In FIG. 6, α is the incident angle of electrons, and V ₀ is x
Assuming the initial velocity in the direction, the deflection amount ΔR is obtained as follows by solving the equation of motion of the deflection beam in the x direction.

[0031]

ΔR = (α · d / 4) · (d / Vacc) · Ex (2)

Accordingly, it has been found that the amount of deflection shift is proportional to the electric field E (see equation (2)).

Actually, the electric field distribution shown in the equation (1) is expressed as d =
At 30 mm, fitting to the experimental results confirmed that they matched well. FIG. 9 shows the results. FIG. 9 shows the dependence of the dummy charge distance on the horizontal axis of the position on the wafer and the vertical axis of the field magnification. The intermittent dotted line shows the experimental results, and the continuous one shown in the actual battle is It is an electric field calculation result (calculation result by an electric field image model).

As described above, according to the present embodiment, when patterning is performed by electron beam lithography using a photoresist as a mask, the correlation between the amount of charge accumulated on the resist surface and the amount of field magnification change of the lithography chip is obtained. Could be functionalized. In this way, by making the relationship between the accumulated charge amount and the field magnification value into a function, it is possible to quantitatively estimate the positional shift amount in the actual pattern.

Embodiment 2 In this embodiment, the amount of positional deviation in an actual device is quantitatively estimated using the field magnification function obtained in Embodiment 1, and the field magnification is calculated in accordance with the electron beam drawing order. By correcting the deflection voltage of the electron beam drawing apparatus so as to correct the value, the drawing position accuracy is improved.

FIG. 1 shows a field magnification value correction algorithm in this embodiment. As shown in FIG.
In the present embodiment, the step 1 of calculating the accumulated charge amount per chip from the desired pattern drawing rate and the effective dose is performed, and the chip 1 is drawn 2. Next, the above-described equation is applied. That is, with respect to the subsequent drawing, the field magnification change amount ΔR (i-1, i) of the chip i received from the chip i-1 is calculated 3 by the above equation (2) (see the above equation (2) and its description). Next, the ΔR
Feedback (4) is provided to the drawing apparatus using (i-1, i) as an offset value. Based on this, the offset value ΔR (i
The deflection voltage of the drawing device is corrected so that −1, i) = 0, and the chip i is drawn 5. Next, the process proceeds to the next drawing operation, and the correction is sequentially performed again from the above-mentioned step 3 to draw the next chip. If all the chips are drawn, that is, if the above algorithm is repeated until i = 37 in this case, the process is terminated.

The correction algorithm shown in FIG.
To illustrate the concept of charge accumulation that the chip receives during drawing,
As shown in FIG. FIG. 10 conceptually shows charge accumulation received by the #i chip at the time of drawing.

In FIG. 10, the accumulated charge amount received by the #i chip before drawing is the total charge amount received from the drawing chips # 1 to # i−1, and the amount is expressed by the equation (1) in the first embodiment. Using 1), it can be estimated as follows.

[0039]

Equation 3] σ (y, z) = ε 0 E = Σ N i = 1 (-Q · d / 2π) _{^{[d 2 + y i 2 + z}} i 2) -3/2 (3)

Ex of the formula (2) is obtained from the formula (3), and ΔR is obtained from the formula (2). The above value obtained from Expressions (3) and (2) is fed back to the drawing apparatus as the offset correction amount ΔR in the algorithm shown in FIG. As a result, it is possible to realize high-precision drawing in which the drawing position accuracy is significantly improved. Note that the value obtained by Expression (3) corresponds to the value of ΔR (i-1, i) = 0 in the algorithm.

According to the present embodiment, it is possible to quantitatively estimate the amount of positional deviation in the actual pattern by making the relationship between the accumulated charge amount and the field magnification value a function. Further, by utilizing this, it is possible to process a highly accurate semiconductor integrated circuit pattern by compensating for deterioration of drawing position accuracy due to resist charge-up in a resist process, particularly in a resist single layer process, without using a conductive film or the like. It has become possible.

[0042]

As described above, according to the electron beam lithography method and the electron beam lithography apparatus of the present invention, charge-up can be effectively prevented without providing a conductive film or the like on a resist to be exposed. Without any problems such as deterioration of resolution
It is possible to prevent the influence due to the occurrence of charge-up.

[Brief description of the drawings]

FIG. 1 is a diagram showing a field magnification value correction algorithm according to a second embodiment of the present invention.

FIG. 2 is a diagram showing an outline of drawing pattern data.

FIG. 3 is an enlarged view of a charge dummy pattern cell.

FIG. 4 is a diagram showing actual measurement values of field magnification values.

FIG. 5 is a diagram illustrating the distance dependency of a field magnification value with a dummy charge.

FIG. 6 is a diagram showing an electric image model for calculating a surface potential of a dummy charge.

FIG. 7 is a diagram showing a mechanism for estimating occurrence of field expansion.

FIG. 8 is a diagram showing an optical system of a general electron beam drawing apparatus.

FIG. 9 is a diagram illustrating a comparison with a dummy charge distance-dependent electric image model.

FIG. 10 is a diagram illustrating the concept of charge accumulation received by a chip during writing.

[Explanation of symbols]

1 ... accumulated charge amount calculation step, 2 ... chip drawing step, 3 ... field magnification change amount calculation step, 4 ...
A step of feeding back the field magnification change amount to the drawing apparatus;

Claims (7)

[Claims] 1. An electron beam lithography method for performing patterning by electron beam lithography using a photoresist as a mask, comprising a step of correcting a change in field magnification due to a resist surface potential. 2. An electron beam lithography method for performing patterning by electron beam lithography using a photoresist as a mask, the method comprising a step of making a correlation between an accumulated charge amount on a resist surface and a field magnification change amount of a lithography chip a function. Characteristic electron beam drawing method. 3. The electron beam lithography method according to claim 2, wherein the amount of displacement in an actual device can be quantitatively estimated by using the function formula of the accumulated charge amount and the field magnification. 4. A deflection voltage of an electron beam lithography apparatus is corrected by using a function formula of the accumulated charge amount and a field magnification to correct a field magnification value in accordance with an electron beam drawing order. The electron beam drawing method according to 1. 5. An electron beam lithography apparatus for performing patterning by electron beam lithography using a photoresist as a mask, comprising a functioning mechanism for functioning a correlation between an accumulated charge amount on a resist surface and a field magnification change amount of a lithography chip. An electron beam drawing apparatus characterized by the above-mentioned. 6. The electron beam lithography apparatus according to claim 5, further comprising an estimation mechanism for quantitatively estimating a position shift amount in an actual device using the function formula of the accumulated charge amount and the field magnification. 7. A correction mechanism for correcting a deflection voltage of an electron beam lithography apparatus to correct a field magnification value in accordance with an electron beam lithography order by using the function formula of the accumulated charge amount and the field magnification. The electron beam lithography apparatus according to claim 5.