JP2000222256A - Debugging device for processor incorporating cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a debugging device for a processor incorporating a cache memory of high real-time debugging property, which is free from the restriction of a cache hitting ratio computable period due to the overflow of a counter. SOLUTION: As trace data 114 outputted from the processor 100 incorporating the cache memory 102, information on an instruction fetch value 109 and a cache hit value 110 are added to branching destination address information and outputted, thereby the trace and cache hitting ratio can be computed without losing real-time property.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a debug device for a processor with a built-in cache memory.

[0002]

2. Description of the Related Art Generally, a processor having a built-in cache memory performs a closed operation inside the processor when a hit occurs in the cache memory. Therefore, it is difficult to follow the operation of the cache memory outside the processor.
In a conventional debug device of a processor having a built-in cache memory, a real-time trace function and a hit ratio calculation indicating the efficiency of the cache memory are realized by the following means.

Hereinafter, examples of a conventional debug device for a processor with a built-in cache memory will be described with reference to the drawings. FIG. 2 is a block diagram showing a first example of a conventional debug device of a processor with a built-in cache memory, and FIG. 3 is a block diagram showing a second example of a debug device of a conventional processor with a built-in cache memory.

[0004] The debug device for a processor with a built-in cache memory shown in FIG. 2 includes a processor 400 having a CPU 401 and a cache memory 402, a counter unit 500 having a cache hit counter 501 and a memory access counter 502, and a host computer 6.
00 and an external memory 700. The operation is as follows. First, a hit signal 404 when an instruction fetch access / data access 403 from the CPU 401 hits the cache memory 402 is used by the cache hit counter 501 in order to obtain a hit ratio indicating the use efficiency of the cache memory 402. The external memory access signal 405 when the cache memory 402 is not hit is counted by the memory access counter 502. The host computer 600 captures the cache hit counter value 503 counted by the cache hit counter 501 and the memory access counter value 504 counted by the memory access counter 502,
The calculation realizes a hit ratio calculation indicating the efficiency of the cache memory 402.

[0005] The conventional debug device for a processor with a built-in cache memory shown in FIG. 3 includes a processor 400 containing a CPU 401 and a cache memory 402, an external memory 700, an instruction flow static analyzer 801, a trace information generator 802, and a tracer. The processor 400 includes a trace analyzer 800 having a memory 803 and a host computer 600.
2 is provided with a dedicated external terminal for outputting a status signal 406 including information of enabling / disabling of a branch, occurrence of a branch that can be statically analyzed, occurrence of a branch that cannot be statically analyzed, and occurrence of an instruction fetch. Further, the trace analyzer 800 selects a tracing method according to the content of the status signal 406 while the dynamic instruction flow 8
05 is realized by assembling.

Next, a method for generating the dynamic instruction flow 805 will be described. First, when the cache memory 402 is invalidated, the dynamic instruction flow 80 is traced by tracing the address bus of the external memory access 405.
5 and if the cache memory 402 is enabled, the program can be preliminarily analyzed by a static instruction flow 804 obtained from the instruction flow static analysis unit and instruction fetch generation and branch destination static analysis included in the status signal 406. Branch occurrence,
A dynamic instruction flow 805 is assembled based on information on occurrence of a branch destination static analysis impossible branch. Here, the status signal 406
Indicates that the branch destination cannot be analyzed statically, the trace analyzer 800 generates an interrupt to the processor 400 and then obtains the branch destination address by taking in the value of the program counter of the processor 400 to obtain an instruction. It realizes the assembly of the flow.

[0007]

However, in the configuration of the first example of the conventional device, the cache hit ratio after the overflow of the cache hit counter 501 or the memory access counter 502 built in the counter unit 500 occurs. Therefore, there is a problem that only the cache hit ratio calculation for a limited processor operation period can be realized because the calculation of the instruction flow generation unit 802 is not possible. When the branch destination address cannot be statically analyzed, there is a problem that an interrupt unnecessary for execution of the program is generated to obtain a program counter value for the processor 400, which impairs real-time debug of the program. Was.

An object of the present invention is to provide a debugging apparatus for a processor with a built-in cache memory which has high real-time debugging performance and has no restriction on a period in which a cache hit ratio can be calculated due to an overflow of a counter. It is the purpose.

[0009]

A debug device for a processor with a built-in cache memory according to the present invention comprises: a counter for counting an instruction fetch signal output from a CPU; a counter for counting a cache hit signal output from a cache memory; A branch occurrence signal and a branch destination address output from the CPU are received,
A processor including a trace output unit and a cache memory configured by a trace output circuit that traces out two counter values, a trace analyzer, and a host computer for displaying information obtained from the trace analyzer. is there.

According to the present invention, it is possible to realize a debugger for a processor with a built-in cache memory, which has high real-time debuggability and has no restriction on the period in which the cache hit ratio can be calculated due to overflow of the counter.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a debug device for a processor with a built-in cache memory according to the present invention.

The basic configuration of the debugging device shown in FIG. 1 comprises a processor 100, a trace analyzer 200 and a host computer 300.
A cache memory 102 built in the processor 100; an instruction fetch counter 103 having a mechanism for counting an instruction fetch signal 107 output from the CPU 101 and clearing the value by a counter reset signal 113 , 104 are cache hit rate counters provided with a mechanism for counting the cache hit signal 108 output from the cache memory 102 and clearing the value by a counter reset signal 113, and 105 is input with a branch occurrence signal 111 output from the CPU 101. When the branch destination address 112
And a value 109 of the instruction fetch counter 103 and a value 110 of the cache hit rate counter 104, respectively. A trace output circuit 114 has a function of outputting a trace from the trace output circuit 105 through a dedicated external terminal for trace output provided in the processor 100. Trace data 201 receives the trace data 114, and writes a result 205 obtained by decoding the data into a trace memory 202 and a cache hit ratio register 203 described later. A trace information decoding unit 202 stores the sequentially output trace information. Memory 203, a cache hit rate register for storing the total number of instruction fetches and cache hits in the sequentially output trace information, and 204 a trace memory content 206 and cache hit information. A host interface unit 300 for outputting 207 to the host communication path 208 has a function of displaying trace information obtained through the host communication path 208 and a cache hit ratio based on the number of instruction fetches and cache hits obtained by the host communication path 208. This is a host computer having a function of calculating.

Next, the operation will be described. First, a case in which the CPU 101 is executing an instruction in FIG. 1 will be described. An instruction fetch signal 107 is output each time an instruction fetch occurs, and a cache hit signal 108 is output when the cache memory 102 is hit during instruction fetch. When a branch occurs, a branch occurrence signal 111 and a branch destination address 112 are output. When the branch generation signal 111 is input, the trace output unit 105 fetches a branch destination address 112, an instruction fetch counter value 109, and a cache hit rate counter value 110, outputs these as trace data 114, and outputs a counter reset signal 113. I do.

A trace information analysis unit 201 in the trace analyzer 200 receives the trace data 114, analyzes the information content, converts the information into valid debug information, and writes the result into the trace memory 202. Indicates the number of instruction fetches and the number of cache hits, the value of the cache hit ratio register 203 plus the respective number is overwritten.

The host computer 300 communicates with the host interface unit 204 inside the trace analyzer 200 through the host communication path 208,
By reading the trace result 206 required for debugging from the trace memory 202 and the cache hit information 207 required for calculating the cache hit ratio from the cache hit ratio register 203, and displaying and calculating the same, the debug device of the processor with a built-in cache memory can Realize.

As described above, according to the present embodiment, the trace of the processor incorporating the cache memory maintains the real-time debug performance without generating unnecessary interrupts to the processor, and the instruction execution result of the processor is maintained. , It is possible to easily know an accurate operation state in a branch unit of the cache memory according to. In calculating the cache hit ratio, even when the cache hit ratio register overflows, the instruction fetch count and the cache hit count for each branch are stored in the trace memory. It is possible to easily develop software that makes the most of the performance of the processor.

[0017]

As described above, according to the present invention, it is possible to easily know an accurate operation state in a branch unit of a cache memory in accordance with a result of instruction execution of a processor without impairing real-time debug performance. Yes, even if the cache hit rate register overflows, it is possible to calculate the cache hit rate continuously by reading the contents of the trace memory, and at the same time, develop software that maximizes the performance of the processor. Can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a debugging device for a processor with a built-in cache memory according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a first example of a conventional debug device for a processor with a built-in cache memory;

FIG. 3 is a block diagram showing a second example of a conventional debug device for a processor with a built-in cache memory;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 processor 101 CPU 102 cache memory 103 instruction fetch counter 104 cache hit counter 105 trace output circuit 106 instruction fetch access / data access 107 instruction fetch occurrence signal 108 cache hit signal 109 instruction fetch counter value 110 cache hit rate counter value 111 branch occurrence signal 112 Branch destination address 113 Counter reset signal 114 Trace data 115 Trace output unit 200 Trace analyzer 201 Trace information decoding unit 202 Trace memory 203 Cache hit ratio register 204 Host interface unit 205 Trace data decoding result 206 Trace result 207 Cache hit information 208 Host communication Path 300 Host computer

Claims (2)

[Claims] 1. A counter for counting an instruction fetch signal output from a CPU, a counter for counting a cache hit signal output from a cache memory, and a branch destination signal receiving a branch occurrence signal and a branch destination address output from the CPU. A processor including a trace output unit and a cache memory constituted by a trace output circuit configured to trace and output an address and the two counter values; a trace analyzer; and a host computer for displaying information obtained from the trace analyzer. A debug device for a processor with a built-in cache memory, comprising: 2. A trace analyzer, comprising: a trace memory for accumulating trace information; a register for storing an instruction fetch count and a cache hit count required for obtaining a cache hit ratio; and a trace output output from the processor. A trace information decoding unit having a function of decoding and writing a result of the decoding into the trace memory and the register; and a host interface unit for transferring the contents of the trace memory and the register by communicating with a host computer. The debug device for a processor with a built-in cache memory according to claim 1.