JP2000221929A - Sampling latch circuit, and liquid crystal display device mounting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling latch circuit capable of being applied in a device having a large threshold Vth such as TFT, and capable of fulfilling simultaneously both miniaturization of the area and reduction of the power consumption, and liquid crystal display device mounting the sampling latch circuit. SOLUTION: A CMOS latch cell 10 having a comparator formation is used as a basic formation, and switches 15, 16 are connected between two input parts of the CMOS latch cell 10 (each input terminal of CMOS inverters 11, 12) and two input signal sources (two circuit input terminals 13, 14 where input signals in1, in2 are inputted), and a switch 18 is connected to the power supply side of the CMOS latch cell 10, and a supplemental switching control between the switches 15, 16 and the switch 18 is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling latch circuit and a liquid crystal display device having the same, and more particularly, to a sampling latch circuit having a CMOS latch cell as a basic structure and having a level shift function and a scanning system comprising the sampling latch circuit. The present invention relates to a so-called drive circuit integrated type liquid crystal display device mounted as one of circuits.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional example of a sampling latch circuit having a level shift function composed of CMOS. The sampling latch circuit according to this conventional example has an N-channel MOS (hereinafter simply referred to as NMOS) having an input signal in1 as a gate input and a source connected to the ground.
A transistor Qn101; an NMOS transistor Qn102 having an input signal in2 as a gate input and a source connected to the ground;
And the gate is connected between the drain of
P-channel MOS (hereinafter simply referred to as PMOS) transistor Qp101 connected to the drain of MOS transistor Qn102, and NMOS transistor Qn102
And the gate is connected between the drain of
The basic configuration is a CMOS latch cell 101 having a comparator configuration having a PMOS transistor Qp102 connected to the drain of a MOS transistor Qn101.

In the CMOS latch cell 101, N
The drain outputs of the MOS transistors Qn102 and Qn101 are latched by a latch circuit 106 via inverters 102 and 103 and sampling switches 104 and 105. Then, one latch output of the latch circuit 106 is inverted by an inverter 107 to output an output signal o.
ut, and the other latch output is inverted by the inverter 108 to obtain an inverted signal xout of the output signal out.
Is derived as

In the conventional sampling latch circuit having the above configuration, it is assumed that a signal having a low voltage amplitude of, for example, 3 V is input as in1, and an inverted signal of the input signal in1 is input as in2. The input signals in1 and in2 having the low voltage amplitude of 3 V are supplied to the CMOS latch cell 101.
, The voltage is once raised to the power supply voltage VDD of the circuit, and then passed through the inverters 102 and 103 to the sampling switch 10.
At 4 and 105, the signal is sampled by the sampling pulse SP and stored in the latch circuit 106. The output signals are inverted by inverters 107 and 108 and output signals out,
It will be derived as xout.

[0005]

However, in the sampling latch circuit according to the conventional example described above, it is difficult to reduce the area because the number of elements constituting the circuit is large.
When a circuit is configured using a device having a large threshold Vth such as an FT (thin film transistor), the input signal in1,1 is input to the threshold Vth.
Since the voltage amplitude of n2 is too small to reliably turn on each transistor, there is a concern that the sampling operation may not be possible.

On the other hand, FIG. 11 shows a conventional example in which the device is easily operated even if the threshold value Vth of the device is high.
A sampling latch circuit according to another conventional example employs a configuration in which a DC level of a signal is shifted by a capacitor. That is, the output terminals of the switch 201 receiving the signal in1 and the switch 202 receiving the signal in2 are commonly connected, and one end of the switched capacitor 203 is connected to the common connection point. The other end of the capacitor 203 is connected to one end of each of the switches 204 and 205 and the input end of the inverter 205.

The other end of the switch 205 has an inverter 20
7 are connected. And the switch 204
, The output terminal of the inverter 206 and the inverter 2
07 are connected in common, and the input terminal of the inverter 208 is connected to the common connection point.
An output signal out is derived from the output terminal of the output signal.

In a sampling latch circuit according to another conventional example having the above configuration, the switched capacitor 203 is used as a comparator, and the circuit operation is as follows. First, the circuits are reset by turning on the switches 202 and 204 in response to the equalizing pulse Eq. Thereafter, the switch 201 is turned on in response to the sampling pulse SP to sample the input signal in1 having a low voltage amplitude. Is done. Subsequently, the sampled signal in1 is level-shifted by the capacitor 203 while being compared with the input signal in2, and finally the switch 205 is turned on in response to the latch pulse LT, whereby the latch circuit including the inverters 206 and 207 is provided. Latched.

As described above, in the sampling latch circuit according to another conventional example, the signal in1 is set by the capacitor 203.
Is shifted, the threshold value Vth
This makes it easy to operate even a circuit configured using a TFT having a high sampling rate, so that a stable sampling and latch operation can be realized. However, on the other hand, it is difficult to reduce power consumption because a DC current needs to flow at the time of resetting.Moreover, there are many types of pulses required for circuit operation, and the timing control is difficult, so the configuration of the control circuit becomes complicated, Therefore, it is difficult to reduce the area.

The present invention has been made in view of the above problems, and has as its object to be applicable to a device having a large threshold Vth, such as a TFT, and to simultaneously reduce the area and power consumption. An object of the present invention is to provide a satisfactory sampling latch circuit and a liquid crystal display device having the same.

[0011]

SUMMARY OF THE INVENTION A sampling latch circuit according to the present invention is based on a CMOS latch cell having a comparator configuration, and is connected between two input portions and two input signal sources of the CMOS latch cell. A first switch, a second switch connected between the power supply side of the CMOS latch cell and the power supply line, and control means for performing complementary switching control of the first switch and the second switch. It has a configuration.

A liquid crystal display device according to the present invention is a drive circuit integrated type liquid crystal display device in which a drive circuit including a scanning system is formed integrally with a pixel portion on the same substrate. , Using the sampling latch circuit having the above configuration.

In the sampling latch circuit having the above configuration and the liquid crystal display device having the same, two input signals are sampled when the first switch is turned on (closed). During this sampling period, the second switch is off (open), and the CMOS latch cell is disconnected from the power supply. Then, the sampling period ends, the second switch is turned on, and the CMO
At the moment when the power is supplied to the S latch cell, the input signal having the small voltage amplitude is latched as the signal having the amplitude of the power supply voltage.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of the configuration of the sampling latch circuit according to the first embodiment of the present invention.
In the sampling latch circuit according to the first embodiment, a CMOS inverter 11 including an NMOS transistor Qn11 and a PMOS transistor Qp11 whose gates and drains are commonly connected, respectively, and respective gates and drains are commonly connected. N
The basic configuration is a CMOS latch cell 10 having a comparator configuration in which a CMOS inverter 12 including a MOS transistor Qn12 and a PMOS transistor Qp12 is connected in parallel with each other between a power supply line 17 of a power supply voltage VDD and the ground.

In this CMOS latch cell 10, C
An input terminal of the MOS inverter 11, that is, a common connection point of the gates of the MOS transistors Qn11 and Qp11, and a CMOS
The output terminal of the inverter 12, that is, the MOS transistor Qn
12 and Qp12 are connected to the common drain connection point. Further, the input terminal of the CMOS inverter 12, that is, the gate common connection point of the MOS transistors Qn12 and Qp12 and the CM
The output terminal of the OS inverter 11, that is, the common drain connection point of the MOS transistors Qn11 and Qp11 is connected.

A switch 15 is connected between the input terminal of the CMOS inverter 11 and the first circuit input terminal 13 by a CMO.
Switches 16 are respectively connected between the input terminal of the S inverter 12 and the second circuit input terminal 14. further,
The switch 18 is also connected to the power supply side of the CMOS latch cell 10, that is, between the node A and the power supply line 17. The switches 15 and 16 are switching-controlled directly by a sampling pulse SP input from a sampling terminal 19, and the switch 18 is controlled by an inverted pulse of the sampling pulse SP passed through an inverter 20. An inverter 23 is provided between the input terminal of the CMOS inverter 12 and the first circuit output terminal 21, and an inverter 24 is provided between the input terminal of the CMOS inverter 11 and the second circuit output terminal 22.
Are connected respectively.

In the sampling latch circuit according to the first embodiment having the above configuration, a signal in1 having an amplitude Vp of, for example, about 3 V is input to the first circuit input terminal 13, and 0 V or more and Vp or less to the second circuit input terminal 14. It is assumed that an arbitrary DC voltage (reference voltage Vref) within the voltage range is input as signal in2.

Here, the circuit operation will be described with reference to the timing chart of FIG. 2. When an active "H" sampling pulse SP is input from the sampling terminal 19, the switches 15 and 16 are turned on (closed). Thereby, input signals in1 and in2 are transmitted to the node of CMOS latch cell 10. At the same time, the switch 1 is turned on by the inversion pulse of the sampling pulse SP.
8 is turned off (open), so that the CMOS latch cell 1
0 is disconnected from the power supply line 17 (node A).

Next, when the sampling pulse SP disappears, the node of the CMOS latch cell 10 is disconnected from the first and second circuit input terminals 13 and 14, and at the same time, the CMOS
The power supply side of the latch cell 10 is connected to the power supply line 17. The comparison process according to the voltage of the node at this moment is performed by the CMOS latch cell 10, and the latch operation starts. Finally, the node is latched at the power supply voltage VDD or 0 V according to the polarity of the input signal in1 at the moment when the sampling pulse SP disappears. At this time, the voltage of the opposite polarity is latched at the node.

With the above circuit operation, the data of the input signal in1 having the amplitude Vp of, for example, about 3 V is sampled in synchronization with the sampling pulse SP, and latched at the node as the data having the amplitude of the power supply voltage VDD. The latch data of the node is inverted by the inverter 23 and is derived from the first circuit output terminal 21 as an output signal out.
4 and output signal ou from the second circuit output terminal 22.
It is derived as an inverted signal xout of t.

As described above, the CMOS latch cell 10 having the comparator configuration is used as a basic configuration. Two input sections (nodes) of the CMOS latch cell 10 and two input signal sources (first and second circuit input terminals 13) are provided. , 14), respectively, and switches CMO
Power supply side (node A) of S latch cell 10 and power supply line 1
7 is also connected to the switch 18, and the switches 15, 1
6 and the switch 18 are controlled in a complementary manner, so that no current flows through the CMOS latch cell 10 during the sampling period of the input signals in1 and in2 by the switches 15 and 16, so that the DC current flowing during operation is extremely small. Since it is slight, the power consumption of the sampling latch circuit can be reduced.

When the sampling period ends, the CMO
Supply voltage VD through switch 18 to S latch cell
At the moment when D is supplied, the data of the input signal in1 having the amplitude Vp of, for example, about 3 V is latched as the data of the amplitude of the power supply voltage VDD. Therefore, a device having a large threshold Vth such as a TFT is used. Even in the case of the configured circuit, stable sampling and latch operation can be realized. Moreover, since the configuration can be achieved by simply adding the switches 15, 16, 18 and the like to the basic circuit of the CMOS latch cell 10, a sampling latch circuit having a small area and a level shift function can be realized with a very small number of elements. .

In the sampling latch circuit according to the present embodiment, 0 ≦ Vre is used as the input signal in2.
Although a DC voltage (reference voltage) Vref in the range of f ≦ Vp is input, it is sufficient that the logic of the input signal in1 can be determined. As shown in (1), an inverted signal of the input signal in1 can be used as a reference signal for the determination. In this case, 0
There is an advantage that a larger margin for logic determination of the input signal in1 can be obtained than when a DC voltage in the range of ≦ Vref ≦ Vp is used as the reference voltage.

In the circuit example of FIG. 1, two output signals out and xout are derived, ie, non-inversion and inversion. However, only one of the output signals may be derived. . In this case, two inverters 2
One of 3, 24 becomes unnecessary.

FIG. 4 is a circuit diagram showing a modification of the level shift circuit according to the first embodiment. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the level shift circuit according to this modification, the switch 1 on the signal input side in FIG.
NMOS transistors Qn13, Qn1 as 5, 16
4 and PM 18 as the switch 18 on the power supply side.
The OS transistor Qp13 is used, and the sampling pulse SP is directly applied to each gate of these transistors.

As described above, when the switches 15, 16, and 18 are realized by transistors, the operation of the circuit is the same as that of the circuit of FIG. Also, the timing example is the same as in FIGS. In this modification, the switches 15 and 16 are NMOS and the switch 18 is P
Although implemented by MOS, it is obvious that the polarity is reversed when the sampling pulse SP is active "L".

FIG. 5 is a circuit diagram showing an example of the configuration of the sampling latch circuit according to the second embodiment of the present invention.
In the sampling latch circuit according to the second embodiment, a CMOS inverter 31 including an NMOS transistor Qn31 and a PMOS transistor Qp31 whose gates and drains are commonly connected, respectively, and respective gates and drains are commonly connected. N
The basic configuration is a CMOS latch cell 30 having a comparator configuration in which a CMOS inverter 32 including a MOS transistor Qn32 and a PMOS transistor Qp32 is connected in parallel with each other between a power supply line 37 and the ground.

In this CMOS latch cell 30, C
An input terminal of the MOS inverter 31, that is, a common connection point of the gates of the MOS transistors Qn31 and Qp31, and a CMOS
The output terminal of the inverter 32, that is, the MOS transistor Qn
32, Qp32, and a common connection point of the CMOS inverter 32, that is, a common connection point of the gates of the MOS transistors Qn32, Qp32 and the CM.
The output terminal of the OS inverter 31, that is, the common drain connection point of the MOS transistors Qn31 and Qp31 is connected.

The switch 35 is connected between the input terminal of the CMOS inverter 31 and the first circuit input terminal 33 by the CMO.
Switches 36 are respectively connected between the input terminal of the S inverter 32 and the second circuit input terminal 34. further,
The switch 38 is also connected to the power supply side of the CMOS latch cell 30, that is, between the node A and the power supply line 37. The switches 35 and 36 are directly controlled by the sampling pulse SP input from the sampling terminal 39, and the switch 38 is controlled by the inverted pulse of the sampling pulse SP passed through the inverter 40.

An inverter 43 is provided between the input terminal of the CMOS inverter 32 and the first circuit output terminal 41. An inverter 43 is provided between the input terminal of the CMOS inverter 31 and the second circuit output terminal 42. 44 are respectively connected. The inverter 43 has a CMOS inverter configuration including P and NMOS transistors Qp33 and Qn33, each of which has a gate and a drain connected together and is connected between the notebook A and the ground. Similarly, the inverter 44 has its gate and drain connected in common, and
And a CMOS inverter composed of P and NMOS transistors Qp34 and Qn34 connected between the ground and the ground.

In the sampling latch circuit according to the second embodiment having the above structure, a signal in1 having an amplitude Vp of, for example, about 3 V is input to the first circuit input terminal 33, and the second circuit input terminal 34 has a voltage of 0 V or more and Vp or less. Is input as signal in2. The circuit operation of the sampling latch circuit according to the second embodiment is basically the same as that of the sampling latch circuit according to the first embodiment.

That is, when an active "H" sampling pulse SP is input from the sampling terminal 39, the switches 35 and 36 are turned on (closed), whereby the input signals in1 and in2 are applied to the nodes of the CMOS latch cell 30, Is transmitted to At this time, at the same time, the switch 3
8 is turned off (open), so that the CMOS latch cell 3
0 is disconnected from the power supply line 37.

Next, when the sampling pulse SP disappears, the node of the CMOS latch cell 30 is disconnected from the first and second circuit input terminals 33 and 34, and at the same time, the CMOS
The power supply side of the latch cell 30 is connected to the power supply line 37. The comparison process according to the voltage of the node at this moment is performed by the CMOS latch cell 30, and the latch operation starts. Finally, the node is latched at the power supply voltage VDD or 0 V according to the polarity of the input signal in1 at the moment when the sampling pulse SP disappears. At this time, the voltage of the opposite polarity is latched at the node.

With the above circuit operation, the data of the input signal in1 having the amplitude Vp of, for example, about 3 V is sampled in synchronization with the sampling pulse SP, and latched at the node as the data having the amplitude of the power supply voltage VDD. The latch data of the node is inverted by the inverter 43 and is derived as an output signal out from the first circuit output terminal 41.
4 and output signal ou from the second circuit output terminal 42.
It is derived as an inverted signal xout of t.

According to the configuration of the sampling latch circuit according to the second embodiment, in addition to the effects of the sampling latch circuit according to the first embodiment, the CMO
The power supply to the S inverters 43 and 44 is also C
Since the switching control is performed in the same manner as the MOS latch cell 30, unnecessary current flowing through the CMOS inverters 43 and 44 can be reduced, so that the power consumption of the sampling latch circuit can be further reduced.

In the case of the sampling latch circuit according to the second embodiment, the switches 35, 36, and 38 can be realized by transistors as in the case of the modification of the first embodiment shown in FIG. Further, an inverted signal of the input signal in1 is used as the input signal in2,
It is also possible to adopt a configuration in which only one of the two output signals out and xout is derived.

The sampling latch circuits according to the first and second embodiments of the present invention described above include, for example, a digital interface on a glass substrate on which polysilicon TFTs are arranged in a two-dimensional matrix as switching elements of each pixel. In a so-called drive circuit integrated type liquid crystal display device in which a drive circuit is formed integrally with a pixel portion by a polysilicon TFT, it is used as a sampling and first latch circuit of a horizontal drive system. FIG. 6 shows an example of a configuration of a liquid crystal display device with an integrated drive circuit.

In FIG. 6, a horizontal drive system 42 is arranged, for example, above the effective pixel area 41 in which pixels are arranged in a two-dimensional matrix, and a vertical drive system 43 is arranged, for example, on the left side.
Are arranged integrally with the effective pixel area 41 on a glass substrate with a polysilicon TFT. The horizontal drive system 42 includes a horizontal shift register 421, a sampling & first latch circuit 422, a second latch circuit 423, and a DA (digital-analog) converter 424. The vertical drive system 43 is configured by a vertical driver 431 including a shift register.

In the horizontal drive system 42, the horizontal shift register 421 receives a horizontal start pulse HST and a horizontal clock pulse HCK as horizontal transfer pulses. Then, the horizontal shift register 421 performs horizontal scanning by sequentially outputting shift pulses from each stage at a cycle of the horizontal clock pulse HCK in response to the horizontal start pulse HST. Sampling & first latch circuit 42
2 sequentially samples digital data in response to a shift pulse output from the horizontal shift register 421, and further samples the sampled data in the effective pixel area 41.
Latch for each column line.

The second latch circuit 423 performs sampling &
The latch data corresponding to the column line latched by the first latch circuit 422 is re-latched every 1H in response to a latch signal given in a 1H (H is a horizontal scanning period) cycle. The DA converter 424 converts the digital data re-latched by the second latch circuit 423 into an analog signal for each column line, and supplies the analog signal to the corresponding column line.

In the liquid crystal display device integrated with a driving circuit having the above-described configuration, the sampling and latch circuit according to the first and second embodiments of the present invention is used as the sampling and first latch circuit 422 of the horizontal drive system 42. As described above, by mounting the sampling latch circuit which can be realized in a small area and consumes low power, the driving circuits such as the horizontal driving system 42 and the vertical driving system 43 including the sampling latch circuit are the same as the effective pixel area 41. When it is formed on a substrate, the peripheral area (frame) of the effective pixel area 41 in which the drive circuit is arranged can be narrowed, and a drive circuit integrated liquid crystal display device with low power consumption can be realized.

Further, as is apparent from the above description, this sampling latch circuit can realize a stable sampling and latch operation even with a device having a large threshold value Vth, for example, a circuit using a TFT. In a driving circuit integrated type liquid crystal display device in which a driving circuit is formed integrally with an effective pixel region 41 by a polysilicon TFT, the driving circuit is useful as a sampling & first latch 422 of the horizontal driving system 42. Hereinafter, a specific example of the application will be described.

FIG. 7 is a block diagram showing a concrete example of this, for example, 3-bit digital data b0, b1, b2
Here is an example in which is input. As is clear from the figure, the sampling latch circuits 422-1, 422-2, 422-3 are provided for each bit of the digital data b0, b1, b2.
Is provided. These sampling latch circuits 42
Bit data of digital data b0, b1, and b2 are input as input signals in1 to 2-1 4222-2, and 422-3, respectively, and a reference voltage (DC voltage) V is input signals in2.
ref is commonly input to each circuit. Then, the sampling pulse S output from the horizontal shift register 421
According to P, the data signals b0, b1,
The sampling of b2 is performed.

The sampling latch circuits 422-1 and 42-1
In each of 22-2 and 422-3, the sampled signal is level-shifted and latched to a signal having a high voltage amplitude required for the TFT circuit. The latched high-voltage amplitude signal is supplied to the sampling latch circuit 422.
-1, 422-2, and 422-3, second latch circuits 423-1, 423 provided for each bit of digital data.
-2, 423-3 line-sequential processing,
The signal is output to the corresponding column line of the effective pixel area 41 through 24.

Here, the sampling latch circuit 422-
1,422-2,422-3 are required to be able to fit in a very small area. The length in the horizontal direction assigned to one sampling latch unit is very short, which is the dot pitch / bit number in the configuration of the driving circuit integrated type liquid crystal display device shown in FIG. Therefore, sampling latch circuits 422-1, 422-2, 4 satisfying this condition can be used.
As 22-3, the sampling latch circuit according to the present invention, which can be realized in a small area, is very effective.

In the circuit example of FIG. 7, the input signal in2
The reference voltage (DC voltage) Vref is commonly input to each circuit. However, as described in the sampling latch circuit according to the first embodiment, as shown in FIG. 422-1, 42
It is also possible to input the inverted signals xb0, xb1, xb2 of the data signals b0, b1, b2 for each of 2-2, 422-3.

FIG. 9 is a block diagram showing a modification of FIG. 8, in which the same parts as those in FIG. 8 are denoted by the same reference numerals. In this modification, each sampling latch circuit 4
22-1, 422-2, and 422-3 on the power supply side (see FIG. 1).
The switch 18 of FIG. 5 and the switch 38 of FIG. 5) are shared between the circuits 422-1, 422-2, and 422-3, and this switch is realized by, for example, a PMOS transistor Qp41.

According to the above configuration, when the digital data is, for example, 3 bits, the number of switches on the power supply side can be reduced by two, so that the area can be further reduced. Also, as in the case of the circuit example of FIG. 7, the inverted signal xb
0, xb1, xb2 instead of DC voltage reference voltage Vr
ef is set to each sampling latch circuit 422-1, 422-2,
An input signal in2 common to 422-3 may be used.

In this embodiment, the case where the sampling and latch circuit according to the present invention is applied to the sampling and first latch circuit 422 of the horizontal drive system in the liquid crystal display device integrated with a drive circuit has been described as an example. The present invention is not limited to this, and can be applied to circuits using TFTs formed on a silicon substrate, and not only to TFTs, but also to circuits using devices with a large threshold Vth.

[0051]

As described above, according to the present invention,
A CMOS latch cell having a comparator configuration is used as a basic configuration. A first switch is connected between two input units of the CMOS latch cell and two input signal sources, and a power supply line of the CMOS latch cell is connected to a power supply line. The second switch is also connected between the first switch and the first switch and the second switch are controlled in a complementary manner, so that it can be configured with a very small number of elements.
Since no current flows through the CMOS latch cell during the sampling period by the first switch, a stable sampling and latch operation with a small area and low power consumption can be realized even when a device having a large threshold Vth is used. Become.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a configuration of a sampling and holding circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a circuit operation of the sampling and holding circuit according to the first embodiment.

FIG. 3 is a timing chart when an inverted signal of the input signal in1 is set to the input signal in2.

FIG. 4 is a circuit diagram showing a modification of the first embodiment.

FIG. 5 is a circuit diagram illustrating an example of a configuration of a sampling and holding circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing an example of the configuration of a drive circuit integrated liquid crystal display device according to the present invention.

FIG. 7 is a block diagram showing a specific example when applied to a sampling and first latch circuit of a horizontal drive system.

FIG. 8 shows an inversion of digital data as input signal in2.
FIG. 4 is a block diagram showing a configuration in the case where.

FIG. 9 is a block diagram showing a modification of FIG.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a circuit diagram showing another conventional example.

[Explanation of symbols]

10, 30,... CMOS latch cells, 11, 12, 31,
32 ... CMOS inverter, 15, 16, 18, 35,
36, 38: switch, 23, 24, 43, 44: inverter, 41: effective pixel area, 42: horizontal drive system, 43
... vertical drive system, 422 ... sampling & first latch circuit

Continued on the front page F-term (reference)

Claims (14)

[Claims] A first switch connected between two input units and two input signal sources of the CMOS latch cell; and a power supply side of the CMOS latch cell. A sampling latch circuit comprising: a second switch connected between the first switch and a power supply line; and control means for performing complementary switching control of the first switch and the second switch. 2. The sampling latch circuit according to claim 1, wherein said first and second switches are realized by transistors. 3. A sampling latch circuit according to claim 1, wherein a plurality of sampling latch circuits according to claim 1 are arranged, and said second switch is shared by said plurality of sampling latch circuits. 4. A switching control in synchronization with the second switch also between a power supply side of an output circuit for deriving an output signal of the CMOS latch circuit and a power supply line.
2. The sampling latch circuit according to claim 1, further comprising: 5. The sampling latch circuit according to claim 4, wherein said second switch is also used as said third switch. 6. A sampling latch circuit according to claim 5, wherein a plurality of sampling latch circuits according to claim 5 are arranged, and said second switch is shared by said plurality of sampling latch circuits. 7. The semiconductor device according to claim 1, wherein said thin film transistor is formed using a thin film transistor formed on a glass substrate.
A sampling latch circuit as described. 8. The sampling latch circuit according to claim 1, wherein the sampling latch circuit is formed using a thin film transistor formed on a silicon substrate. 9. A liquid crystal display device in which a driving circuit including a scanning system is integrally formed on the same substrate as a pixel portion, wherein the scanning system has a CMOS latch cell having a comparator configuration as a basic configuration, 2 input parts and 2
A first switch connected between the two input signal sources, a second switch connected between a power supply side of the CMOS latch cell and a power supply line, the first switch and the second switch. A liquid crystal display device comprising a sampling latch circuit including control means for complementarily performing switching control on a switch. 10. The system according to claim 9, wherein said first and second switches are realized by transistors.
The liquid crystal display device according to the above. 11. A plurality of said sampling latch circuits are arranged corresponding to the number of bits of digital data,
For the plurality of sampling latch circuits, the second
10. The switch according to claim 9, wherein:
The liquid crystal display device according to the above. 12. A semiconductor device according to claim 11, further comprising a third switch, which is controlled in synchronization with said second switch, between a power supply side of an output circuit for deriving an output signal of said CMOS latch circuit and a power supply line. The liquid crystal display device according to claim 9, wherein: 13. The liquid crystal display device according to claim 12, wherein said second switch is also used as said third switch. 14. A plurality of sampling latch circuits are arranged corresponding to the number of bits of digital data,
For the plurality of sampling latch circuits, the second
2. The switch of claim 1, wherein the switches are shared.
3. The liquid crystal display device according to 3.