JP2000216840A - Psk signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process an input signal at high speed with a simple configuration by obtaining data on a phase error and a soft judgment gain by means of referring to a memory table with the common mode and orthogonal signal values of demodulator outputs as addresses. SOLUTION: A received modulation signal is distributed to common mode and orthogonal signals whose phases are shifted by 90 degrees in an orthogonal demodulator 1. They are inputted to an A/D converter 2 and are converted into digital signals. The phases of the common mode and orthogonal signals, which are converted into the digital signals by the A/D converter 2, are rotated in accordance with output from a phase controlled variable calculator 7 in a phase controller 3. Then, they are outputted to a memory table 6 and a soft judgment gain data adder 4. Namely, output from the phase controller 3 is inputted to the memory table 6 and an error value which is previously stored in the memory table 6 is read with the common mode signal value and an orthogonal signal value as addresses. Then, the phase error value which is read is outputted to a low pass filter 8. Thus, two operation processings are obtained only by once referring to the memory table.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PSK (Phase Sh) transmitted from, for example, a maritime satellite (Inmarsat).
The present invention relates to a PSK signal receiving apparatus for receiving, demodulating, and decoding ift keying (phase modulation) signals.

[0002]

2. Description of the Related Art PSK for demodulating and decoding a received PSK signal
The SK signal receiving apparatus generally includes a quadrature demodulator and a decoder, a means for correcting a phase error caused by a frequency offset and noise of a demodulated PSK signal, and an error correction performed by the decoder. And means for obtaining soft decision gain data to be performed. FIG. 4 is a block diagram showing a conventional PSK signal receiving apparatus of this type. In FIG. 4, 1 is a quadrature demodulator, 2 is an A / D converter, 3 is a phase controller, 4 is a soft decision gain data adder, 5 is a decoder,
Reference numeral 7 denotes a phase control amount calculator, 8 denotes a low-pass filter, 9 denotes a phase error detector, and 10 denotes a soft decision gain data calculator.

In FIG. 4, received PSK (modulation)
The signal is divided by the quadrature demodulator 1 into two signals (in-phase and quadrature signals) whose phases are shifted from each other by 90 degrees, input to the A / D converter 2 and converted into a digital signal. The phase of the in-phase and quadrature signals converted into digital signals by the A / D converter 2 is rotated by the phase controller 3 in accordance with the output from the phase control amount calculator 7, and the phase error detector 9 and the soft decision gain The data is output to the data adder 4.

The phase error detector 9 calculates the phase error of the signal output from the phase controller 3 with respect to the reference phase, and outputs the calculated signal to the low-pass filter 8 and the soft-decision gain data calculator 10. In the band-pass filter 8, the high-frequency component of the phase error value is removed, averaged, and input to the phase control amount calculator 7, which calculates the required phase control amount and calculates the phase control amount. Input to the controller 3, the output phase of the phase controller 3 is rotated by this phase control amount, and feedback control is performed so as to match the reference phase.

In the soft decision gain data calculator 10,
The accuracy (probability) of the output of the phase controller 3 that can be distinguished from the phase error value output from the phase error detector 9 is output as soft decision gain data and output to the soft decision gain data adder 4. The soft-decision gain data adder 4 adds the soft-decision gain data to the output of the phase controller 3 and outputs the result to the decoder 5. The decoder 5 corrects the error based on the soft-decision gain data. Done.

[0006]

The conventional P as described above
In the SK signal receiving apparatus, both the phase error detector and the soft decision gain data calculator are configured by arithmetic circuits, and the phase error detector uses a calculation formula such as tan ^-1 (quadrature signal / in-phase signal). The phase error with respect to the reference phase is sequentially calculated, and the obtained phase error is input to the soft decision gain data calculator to calculate the soft decision gain data. Processing of input signals becomes difficult. As the soft decision gain data, quaternary values (that is, [most probable] to [least probable] are classified into four levels and represented by quaternary values) are appropriate. Has to be processed to divide the data into four values, which causes a further delay in processing.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a PSK signal receiving apparatus capable of processing an input signal at a high speed with a simpler configuration than the conventional one.

[0008]

A PSK signal receiving apparatus according to the present invention receives a PSK signal, corrects and demodulates a phase error, and performs error correction and decoding using soft decision data. In the PSK signal receiving apparatus, a memory table in which phase error data used for demodulation is stored in advance, and a memory table in which gain data for soft decision used for error correction are stored in advance are provided. It is characterized in that phase error data and soft decision gain data are obtained by referring to these memory tables using signal values as addresses.

A memory table is provided which stores data obtained by integrating phase error data used for demodulation and soft decision gain data used for error correction,
It is characterized in that the phase error data and the soft decision gain data are obtained simultaneously by referring to the memory table with the in-phase and quadrature signal values of the demodulator output as addresses.

Further, the soft decision gain data is data of 2 bits and 4 divisions.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the device configuration of the PSK signal receiving device of the present invention.
In FIG. 1, 1 is a quadrature demodulator, 2 is an A / D converter, 3
Is a phase controller, 4 is a soft decision gain data adder, 5 is a decoder, 6 is a memory table, 7 is a phase control amount calculator, 8
Indicates a low-pass filter.

Next, the operation will be described. In FIG. 1, a received PSK (modulation) signal is divided by a quadrature demodulator 1 into two signals (in-phase and quadrature signals) whose phases are shifted from each other by 90 degrees, and is input to an A / D converter 2 and converted into a digital signal Is converted to The phase of the in-phase and quadrature signals converted into digital signals by the A / D converter 2 is rotated by the phase controller 3 in accordance with the output from the phase control amount calculator 7.
Output to the memory table 6 and the soft decision gain data adder 4.

As described above, this type of PSK signal receiving apparatus has a means for correcting a phase error caused by a frequency offset and noise of a demodulated PSK signal, and a means for effectively performing error correction performed by a decoder. Means for obtaining gain data for soft decision. That is, the received PSK
If the (modulation) signal has a frequency offset, the symbol identification point is gradually shifted from the reference phase due to the frequency offset, and a so-called phase error occurs. appear. Therefore, in demodulating a PSK (modulation) signal, it is necessary to remove the phase error and return the symbol identification point to the reference phase. Further, even if the operation of returning the symbol identification point to the reference phase is performed, if the PSK (modulation) signal contains noise, the signal does not return to the reference phase accurately, and a shift occurs from the reference phase. A means for constantly detecting and correcting the phase error is required.

The means for detecting the phase error may be configured to calculate by calculation as in a conventional apparatus.
The configuration may be such that the difference from the reference phase is only obtained and the data is read from the memory table. In the present invention, such a configuration is employed. That is, the output from the phase controller 3 is input to the memory table 6, and an error value previously stored in the memory table 6 is read using the in-phase signal value and the quadrature signal value as addresses, and the read phase error value is read. Is output to the low-pass filter 8. FIG. 2 is a diagram showing the contents of the memory table 6.

As described above, since the phase error is caused by noise except for the initial frequency offset, the magnitude of the phase error is proportional to the ratio between the signal component and the noise component. . On the other hand, as described above, in this type of PSK signal receiving apparatus, error correction is performed by a decoder, and in order to perform the error correction effectively, soft-decision gain data is generated and the soft-decision gain data is added to demodulated data. Thus, a soft decision gain data generating means is required. In the conventional apparatus, the output phase error is calculated by a soft decision gain data calculator 10 in four steps. , And soft decision gain data is generated.

However, the gain data for soft decision, that is, the data representing the certainty of the data, is proportional to the ratio between the signal component and the noise component of the data, and therefore is also proportional to the above-described phase error. Therefore, in the present invention, as shown in FIG.
Soft decision gain data (4 bits of 2 bits can be considered as an example of this data) is added to the phase error data, and integrated data is stored in the memory table 6. Alone, the soft-decision gain data is also detected at the same time as the detection of the phase error, and the detected soft-decision gain data is output to the soft-decision gain data adder 4. In the conventional device, two arithmetic processes of calculating the phase error and then obtaining the soft decision gain data can be obtained only by referring to the memory table once in the present invention, and high-speed processing can be performed. In addition, since a calculation circuit for performing a complicated calculation can be omitted, the configuration can be simplified.

In the next low-pass filter 8, the high-frequency component of the phase error output from the memory table 6 is removed.
The averaged signal is input to the phase control amount calculator 7,
The output phase of the phase controller 3 is rotated by this phase control amount,
Feedback control is performed so as to match the reference phase. The soft-decision gain data output from the memory table 6 is sent to the phase controller 3 by the soft-decision gain data adder 4.
And input to the decoder 5.

In the above-described embodiment, as shown in FIG. 3, the integrated data obtained by adding each soft decision gain data to each phase error data is stored in the memory table 6. A configuration (not shown) may be provided with two memory tables, a memory table storing error data and a memory table storing gain data for soft decision.

[0019]

As described above, the PSK signal receiving apparatus according to the present invention is capable of converting the phase error and the soft decision gain data at a time by referring to the memory table using the in-phase signal value and the quadrature signal value as addresses. Since such a configuration is adopted, there is an effect that a device capable of high-speed processing with a simple configuration can be obtained without requiring complicated arithmetic processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PSK signal receiving device of the present invention.

FIG. 2 is a diagram showing contents of a memory table shown in FIG. 1;

FIG. 3 is a diagram illustrating an example of data stored in a memory table of FIG. 2;

FIG. 4 is a block diagram for explaining a conventional PSK signal receiving apparatus of this type.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Quadrature demodulator 2 A / D converter 3 Phase controller 4 Soft decision gain data adder 5 Decoder 6 Memory table 7 Phase control amount calculator 8 Low-pass filter 9 Phase error detector 10 Soft decision gain data Calculator

Claims (3)

[Claims] 1. A PSK (Phase Shift Keying: phase modulation) signal is received, a phase error is corrected and demodulated,
In a PSK signal receiving apparatus that performs error correction and decoding using soft decision data, a memory table in which phase error data used for demodulation is stored in advance, and soft decision gain data used for error correction is stored in advance. PSK signal reception characterized by providing a stored memory table, and obtaining phase error data and soft decision gain data by referring to these memory tables with the in-phase and quadrature signal values of the demodulator output as addresses. apparatus. 2. A PSK signal receiving apparatus which receives a PSK signal, corrects a phase error, demodulates the data, and performs error correction using soft decision data to decode the PSK signal. There is provided a memory table storing data obtained by integrating soft decision gain data used for error correction with the phase error data by referring to the memory table with the in-phase and quadrature signal values of the demodulator output as addresses. PSK characterized in that it simultaneously obtains soft decision gain data.
Signal receiver. 3. The PSK signal receiving apparatus according to claim 1, wherein said soft decision gain data is 2-bit 4-part data.