JP2000216839A - Demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator without causing deterioration of characteristic such as an error rate through a long period. SOLUTION: A signal having a frequency nearly equal to the carrier of an inputted modulation signal (IFIN) is oscillated by an oscillator 3 and the output phase of this oscillation signal is π/2-shifted by a π/2 shifter 4. These output and modulation signal are multiplied to each other by a multiplier 12 to be A/D converted (5, 6). In addition, the amplitude difference between Ich and Qch of orthogonal components is corrected by an AGC 7, and an AGC 9 places the respective signals of Ich and Qch on a normal signal point. A detector 12 outputs an error signals Ei and Eq being the deviation of a carrier frequency from a local frequency and an orthogonal controller 13 digitally and automatically removes an orthogonal error. Thus, the orthogonal errors of the demodulator can be removed all digitally and automatically without requiring an analog element and manual adjustment. In addition, since the demodulator is entirely digitized, it can easily be made into an LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a demodulator and, more particularly, to a demodulator provided with an automatic quadrature controller.

[0002]

2. Description of the Related Art Conventionally, a demodulator is generally used in a demodulator in a digital radio communication system. FIG. 14 is a block diagram showing a conventional embodiment. According to FIG. 14, the conventional embodiment includes multipliers 1, 2, an oscillator 3, a π / 2 shifter 4,
A / D converters 5, 6, AGC 7, 9, complex multiplier 8, error detector 12, LPF 11, and angle signal si
NCO (Nu) which is a numerically controlled oscillator that outputs n and cos
(Merical Controlled Oscillator) 10. The function of each of these units is as follows.
Except that i and Eq are not output, it has the same function as each unit applied to the embodiment of the present invention.

[0003] The above conventional example is significantly different from the present invention,
That is, there is no quadrature error controller. Conventionally, the quadrature adjustment is performed by manually adjusting the π / 2 shifter 4.

[0004]

The prior art described above requires an extra time for device fabrication because it does not have a quadrature error controller as described above. Further, the manually adjusted π / 2 shifter has a high possibility of causing a temporal variation due to the temperature, humidity, and the like of the analog component, and it is difficult to guarantee orthogonality for a long period of time. When a quadrature error occurs, a demodulated signal as shown in FIG. 12 or 13 is obtained, which naturally causes a problem that characteristics such as an error rate deteriorate.

[0005] In recent years, analog ICs as quadrature demodulators exist, and the local oscillators are automatically quadrature, but the accuracy is not high. In particular, it is difficult to say that it corresponds to a multi-level modulation method such as QAM, and the current situation is that it must be manually adjusted.

The present invention eliminates the need for manual adjustment by performing orthogonal control digitally and automatically.
It is another object of the present invention to provide a demodulator that does not cause deterioration of characteristics such as an error rate over a long period.

[0007]

In order to achieve the above object, a demodulator according to the present invention comprises an oscillator oscillating a signal having substantially the same frequency as a carrier of an input modulated signal, and a signal oscillated by the oscillator. A π / 2 shifter for shifting the output phase of π / 2 by π / 2, a multiplier for multiplying the output of the oscillator and the π / 2 shifter with the modulation signal, and an A / D converter for A / D converting the output of the multiplier. , A first AGC for correcting the amplitude difference between Ich and Qch of the orthogonal component, and Ich, Q
The second AG that puts the signal of each channel on the normal signal point
C, an error detector for correcting the difference between the carrier frequency and the local frequency, and error signals Ei and Eq output from the error detector are input, and the orthogonal error is digitally and automatically removed. And a quadrature controller.

Further, the demodulator has a complex multiplier which is a quasi-synchronous detection demodulator and a numerically controlled oscillator (NCO), and a phase error signal output from the error detector is rotated by the numerically controlled oscillator. Signals sin and cos are input to the quadrature controller and the complex multiplier.

The multiplier and the A / D converter each have two systems connected in series. The oscillator and the oscillating signal obtained by shifting the oscillating signal by π / 2 by the π / 2 shifter are provided. The input modulated signal is multiplied by I
It is preferable to obtain the respective signal components of ch and Qch.

Further, the demodulator has a loop filter,
The phase error signal output from the error detector may be input to the numerically controlled oscillator via the loop filter.

The above quadrature controller uses the error signals Ei and Eq output from the error detector and a numerically controlled oscillator (NC).
By complexly multiplying the outputs sin and cos of O), error signals Ei and E after phase rotation by the complex multiplier are obtained.
It is preferable to estimate an error signal before phase rotation from q, set the error signal at a position before the phase rotation before the complex multiplier, and correct the quadrature error using the estimated error signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a demodulator according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 11, there is shown one embodiment of the demodulator of the present invention.

FIG. 1 is a block diagram showing a configuration example of a demodulator according to an embodiment of the present invention. The demodulator according to the present embodiment includes multipliers 1 and 2, an oscillator 3, a π / 2 shifter 4,
/ D converters 5, 6, AGC 7, 9, complex multiplier 8,
It comprises an error detector 12, an LPF 11, an NCO (Numerically Controlled Oscillator) 10, and a quadrature controller 13.

In the following description of the present invention, it is assumed that the detection system of the demodulator is quasi-synchronous detection, and that the input modulated signal is quadrature modulation such as QPSK or QAM. The notations Ich and Qch, which are general notations, are used.

The oscillator 3 is a local oscillator having substantially the same frequency as the input IF signal.
IF IN is multiplied by the output of the oscillator whose phase is shifted by π / 2 by the π / 2 shifter 4. As a result, the orthogonal components (channels) Ich and Qc
h are obtained. These are converted into digital signals by A / D converters 5 and 6, and Ich1,
Output as Qch1. Since this demodulator performs quasi-synchronous detection, Ich1 and Qch1 are not perfect baseband signals but include the difference between the carrier frequency and the frequency and phase of the oscillator 3.

The quadrature controller 13 receives Ich1 and Qch1 as inputs, and outputs an error signal E input from the error detector 12.
i, Eq, and rotation angle signal s input from NCO 10
The signal Ic from which the quadrature error has been removed using in and cos
h2 and Qch2 are output.

The AGC 7 receives Ich2 and Qch2 as inputs, and outputs a signal Ich from which the amplitude difference between Ich and Qch has been removed.
3. Output Qch3.

The complex multiplier 8 receives Ich3 and Qch3 as inputs, and outputs a rotation angle signal si input from the NCO 10.
Using n and cos, the signal Ich4 and Qch4 from which the difference between the frequency of the carrier included in Ich3 and Qch3 and the frequency of the oscillator 3 has been removed is output.

The AGC 9 uses the amplitude error signal Ad input from the error detector 12 to demodulate signals Ich5, Qc
Control is performed so that h5 falls on a regular signal point.

The error detector 12 uses Ich5 and Qch5 input from the AGC 9 to generate phase error signals Pd1 and Pd1.
It outputs error signals Ei, Eq and amplitude error signal Ad. The phase error signal Pd1 is smoothed by the LPF 11, and is input to the NCO 10 as the smoothed phase error signal Pd2.

The NCO 10 converts the phase error signal Pd2 input from the LPF 11 into rotation angle signals sin and cos and outputs the signals.

Hereinafter, each block will be described in detail. FIG. 2 is a block diagram showing a configuration example of the AGC 7. 2, the AGC 7 includes a multiplier 71, absolute value calculators 72 and 73, an adder 74, and an LPF 75. The AGC 7 adjusts the amplitude of Ich to the amplitude of Qch by comparing the amplitudes of Ich and Qch.

FIG. 3 is a block diagram showing a configuration example of the AGC 9. As shown in FIG. 3, AGC 9 includes multipliers 91 and 9
2. It is composed of an LPF 93. The AGC 9 uses the amplitude error signal Ad input from the error detector 12 to
Control is performed so that the input signals Ich4 and Qch4 are at the normal signal point positions, and demodulated signals Ich5 and Qch5 are obtained.

FIG. 4 is a block diagram showing a configuration example of the LPF 75 included in the AGC 7 and the LPF 93 included in the AGC 9. This is a simple integrator using a flip-flop 77 and an adder 76.

FIG. 5 is a block diagram showing a configuration example of the LPF 11. In FIG. 5, the LPF 11 includes a flip-flop F / F 111, multipliers 112 and 113, and adders 114 and 115. This is a general second-order lag-lead filter. Normally, in a carrier regeneration loop composed of a complex multiplier, a phase detector, an LPF, and an NCO, it is necessary to cancel the frequency offset, so that a second-order or higher configuration is required.

FIG. 6 is a block diagram showing a configuration example of the complex multiplier 8. As shown in FIG. 6, the complex multiplier 8 includes multipliers 81 to 84 and adders 85 and 86. By the operation according to the block diagram of FIG. 6, the frequency and phase offset components of the carriers included in Ich3 and Qch3 are removed.

FIG. 7 is a block diagram showing a configuration example of the NCO 10. As shown in FIG. In FIG. 7, the NCO 10 is an integrator 10
3, cos () 101 and sin () 102. By integrating the phase error signal smoothed by the LPF 8, a frequency error signal frq is obtained. With this frequency error signal frq as input, co
s () 101 and sin () 102 are cos
(Frq), the value of sin (frq) is converted to the angle signal sin,
Output as cos.

FIG. 8 is a block diagram showing a configuration example of the error detector 12. As shown in FIG. In FIG. 8, the error detector 12
It comprises multipliers 703 to 705, an adder 706, and signal point error detectors 701 and 702.

The signal point error detectors 701 and 702 detect errors of the input signals Ich3 and Qch3 from regular signal point positions, and output error signals Ei and Eq. Here, the error signals Ei and Eq output negative values when the input signals Ich3 and Qch3 deviate in the positive direction from the normal signal point positions, and output positive values when the input signals Ich3 and Qch3 deviate in the negative directions. And These error signals Ei, Eq and Ic
h3, polarity signals Di, Dq of Qch3 (Ich3, Qc
Using h3), a phase error signal Pd1 is obtained. The amplitude error signal Ad is obtained by multiplying the error signal Ei and the polarity signal Di, or by multiplying the error signal Eq and the polarity signal Dq. Here, it is obtained by multiplying the error signal Ei by the polarity signal Di.

FIG. 9 is a block diagram showing the configuration of the quadrature controller 13 which is a feature of the present invention. In FIG.
The orthogonal controller 13 includes an adder 1101, a multiplier 1102,
It comprises an LPF 1103, delay units 1104 and 1105, and a quadrature error detector 1106.

FIG. 10 shows an example of the configuration of the orthogonal error detector 1106. In FIG. 10, a quadrature error detector 1106
Are adders 1107-1109, multipliers 11010-11
And 15. In FIG. 10, adders 1108 to 1108
The portion composed of 109 and multipliers 110 to 1115 is almost the same as the complex multiplier shown in FIG. 6, but differs only in that the rotation direction is opposite. The error signals Ei, Eq input from the error detector 12 are angle signals sin,
The signal is inversely rotated by cos and restored as a signal before being rotated by the complex multiplier 6. The inverted signal and the Ich input through the delay units 1104 and 1105
2. The result of multiplying the sign bit of Qch2 by an adder 11
The signal added at 07 is defined as a quadrature phase error signal Qd. The quadrature error signal Qd is smoothed by the LPF 1103, then multiplied by Qch1 and added to Ich1 to remove the quadrature error.

(Explanation of Operation) The operation of the present embodiment will be described below focusing on the quadrature error controller which is a feature of the present invention. In the following description, FIGS. 12 and 13 showing an example of a demodulated signal when there is an orthogonal shift are used.

In FIG. 1, the processing by the orthogonal controller 13 is performed before the phase is rotated by the complex multiplier 8, whereas the signal point error signals Ei, Eq
Is obtained from the signal after the phase rotation. For this purpose, it is necessary to estimate an error signal before phase rotation from the obtained signal point error signal.

The signal point error signal and the phase error signal are obtained by the error detector 12 shown in FIG. The signal point error signals Ei and Eq are obtained by detecting errors of the input signals Ich3 and Qch3 from the original signal point positions.
These signal point error signals Ei, Eq and Ich3, Q
Using the polarity signals Di and Dq of ch3 (signs of Ich3 and Qch3), the phase error signal Pd1 is generally obtained by the following equation. Pd1 = Ei · Dq−Eq · Di

The conversion from the phase error to the frequency error is shown in FIG.
This is performed by the NCO 10 shown in FIG. Since the frequency is obtained by integrating the phase, the phase error signal Pd1 is
And then integrate to obtain the frequency error signal f
req is obtained. Further, the rotation angle signal sin (fr
eq) and cos (freq) and output from the NCO.

FIG. 6 is a block diagram showing a configuration example of the complex multiplier 8. As shown in FIG. Here, the operation of rotating the inputs Ich3 and Qch3 by the angle signal freq obtained from the error signal is repeated in a loop including the error detector 12, the LPF 11, and the NCO 10, so that Ich3,
The control is performed so that the difference between the frequency of the carrier and the frequency and phase of the oscillator 3 included in Qch3 is eliminated.

On the other hand, multipliers 1112 to 1115, adders 1108 and 1108 in the orthogonal error detector shown in FIG.
The operation performed at 109 is an operation that gives the signal point error signals Ei and Eq rotation completely opposite to the rotation performed by the complex multiplier 8.

FIG. 11 shows the relationship between E and E 'on the IQ phase plane. The vector from the correct signal point position to the output signal of the complex multiplier 8 is the error signal obtained by the error detector 12. Assuming that the phase has been rotated by θ by the complex multiplier 8, the input signal of the complex multiplier 8, that is, the signal before the phase rotation is obtained by rotating the output signal of the complex multiplier 8 by −θ. Therefore, the error signal E ′ before the phase rotation is also obtained by rotating E by −θ.

The error signal obtained above indicates whether the reproduced signal is shifted in the positive direction or the negative direction with respect to the normal signal point position. In order to perform orthogonal control, it is necessary to convert this into an orthogonal error signal.

FIGS. 12 and 13 show a demodulated signal on the complex plane of IQ when there is quadrature shift when demodulating a QPSK-modulated signal. 12 differs from the case where the carrier frequency completely matches the local frequency, and the case of FIG. 13 where the carrier frequency does not match the local frequency. These matches / mismatches are determined by the phase rotation before and after the complex multiplier 8,
The relationship of FIG. 12 is not made / the case of FIG. 13 is made. That is, FIG. 12 shows a case where the carrier frequency completely matches the local frequency in both cases, that is, a case where the phase rotation is not performed before and after the complex multiplier. FIG. 13 shows a case where the phase rotation is performed before and after the complex multiplier 8 because the carrier frequency does not match the local frequency.

From FIG. 12, since the distance between each signal point and the origin is originally equal, the signal point that should be on the vertex of the square is
You can see that it has a diamond shape. In this way, when the phase rotation by the complex multiplier is applied, a circle is drawn around the normal signal point as shown in FIG. To correct these states, as shown in FIG. 12, an error signal that corrects a diagonal shift from a normal signal point is required. To obtain this signal, an error signal Qd as in the following equation may be used. Qd = Ei · Dq + Eq · Di

Although the polarity signal and the error signal must be obtained from the same signal, the error signal is considered to be delayed when passing through the complex multiplier and the phase detector. To do so, a delay unit 106 is required.

Although the quadrature error signal was obtained as described above,
How is the quadrature error controlled? I
The F input signal is A (t), and the angular velocity of the local oscillator is ω
[Rad / s] and the orthogonal error δ [rad], A
The Ich and Qch signals input to / D are given by the following equations.

Ich = A (t) cos (ωt + δ) = A (t) cosωt · cosδ−A (t) sinωt · sinδ = A (t) cosωt · cosδ−Qch · sinδ Qch = A (t) sinωt

In order for this signal to be demodulated normally, Ich
Needs to be eliminated. However, in the following terms, only the gain of Ich is changed and can be corrected by AGC. A (t) cosωt · cosδ

Therefore, the following terms need to be corrected. −Qch · sin δ

Since δ can be regarded as a constant in the short term, the value obtained by multiplying the quadrature error signal by the value of Qch is represented by Ic
By performing the process of subtracting from h, the orthogonal error can be corrected.

The present invention is characterized in that a demodulator in a digital radio communication system is provided with an automatic quadrature controller for performing control using an angle signal and an error signal used for frequency offset control.

As shown in FIG. 1, the demodulator according to the present embodiment having the above characteristics has a local oscillator 3 having substantially the same frequency as the carrier of the modulation signal input to the demodulator, and has an output phase of π .Pi. / 2 shifter 4 for shifting by 1/2, multipliers 1 and 2 for multiplying the outputs of local oscillator 3 and .pi. / 2 shifter 4 with the IF input, A / D 5 for A / D converting the outputs of multipliers 1 and 2, 6, AGC 7 for correcting the amplitude difference between Ich and Qch, AGC 9 for putting each signal of Ich and Qch on a regular signal point, error detector 12 for correcting a deviation between carrier frequency and local frequency, loop filter In addition to the configuration of a normal quasi-synchronous detection demodulator such as an LPF 11, a numerically controlled oscillator (NCO) 10, and a complex multiplier 8, the output si of the NCO 10
A quadrature controller 13 having n, cos, and error signals Ei, Eq output from the error detector 12 as inputs is provided.

In this demodulator, the quadrature controller 13
Error signal Ei, Eq output from error detector 12 and NCO
9 by multiplying sin and cos, which are the outputs of the phase shifter 9, by the complex multiplier 8, the error signals Ei, E after the phase rotation.
From q, the error signal before the phase rotation is estimated. Since the present quadrature controller is at the position before the phase rotation, the quadrature error is corrected using the estimated error signal.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the detection method of the demodulator is quasi-synchronous detection, the input modulation signal is QPSK,
It is quadrature modulation such as QAM. However, the quasi-synchronous detection need not be performed as long as the error signal after the frequency and phase offset correction and the rotation angle information at the time of the frequency and phase offset correction can be obtained. The modulation method is other than QPSK and QAM.
SK or APSK may be used.

[0052]

As is apparent from the above description, the demodulator of the present invention oscillates a signal having substantially the same frequency as the carrier of the input modulated signal, and changes the output phase of this signal to π / 2.
A / D conversion is performed by multiplying each output signal by the modulation signal. Further, Ich and Qc of the orthogonal component
h, the signals of Ich and Qch are put on regular signal points, and the difference between the carrier frequency and the local frequency is corrected. The error signal E which is the output of this error detector is obtained.
Inputting i and Eq, digitally and automatically removing orthogonal errors.

According to this configuration, the analog element is
No manual adjustments required, all digital and
It is possible to automatically remove the quadrature error of the demodulator. In addition, since it is fully digitalized, it is easy to implement an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a demodulator according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an AGC 7 in FIG.

FIG. 3 is a block diagram showing a configuration example of an AGC 9 in FIG.

FIG. 4 is a block diagram showing a configuration example of LPFs 75 and 93 in FIGS. 2 and 3;

FIG. 5 is a block diagram illustrating a configuration example of an LPF 11 in FIG. 1;

FIG. 6 is a block diagram showing a configuration example of a complex multiplier 8 in FIG.

FIG. 7 is a block diagram showing a configuration example of an NCO 10 in FIG.

FIG. 8 is a block diagram showing a configuration example of an error detector 12 in FIG.

FIG. 9 is a block diagram showing a configuration example of an orthogonal controller 13 in FIG. 1;

FIG. 10 is a block diagram illustrating a configuration example of a quadrature error detector in FIG. 9;

FIG. 11 is a diagram for explaining reverse rotation of an error signal.

FIG. 12 is a first diagram illustrating an example of a demodulated signal when there is an orthogonal shift.

FIG. 13 is a second diagram illustrating an example of a demodulated signal when there is orthogonal displacement.

FIG. 14 is a block diagram illustrating a configuration example of a conventional demodulator.

[Explanation of symbols]

1, 2 Multiplier 3 Oscillator 4 π / 2 shifter 5, 6 A / D converter 7, 9 AGC 8 Complex multiplier 10 NCO (Numerical Controlled)
Oscillator) 11, 75, 93 LPF 12 Error detector 13 Quadrature controller 71, 81 to 84, 91, 92, 112, 113, 70
3-705 Multiplier 72, 73 Absolute value calculator 74, 76, 85, 86, 114, 115, 706 Adder 101 cos () 102 sin () 103 Integrator 701, 702 Signal point error detector

Claims (6)

[Claims] An oscillator for oscillating a signal having substantially the same frequency as a carrier of an input modulated signal; a π / 2 shifter for shifting an output phase of a signal oscillated by the oscillator by π / 2; a multiplier for multiplying the output of the π / 2 shifter with the modulation signal; an A / D converter for A / D converting the output of the multiplier; and a first for correcting an amplitude difference between Ich and Qch of a quadrature component. A
GC, a second AGC for putting each of the Ich and Qch signals on a proper signal point, an error detector for correcting a deviation between a carrier frequency and a local frequency, and an error signal which is an output of the error detector A quadrature controller which receives Ei and Eq and automatically and digitally removes quadrature errors; and a quadrature controller. 2. The demodulator further includes a complex multiplier that is a quasi-synchronous detection demodulator, and a numerically controlled oscillator (NCO), and a phase error signal output from the error detector is the numerically controlled oscillator. 2. The demodulator according to claim 1, wherein the signals are rotation signals sin and cos, and are input to the quadrature controller and the complex multiplier. 3. The multiplier and the A / D converter each have two systems connected in series, and the oscillation signal of the oscillator and the π / 2 shifter are used to convert the oscillation signal to π /
3. The demodulator according to claim 1, wherein each of the Ich and Qch signal components is obtained by multiplying the input modulated signal by an oscillation signal shifted by two. 4. The demodulator further includes a loop filter, and a phase error signal output from the error detector is input to the numerically controlled oscillator via the loop filter. Item 4. The demodulator according to item 2 or 3. 5. The quadrature controller outputs the error signals Ei and Eq output from the error detector and the numerically controlled oscillator (NC).
O), by multiplying the output sin and cos by complex, the error signal E after phase rotation by the complex multiplier is obtained.
5. The demodulator according to claim 2, wherein an error signal before phase rotation is estimated from i and Eq. 6. The quadrature controller according to claim 5, wherein the quadrature controller is set at a position before the phase rotation in a stage preceding the complex multiplier, and corrects a quadrature error based on the estimated error signal. Demodulator.