JP2000216376A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent concentration of currents at the end of a gate electrode. SOLUTION: A gate electrode 9a and, along the gate electrode 9a a plurality of island-shaped gate electrodes 9b formed in the same process as the gate electrode 9a are made on a silicon substrate 1 via a gate oxide film 7. Oxide film sidewalls 11 are made at the sidewalls of the gate oxide film 7, the gate electrode 9a, and the island-shaped gate electrode 9b. A diffused layer 13 is formed in a silicon substrate 1. Titanium silicide layers 15a and 15b are made on the surface of the silicon substrate 1 on the diffused layer 13, the topside of the gate electrode 9a, and the topside of the island-shaped gate electrode 9b. A field width x' between the gate electrode 8a and the island-shaped gate electrode 9b and the field width x' between the island-shaped gate electrodes are 0.3 μm, and the titanium silicide layer 15a in the region produces thin line effect, so that the resistance value in the diffused layer region adjacent to the gate electrode 9a rises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a metal silicide layer at least on a diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, salicide (self-aligned-silic
ide) In the MOSFET in which the metal silicide is formed on the gate electrode and the diffusion layer by performing the process, the ES is lower than the MOSFET in which the salicide process is not performed.
It is generally known that D (Electro-Static Discharge) resistance is significantly deteriorated. The reason for this is that the diffusion layer region of the MOSFET that has undergone the salicide process has a low resistance value, and when a discharge current due to static electricity flows into the diffusion layer, particularly the drain diffusion layer, the current concentrates at the end of the gate electrode and the gate electrode Local thermal destruction may occur in the extreme part of the gate insulating film.

[0003] To solve the problem that the ESD resistance deteriorates,
JP-A-5-3173, JP-A-8-279565 and JP-A-10-70266 disclose that a silicon oxide film is formed on a diffusion layer near a gate electrode of a MOSFET before forming a silicide layer. By depositing
A method has been proposed in which a silicide layer is not formed on a diffusion layer in the vicinity of a gate electrode so that current does not concentrate at an end of the gate electrode (prior art 1).

As another method for preventing the deterioration of the ESD resistance, Japanese Unexamined Patent Application Publication No. 9-260590 discloses a method in which a gap is provided between a silicide layer on a diffusion layer and a sidewall of a gate electrode, and a PN of a MOSFET is provided. A method has been proposed in which the gap between the junction and the silicide layer is widened so that current concentration does not occur at the end of the gate electrode (prior art 2). As another method for preventing the deterioration of the ESD resistance, Japanese Patent Application Laid-Open No. 9-306998 discloses that a drain diffusion layer is formed after forming a polysilicon pattern in an island shape on a drain diffusion layer region. There has been proposed a method of preventing concentration of current by increasing the resistance value of a region (prior art 3).

[0005]

In the prior art 1, the ES
In order to leave a silicon oxide film on a diffusion layer near the gate electrode of a MOSFET such as an I / O cell for which the D resistance needs to be improved, and to prevent the silicon oxide film from remaining in other MOSFETs, It is necessary to select a formation region and form a silicon oxide film by a lithography technique and an etching method. Therefore, there is a problem that the manufacturing period is longer than a normal manufacturing period.

In the prior art 2, since it is necessary to perform high-concentration impurity ion implantation for forming a lightly doped drain (LDD) diffusion layer after the formation of the metal silicide layer, the metal silicide layer becomes amorphous, and the resistance of the metal silicide layer is reduced. There is a possibility that the resistance value of the region that needs to be changed may increase. In the prior art 3, although the resistance value of the drain diffusion layer region increases, a low-resistance silicide layer is formed on the diffusion layer adjacent to the end of the gate electrode. Concentration may occur, and the gate insulating film may be broken.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which the resistance value of a diffusion layer region adjacent to a gate electrode is set to a sufficiently high value to prevent current from concentrating on an end of the gate electrode. . Another object of the present invention is to provide a method for manufacturing such a semiconductor device without increasing the manufacturing period.

[0008]

A semiconductor device according to the present invention is provided on a silicon substrate of a first conductivity type via a gate insulating film, a strip-shaped gate electrode, and a predetermined distance from the gate electrode. A plurality of island-shaped gate electrodes are formed at a predetermined distance from each other, and a diffusion layer of the second conductivity type is formed on the silicon substrate excluding the gate electrode region and the island-shaped gate electrode region. The metal silicide is formed on the layer, and the width of the metal silicide formation region between the gate electrode and the island-like gate electrode and the width of the metal silicide formation region between the adjacent island-like gate electrodes are determined by the metal silicide formation region. The metal silicide formed thereon has such a size as to cause the fine wire effect of the silicide.

The thin line effect of the silicide layer is a phenomenon in which the sheet resistance of the silicide layer increases when the width of the region where the silicide layer is formed (hereinafter referred to as field width) becomes smaller than a certain dimension. FIG. 1 is a graph showing a thin line effect of a titanium (Ti) silicide layer formed in an active region defined by a device isolation oxide film (LOCOS). The horizontal axis represents the field width (μm), and the vertical axis represents the sheet resistance value Rs (Ω / □). Here, after titanium was deposited on the active region to a thickness of 500 °, a salicide treatment at a lamp annealing temperature of 725 ° C. was performed to form a titanium silicide layer.

FIG. 1 shows that, in the titanium silicide layer formed under the above conditions, the sheet resistance starts to increase when the field width becomes 0.4 μm, and the sheet resistance increases as the field width becomes smaller. The dimension of the field width at which the thin line effect starts to occur varies depending on the type of metal and the film thickness, the lamp annealing temperature, or the reforming of the silicon substrate surface by amorphization.

The thin line effect of silicide is a factor that limits the miniaturization of the device. In the present invention, this phenomenon is used to prevent the current from being concentrated on the edge of the gate electrode. That is, a plurality of island-shaped gate electrodes are formed on the diffusion layer region near the gate electrode where the ESD resistance is likely to be degraded due to the formation of the metal silicide layer, with a field width such that the thin line effect of silicide occurs. To increase the resistance value. As a result, current does not concentrate on the end of the gate electrode, and deterioration of the ESD resistance can be suppressed.

A method of manufacturing a semiconductor device according to the present invention includes the following steps (A) to (E). (A) a step of forming a gate insulating film on a silicon substrate of the first conductivity type; (B) depositing a polysilicon film on the gate insulating film, and patterning the gate insulating film and the polysilicon film; A gate electrode, an island-like gate electrode, and a metal silicide formed by a process described later on a silicon substrate between adjacent gate-like gate electrodes and between adjacent island-like gate electrodes cause a thin line effect. Forming a gate electrode and an island-shaped gate electrode with a distance between the gate electrodes, (C) forming a sidewall on the side wall of the gate electrode and the island-shaped gate electrode, (D) forming the gate electrode, the island-shaped gate electrode and the side Forming a second conductivity type diffusion layer on the silicon substrate using the wall as a mask; (E) forming a metal silicide on the gate electrode, the island-like gate electrode and the diffusion layer Forming.

In the method of manufacturing a semiconductor device according to the present invention, the island-shaped gate electrode is simultaneously patterned when the gate electrode is patterned, and the distance between the gate electrode and the island-shaped gate electrode and the distance between adjacent island-shaped gate electrodes are controlled. By doing so, the resistance value of the metal silicide layer formed on the diffusion layer adjacent to the gate electrode is increased, so that there is no need to provide a separate step for forming the island-shaped gate electrode, thereby increasing the manufacturing period. Without this, the resistance value of the diffusion layer region adjacent to the gate electrode can be made sufficiently high.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred example of a metal silicide of a semiconductor device according to the present invention is titanium silicide. The width of a metal silicide formation region between a gate electrode and an island-like gate electrode and the distance between adjacent island-like gate electrodes are different. The width dimension of the metal silicide formation region is preferably 0.5 to 0.1 μm. As a result, a thin line effect of silicide can be generated in the titanium silicide formation region, and the resistance value of the diffusion layer region adjacent to the gate electrode can be increased.

[0015]

2 (A) to 2 (C) and 3 (D) to 3 (F).
FIG. 1 is a plan view (left view) showing a semiconductor device according to an embodiment of the present invention together with a manufacturing method thereof, and a cross-sectional view at the AA ′ position and BB ′ position (right view) of the plan view. First,
The structure of the semiconductor device according to the present invention will be described with reference to FIG. An element isolation oxide film 3 having a thickness of 4000 ° is formed on a silicon substrate 1 by a selective oxidation method.
On the silicon substrate 1 in the active region 5 located at the opening of the element isolation oxide film 3, a band-shaped gate electrode 9a made of polysilicon having a thickness of 2500 ° is interposed via a gate oxide film 7 having a thickness of 80 °. A plurality of island-shaped gate electrodes 9b are formed along the gate electrodes 9a. The distance between the gate electrode 9a and the island-shaped gate electrode 9b, and the distance between the island-shaped gate electrode 9
The distance between b and 9b is a distance x, and the distance x is, for example, 0.6 μm. The dimension y of the island-shaped gate electrode 9b in the direction orthogonal to the gate electrode 9a is, for example, 1.0 μm. On the side walls of the gate oxide film 7, the gate electrode 9a, and the island-shaped gate electrode 9b, an oxide film sidewall 11 having a thickness of, for example, 0.15 μm on the surface of the silicon substrate 1 is formed. The field width (distance x ′) is, for example, 0.3 μm.

The gate electrode 9a, the island-shaped gate electrode 9b, and the side wall 11
The diffusion layer 13 is formed except for the region where is formed. Titanium silicide layers 15a and 15b are formed on the surface of the silicon substrate 1, the upper surface of the gate electrode 9a, and the upper surface of the island-shaped gate electrode 9b on the diffusion layer 13. The titanium silicide layers 15a and 15b are made of the same material, but are formed on the diffusion layer 13 between the gate electrodes 9a and the island-shaped gate electrodes 9b and on the diffusion layer 13 between the island-shaped gate electrodes 9b and 9b. The titanium silicide layer thus obtained is referred to as 15a, and the other titanium silicide layers are referred to as 15b.

Interlayer insulating film 17 covering the entire surface of silicon substrate 1
Is formed, and the diffusion layer 13 is formed on the interlayer insulating film 17.
A plurality of contact holes 19 are formed, including through holes reaching the upper titanium silicide layer 15b and through holes (not shown) reaching the titanium silicide layer 15b on the gate electrode 9a. Although not shown in the figure, a metal wiring is connected via a contact hole 19.

In this embodiment, the field width between the gate electrode 9a and the island-shaped
The field width between b and 9b is 0.3 μm, and the titanium silicide layer 15a formed in those regions produces a thin wire effect, so that the resistance value of the diffusion layer region adjacent to the gate electrode 9a can be increased. In addition, it is possible to prevent the current from concentrating on the end of the gate electrode 9a.

The dimension y of the island-shaped gate electrode 9b determines the area of the titanium silicide layer 19a that produces the thin line effect. If the dimension y is too long, the region having a high sheet resistance increases, so that the driving capability of the transistor is increased. If it is too short, the sheet resistance value will be low, so that improvement in ESD resistance cannot be expected. This dimension y depends on the transistor characteristics and ES
It is preferable to experimentally determine and determine a well-balanced relationship between the D tolerances. Since the size at which the thin line effect of the silicide layer starts to occur varies due to a change in the type and thickness of the metal, a change in the lamp annealing temperature, or a modification of the surface of the silicon substrate due to the amorphization, the field width x ′ is set in this embodiment. It is not limited to the illustrated one, but may be any dimension as long as a thin line effect is generated.

Next, one embodiment of a method of manufacturing the semiconductor device will be described with reference to FIGS. (A) An element isolation oxide film 3 is formed on a silicon substrate 1 by a selective oxidation method, and an active region 5 including an opening of the element isolation oxide film 3 is formed. In this embodiment, the element isolation oxide film 3 has a thickness of 4000
It is preferable to form it within the range of 0 °.

(B) After forming a gate oxide film 7 with a thickness of 80 ° on the silicon substrate 1 in the active region 5, a polysilicon film is deposited thereon with a thickness of 2500 °. And
The gate electrode 9a and the island-shaped gate electrode 9b are formed by patterning the polysilicon film and the gate oxide film 7 by photolithography and etching. In this embodiment, the distance x is 0.6 μm and the dimension y is 1.0 μm.
m. The thickness of the polysilicon film for the gate electrode 9a and the island-shaped gate electrode 9b is preferably in the range of 1000 to 3000 °.

(C) After a silicon oxide film is deposited on the silicon substrate 1 to a thickness of, for example, 1500 ° by the CVD method, the silicon oxide film is etched back to form the gate electrode 9a, the island-shaped gate electrode 9b and the gate oxide. A side wall 11 is formed on the side wall of the film 7. Since the film thickness of the sidewall 11 is almost the same as the deposited film thickness of the silicon oxide film, it is formed at 1500 °, that is, 0.15 μm, and is formed between the gate electrode 9a and the island-shaped gate electrode 9b that are opened by the distance x. The distance between the island-shaped gate electrodes 9b, 9b is reduced from both sides by the dimension of the thickness of the sidewall 11, and the field width x 'is about 0.3 μm.

(D) The gate electrode 9 is formed by ion implantation.
a, impurity implantation for forming a source region and a drain region of a MOSFET is performed on the silicon substrate 1 using the island-shaped gate electrode 9b and the side wall 11 as a mask. For NMOSFET, for example, 50 keV, 3 × 10
Arsenic is implanted under the condition of ¹⁵ cm ^-2 . After that, a heat treatment is performed at 850 ° C. for about 30 minutes in a diffusion furnace to activate the impurities and form the diffusion layer 13.

(E) Titanium is coated on the entire surface of the silicon substrate 1
After the film is deposited to a thickness of 00 °, a heat treatment at 600 to 800 ° C. is performed in an inert gas atmosphere by lamp annealing, and a titanium silicide layer is formed on the upper surface of the gate electrode 9a, the upper surface of the island-like gate electrode 9b and the exposed surface of the silicon substrate 1. 13a,
13b is formed. After that, unreacted titanium on the element isolation oxide film 3 and the sidewalls 11 is selectively removed with a mixed solution of ammonia and hydrogen peroxide solution. The thickness of the titanium film formed on the silicon substrate 1 is 200 to 600 °
Is preferably within the range. (F) After forming an interlayer insulating film 17 on the silicon substrate 1 and forming a contact hole 19 in the interlayer insulating film 17, a metal wiring is formed according to a wiring forming step in a normal LSI manufacturing process.

In this embodiment, the thin line effect is generated in the titanium silicide layer 15a on the diffusion layer 13 adjacent to the gate electrode 9a to increase the resistance of the diffusion layer region adjacent to the gate electrode 9a. Since the island-shaped gate electrode 9b is formed around the gate electrode 9a and the island-shaped gate electrode 9b is formed by the same photolithography process and etching process as the gate electrode 9a, the gate electrode 9a can be formed without increasing the manufacturing period. Concentration of current at the end can be prevented.

[0026]

In the semiconductor device according to the present invention, a plurality of islands are formed on the diffusion layer region adjacent to the gate electrode where the ESD resistance due to the formation of the silicide layer is feared, with a field width of such an extent that the thin line effect of silicide occurs. Since the gate electrode is formed so as to suppress an unnecessarily low resistance in that region, current concentration does not occur at the end of the gate electrode, and deterioration of ESD resistance can be suppressed. Further, in the method of manufacturing a semiconductor device according to the present invention, the island-shaped gate electrode is simultaneously patterned when the gate electrode is patterned, and the distance between the gate electrode and the island-shaped gate electrode and the distance between adjacent island-shaped gate electrodes are controlled. By doing
Since the resistance value of the metal silicide layer formed on the diffusion layer adjacent to the gate electrode is increased, the resistance value of the diffusion layer region adjacent to the gate electrode can be set to a sufficiently high value without increasing the manufacturing period. can do.

[Brief description of the drawings]

FIG. 1 is a graph showing a thin line effect of a titanium silicide layer formed on an active region.

FIG. 2 is a plan view (left figure) showing the first half of a semiconductor device manufacturing method according to an embodiment, and positions AA ′ and B in the plan view.
It is sectional drawing (right figure) in the -B 'position.

FIG. 3 is a plan view (left diagram) showing an embodiment of the semiconductor device together with the latter half of the same embodiment, and a cross-sectional view (right diagram) taken along positions AA ′ and BB ′ of the plan view. .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation oxide film 5 Active region 7 Gate oxide film 9a Gate electrode 9b Island-like gate electrode 11 Side wall 13 Diffusion layer 15a, 15b Titanium silicide layer 17 Interlayer insulating film 19 Contact hole

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 F term (Reference) 4M104 AA01 BB01 BB25 CC01 CC05 DD04 DD79 DD84 DD88 DD89 FF14 GG09 5F038 BH02 BH07 BH13 5F040 DA00 DA25 DB01 DB10 DC01 EC04 EC07 EC13 EC21 EH02 EK01 FA03 FA05 FA19 FC19 5F048 AB06 AB07 AC01 AC10 BA01 BB02 BB05 BB08 BB12 BG12 CC01 CC03 CC09 CC18 DA25

Claims (4)

[Claims] 1. A band-shaped gate electrode and a predetermined distance from a gate electrode on a silicon substrate of a first conductivity type with a gate insulating film interposed therebetween, and the respective spaces are also separated by a predetermined distance. A plurality of island-shaped gate electrodes are formed, a diffusion layer of a second conductivity type is formed on the silicon substrate excluding the gate electrode region and the island-shaped gate electrode region, and a metal silicide is formed on at least the diffusion layer. And
The width dimension of the metal silicide formation region between the gate electrode and the island-shaped gate electrode and the width dimension of the metal silicide formation region between the adjacent island-shaped gate electrodes are such that the metal silicide formed on the metal silicide formation region is A semiconductor device having a size that produces a thin wire effect of silicide. 2. The method according to claim 1, wherein the metal silicide is titanium silicide, and a width of a titanium silicide formation region between the gate electrode and the island gate electrode and a width of a titanium silicide formation region between the adjacent island gate electrodes. 2. The semiconductor device according to claim 1, wherein is 0.5 to 0.1 μm. 3. 3. A method for manufacturing a semiconductor device, comprising the following steps (A) to (E). (A) a step of forming a gate insulating film on a silicon substrate of a first conductivity type; and (B) depositing a polysilicon film on the gate insulating film, and then removing the polysilicon film and the gate insulating film. The width dimension between the gate electrode and the island-shaped gate electrode, in which the metal silicide formed by patterning is formed on the silicon substrate between the gate electrode and the island-shaped gate electrode and between the adjacent island-shaped gate electrodes by a later-described process causes a fine wire effect. Forming a gate electrode and an island-shaped gate electrode around the gate electrode with a width dimension between adjacent island-shaped gate electrodes; and (C) forming an insulating film sidewall on a side wall of the gate electrode and the island-shaped gate electrode. Forming a,
(D) using the gate electrode, the island-shaped gate electrode, and the sidewalls as a mask,
(E) forming a metal silicide on the gate electrode, the island-shaped gate electrode, and the diffusion layer. 4. The method according to claim 1, wherein the metal silicide is titanium silicide, and a distance between the sidewalls is 0.5.
The method for manufacturing a semiconductor device according to claim 3, wherein the thickness is from 0.1 μm to 0.1 μm.