JP2000216364A - Semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate which is also suitable for large- scale integration, and moreover suppresses the enlargement of a substrate and has circuit element formation regions on both sides. SOLUTION: A semiconductor substrate has a structure in which embedded insulating layers 12 and 13 consisting of oxide films are made on both sides of a silicon substrate 11, and that silicon layers 14 and 15 to serve as element forming regions for the formation of circuit elements are made severally thereon, and it becomes possible to form twice as many circuit elements as before by forming circuit elements in each silicon layer 14 and 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI substrate having a buried insulating layer in a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been required to reduce power consumption and cost. On the other hand, in recent years, SOI technology has been proposed and is rapidly progressing.

In this SOI technique, as shown in FIG. 4, an insulating layer 2 made of an oxide film is provided in a silicon semiconductor substrate 1, and a silicon layer 3 serving as an element forming region for forming a circuit element is formed thereon. Is formed.

[0004] Today, the quality of silicon crystal in the silicon layer 3 formed on the insulating layer 2 has been improved to a level comparable to that of a bulk silicon substrate, and many high-density integrated circuits have already been prototyped. . The low stray capacitance, radiation resistance, process simplicity, etc. of this SOI substrate are extremely suitable for logic LSIs and high-density DRAMs, etc., which will be required in the future. It's getting harder.

The low power consumption of the circuit elements formed on the SOI substrate is mainly due to the low stray capacitance and the small substrate bias effect even at a low power supply voltage. There are many reports that even at a low power supply voltage of 1 to 2 V, the circuit operates at a higher speed than a circuit element formed on a bulk silicon substrate.

Further, when such an SOI substrate is used for a DRAM, even if an alpha ray hits, the generation of electron-hole pairs can be virtually ignored, and the DRAM cell becomes soft error free. This greatly reduces the burden of technical development on DRAM capacitors.

[0007]

A conventional conventional SOI substrate has an element formation region formed only on one surface of a silicon semiconductor substrate.

[0008] However, when a further large-scale integration is required, it is inevitable to increase the size of the semiconductor substrate (chip) in accordance with the design rules as in the conventional bulk silicon substrate.

Accordingly, an object of the present invention is to provide a semiconductor substrate which is suitable for large-scale integration and has circuit element formation regions on both sides while suppressing an increase in the size of the substrate.

[0010]

According to the present invention, there is provided a semiconductor device comprising: a first and a second buried insulating layers formed on both surfaces of a substrate made of silicon;
And a first silicon layer and a second silicon layer which are formed on the respective buried insulating layers and serve as element forming regions for forming circuit elements.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a sectional structure of a semiconductor substrate according to an embodiment of the present invention.

This semiconductor substrate has embedded insulating layers 12 and 13 made of an oxide film on both surfaces of a substrate 11 made of silicon.
Are formed, and silicon layers 14 and 15 which are element forming regions for forming circuit elements are formed in the upper layers. With this structure, the so-called SOI (Silicon-On-I
nsulator) substrate.

By forming circuit elements on the respective silicon layers 14 and 15, it is possible to simply form twice as many circuit elements. For example, in the case of a memory element, a memory element having twice the capacity can be formed in a chip having a conventional size.

In connection between these circuit elements, wiring is formed and connected on the same surface as in the conventional case. On the other hand, in the connection between both surfaces, as shown in FIG. 2, a via hole 21 penetrating through the semiconductor substrate 11 may be formed, and after insulating around the hole 21, a conductor 22 may be embedded and used as a wiring.

The silicon layers 1 on both surfaces of the semiconductor substrate 11
After the circuit elements are formed on the circuit boards 4 and 15, electrodes necessary for these circuit elements are formed in advance, and the electrodes of the circuit elements on the lower surface are connected to the frame substrate 20 a by the face-down TAB method by using the bumps 23 at the time of packaging. Or the electrodes of the circuit elements on the lower surface are connected to the electrodes 26 of the frame substrate 20b by the lip-chip method using the bumps 25.

The connection with the circuit element on the upper surface is made by the bonding method using the electrode 27 of the frame substrate 20.
The electrodes 29 of the frame substrate 20a and the bumps 30 can connect the electrodes of the circuit elements to each other by the bonding wires 28 or the face-up TAB.

Next, with reference to FIGS. 3A to 3D, a description will be given of a method of manufacturing a semiconductor substrate having a silicon layer serving as a circuit element forming region on both surfaces of the substrate.

As shown in FIG. 3A, the double-side polished silicon semiconductor substrate 11 is placed in an oxygen atmosphere and the surface is thermally oxidized to form a silicon oxide film 16 having a thickness of 0.1 to 5 μm.
To form

Next, as shown in FIG. 3B, the surfaces to be bonded of the silicon substrate pieces 17 and 18 are mirror-polished and finished in a mirror shape, and are bonded to the silicon oxide film 12. Then, for example, heat treatment is performed at 1100 ° C. for 2 minutes to bond them.

Then, as shown in FIG. 3 (c), the bonded silicon substrate pieces 17, 18 are ground from the surface and removed to a certain thickness, and then, as shown in FIG. 3 (d). The surfaces are polished and removed to a predetermined thickness by using a CMP method or the like to form silicon layers 14 and 15 for forming circuit elements.

In the case of forming a circuit element in the element formation region of the semiconductor substrate of the present embodiment, the end face of the semiconductor substrate is gripped, and processing such as transfer, film formation and etching in a manufacturing apparatus is performed. It is desirable to do.

As described above, since the element formation regions are formed on both surfaces of the semiconductor substrate by the structure of the semiconductor substrate of the present embodiment, twice as many circuit elements are formed in the conventional chip area. be able to.

[0024]

As described above in detail, according to the present invention, it is possible to provide a semiconductor substrate which is suitable for large-scale integration and has circuit element formation regions on both sides while suppressing an increase in the size of the substrate. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor substrate according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of connecting circuit elements on the substrate of the embodiment.

FIG. 3 is a diagram illustrating an example of a manufacturing process for forming the present embodiment.

FIG. 4 is a diagram showing a cross-sectional structure of a conventional SOI substrate.

[Explanation of symbols]

 11 ... substrate (silicon semiconductor substrate) 12, 13 ... buried insulating layer 14, 15 ... silicon layer

Claims (4)

[Claims] A first buried insulating layer formed on both surfaces of a substrate made of silicon; and a circuit element formed on each of the first and second buried insulating layers. A first silicon layer serving as an element formation region for the semiconductor substrate. 2. First and second buried insulating layers are formed on both surfaces of a substrate made of silicon, and a first burying insulating layer is formed on the first and second buried insulating layers to form first and second circuit elements. SOI (Si) on which a second silicon layer is formed
A semiconductor substrate, which is a (icon-on-insulator) substrate. 3. The connection between circuit elements formed on the first and second silicon layers of the semiconductor substrate is performed by wiring penetrating the semiconductor substrate and electrically separated from the semiconductor substrate. The semiconductor substrate according to claim 1, wherein: 4. The connection between circuit elements formed on the first and second silicon layers of the semiconductor substrate is made using a bump or a bonding wire via a package substrate on which the semiconductor substrate is mounted. The semiconductor substrate according to claim 1, wherein: