JP2000214967A - Low-electric-power information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current when the processor is in operation by controlling the operation by the blocks of a circuit with an instruction signal. SOLUTION: An instruction decoder 102 inputs the instruction signal 101 and makes a decision according to information showing whether or not a circuit block 104 is used. According to the decision result of the instruction decoder 102, an operation mode for determining whether the leakage current of the circuit block 104 is large or small is indicated by using a signal 103. Namely, when the instruction indicated by the instruction signal 101 uses the circuit block 104, an operation mode wherein the leakage current is large is indicated and a circuit which does not decrease in speed is placed in operation; when the instruction indicated by the instruction signal 101 does not use the circuit block 104, an operation wherein the leakage current is small is indicated to reduce the leakage current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS integrated circuit.

[0002]

2. Description of the Related Art The prior arts known for the purpose of reducing the power of an information processing apparatus are: (1) ratioless in a CMOS design; (2) a sleep / standby state and a clock stop at that time. The item number 1 is that the CMOS gate does not consume anything other than the sub-threshold leakage current when the input is at the high level or the low level. In the present application, the term “leak current” refers to a sub-threshold leak current, that is, a steady leak current in a state where the input of the CMOS gate is determined to be at a high level or a low level. Therefore, by executing the items 1 and 2, the charge / discharge current and the through current of the CMOS circuit can be reduced in the sleep / standby state, but the leak current is not reduced.

[0003] A leak current is described in the September 1998 STARC Symposium Proceedings (Kyoto), pp. 100-109.

[0004] The leakage current is determined by the threshold voltage of the MOS transistor. There is a relationship that the smaller the threshold voltage of the MOS transistor is, the larger the leak current is. According to the document p.103, when the threshold voltage is 0.3 V and the leakage current is 5 mA in the case of a circuit of 1 million transistors and the temperature is 125 ° C., the leakage current is 0.1 mA when the threshold voltage is 0.1 V. The figure shows that the current has a large value of 1A. On the other hand, if the power supply voltage is Vcc and the threshold voltage is Vt, the drive current of the MOS transistor is (Vcc-V
Since it is known that the threshold voltage is proportional to the square of t), it is necessary to set the threshold voltage low when increasing the operation speed, and the leakage current increases.

A technique for reducing the leak current is disclosed in 1995.
June, IEICE Technical Report ICD95-41, pp.1-8. In the description, in order to reduce the leakage current during non-operation, a high threshold M
An OS transistor is provided as a power switch. In addition, the above STARC Symposium lecture proceedings
It is described that a MOS transistor having a high threshold value is used to shut off a circuit at the time of standby.

[0006] Also, IEEE JOURNAL OF SOLID-STATE CIRC
UITS, VOL.31, NO.11 (November 1996) requires controlling the substrate bias of a MOS transistor during standby to increase its threshold voltage and reduce leakage current during non-operation. Is described.

Japanese Patent Application Laid-Open No. 8-274620 discloses an LSI having a mode in which the threshold voltage of a MOS transistor is increased by controlling the substrate potential in order to reduce the leakage current of the CMOS and reduce the power consumption. It has been disclosed.

However, these documents do not disclose how to start and end the control of such a leak current, or interrupt control or mode control unrelated to the operation (instruction) executed by the circuit. It is done by. That is, a control system for controlling the power consumption of the circuit is provided separately from the control system for controlling the operation (calculation and the like) of the circuit.

On the other hand, another technique for lowering the power of a processor is disclosed in Japanese Patent Application Laid-Open No. 10-20959. In this known example, a power control field is provided in the instruction code, and the microprocessor decodes the power control field and operates only necessary functional blocks. However, it states that there are a method of controlling power supply and a method of controlling supply of a clock signal as power control methods.

However, no specific circuit for controlling power supply is shown, and no description is made of a steady-state leakage current flowing even when the input of the CMOS gate is set to a high level or a low level.

[0011]

A technique for reducing a leakage current during operation of a CMOS logic circuit in which a leakage current cannot be ignored, especially a processor, has not been known. Conventional literature for reducing leak current is limited to special states such as when the entire processor is not in use or in standby mode. Regarding mechanisms that automatically reduce leak current in connection with the arithmetic processing of the processor, Had not been considered.

An object of the present invention is to reduce leakage current during operation of a processor.

In particular, to increase the operation speed, the CM
When the threshold value of the OS is low, the reduction of the leak current has a significant meaning in reducing the power consumption. The circumstances are as shown in the above-mentioned STARC symposium proceedings.
This is because, when the temperature is 125 ° C. in a circuit with one million transistors, the leakage current has a large value of 1 A when the threshold value is 0.1 V. Today, LSI with high fineness
It is widely known that has a density of over one million transistors.

[0014]

In an information processing apparatus having a plurality of circuit blocks in which at least one circuit block is used by an instruction signal included in an instruction set, an instruction signal is decoded and the circuit block is decoded by the instruction signal. It is determined whether the circuit block is used or not.
When the voltage between the gate and the source of the MOS or NMOS is 0 V, the current flowing in the series-coupled source-drain path of the CMOS is allowed to flow, and a smaller leak current is provided for the unused circuit block. Restrict to

Particularly, in an information processing apparatus in which pipeline control is performed, a control signal for controlling a leak current is transmitted in synchronization with a pipeline stage. As a result, a large leak current is allowed to flow in the circuit block in the pipeline stage where the arithmetic processing is performed, and control is performed so as to limit the leak current to a small leak current when the pipeline stage ends.

Further, in this case, the leak current control is performed prior to the arithmetic processing of the circuit block, so that a transient state for the leak current control does not affect the arithmetic processing.

One example of a circuit block is an ALU (arithmetic logic unit). When an instruction using the ALU is executed, a mode in which the ALU has a large leak current is specified. When an instruction not using the ALU is executed, a mode in which the leak current of the ALU is small is specified. The determination circuit only needs to output an instruction signal regarding the magnitude of the leak current of the ALU based on the information on whether or not the instruction uses the ALU, which results in decoding the instruction.

Another example of a circuit block is an FPU (floating point arithmetic unit), which is used when an instruction signal executes an FPU instruction. Another example is a data memory, which is used only when the instruction signal includes a load operation (read from data memory) or a store operation (write to data memory).

As described above, the mode in which the leak current is large is applied when the circuit block requires operation, and the mode in which the leak current is small is applied when the circuit block does not require operation.
Reduce unnecessary leakage current.

[0020]

(Embodiment 1) FIG. 1 shows an embodiment using the present invention in the simplest form. 10
1 is a 16-bit instruction signal. 104 is one circuit block. Reference numeral 102 denotes an instruction decoder which receives the instruction signal 101 and makes a determination based on information on whether or not the circuit block 104 is used. Based on the determination result of the instruction decoder 102, an operation mode for determining the magnitude of the leakage current of the circuit block 104 is instructed using the signal 103. That is, when the instruction indicated by the instruction signal 101 uses the circuit block 104, the instruction indicating the operation mode in which the leakage current is large is performed, the circuit operates without speed reduction, and the instruction indicated by the instruction signal 101 is output from the circuit block 104. 10
When 4 is not used, an operation mode in which the leak current is small is instructed to reduce the leak current.

(Embodiment 2) FIG. 2 shows another embodiment, which has a plurality of circuit blocks. 201 is a 16-bit instruction signal. 208, 209 and 210 are three circuit blocks. 202, 203, and 204 receive the command signal 201 as input,
It is an instruction decoder that makes a determination based on the information on whether or not 09 and 210 are used. Circuit blocks 208, 209, 210
The signal instructing the operation mode for determining the magnitude of the leakage current is controlled based on the determination result signals 205, 206, 207 of the instruction decoders 202, 203, 204.

The control will be described for the circuit block 208. When the instruction indicated by the signal 201 uses the circuit block 208, an operation mode in which the leakage current is large is instructed to operate the circuit without speed reduction, and the instruction indicated by the instruction signal 201 does not use the circuit block 208. In such a case, an operation mode in which the leak current is small is instructed to reduce the leak current. Circuit blocks 209, 21
The same applies to 0. Circuit blocks 208, 20
Since the conditional expressions relating to the use / non-use of the elements 9 and 210 are generally different from each other, the instruction decoders 202, 203 and 204 are separately provided in order to instruct their different operation modes.
is necessary.

FIG. 3 is a table showing an instruction set employed by the circuit described in FIG. 2 and which of the circuit blocks the instruction uses. Reference numerals 301 to 311 indicate respective instructions in the instruction set. Column 312 is the name of the instruction. Here, for simplicity, instructions 1 (301) to 11
(311), one example is an addition instruction, one instruction is a load instruction, and 1
One instruction is a branch instruction.

The column 313 indicates that each instruction is in the circuit block 1 (20
8) is used. If Y is entered in the field,
Indicates use. When N is entered in the column, it indicates that it is not used. The circuit block 1 (208) is the instruction 1
And used by instruction 10. Similarly, column 314 indicates whether each instruction uses circuit block 2 (209). Row 3
Reference numeral 15 indicates whether each instruction uses the circuit block 3 (210).

FIG. 4 shows a configuration example of the instruction decoder 204. For example, as shown in FIG. 3, column 315, circuit block 2 (209) includes instructions 2, 5, 6, 7,
Used at 11. The decoder 204 has instructions 2, 5, 6,
7 and 11 are decoded, and 1 is output to the output signal 206. Reference numerals 401, 402, and 403 are inverters (logic inverters). Reference numeral 404 denotes a two-input OR (logical sum) gate. Reference numeral 405 denotes a three-input OR (logical sum) gate. 40
Reference numerals 6 and 407 denote three-input AND (logical product) gates. 4
08 is a 4-input AND (logical product) gate.

The operation of this circuit can be understood with the basic knowledge of combinatorial logic. Output 40 of gate 406
9 is 1 when the instruction signal [15:13] = 001, that is, decodes the instruction 2 (302). Gate 4 as well
The output 410 of 07 decodes the instruction 5-7 (305-307). Similarly, output 411 of gate 408 decodes instruction 11 (311).

The output 206 of the gate 405 is the signal 409,
By taking the logical sum of 410, 411, instructions 2, 5,
6, 7, and 11 are decoded. That is, the signal 206 becomes 1 when the command signal 201 is the command 2, 5, 6, 7, or 11.

(Embodiment 3) FIG. 5 shows another embodiment. In this embodiment, the processor uses a pipeline control method. The pipeline control method is characterized in that a computing unit is provided for each pipeline stage, and a timing latch is provided between the pipeline stages.

529-532 are pipeline stages
(The indication of the pipeline stage does not physically exist,
Which is described for explanation). 501 is an instruction signal. 502 and 503 are instruction decoders.
504, 506, 508, 513-518, 519, 5
21, 525-528 are timing latches. 50
5, 507 and 509 are circuit blocks, and the instruction decoder 502 determines whether or not they are used. 505,
507 and 509 are respectively pipeline stages 53
0, 531, and 532.
520 and 522 are circuit blocks, and the instruction decoder 5
03 is used to determine the use. 520, 52
Reference numeral 2 denotes hardware used in the pipeline stages 530 and 531, respectively.

The data controlled by the pipeline in the circuit block corresponding to the instruction decoder 502 is from 504 to 50.
5, 506, 507, 508, and 509. A circuit block corresponding to the instruction decoder 503,
Another data pipeline controlled is 519 to 52
0, 521, and 522. 510,5
11, 512, 523 and 524 are two-input OR (logical sum)
The gate.

FIG. 6 is a timing chart of the circuit shown in FIG. The horizontal axis indicates time. In a certain period (600), the instruction signal 501 indicates the operation A. The time length of the period 600 is one clock. At this time, the processor performs pipeline control, and uses the circuit block A1 (505) in the period 601.
(It is easy to understand that the operation 505 is performed). In the period 602, the circuit block A2 (507) is used. Period 60
3 uses the circuit block A3 (509). At this time, the use instruction signal output from the instruction decoder 502 is transmitted through the pipeline, and has the signal waveforms 513 to 518 in the drawing.
As a result, the circuit blocks A1 (505), A2 (506),
A3 (507) is supplied with a High signal for 1.5 clock times. The first 0.5 clock of the 1.5 clocks includes a time necessary as a transition state for transitioning the circuit block from the low leak state to the high leak state.

(Embodiment 4) FIG. 7 shows another embodiment using the present invention.
One embodiment is an example applied to a single instruction multiple data type processor. In this embodiment, four arithmetic units having a 32-bit width are provided in parallel. However, 0-4 of the arithmetic units are used, and the number used differs depending on the instruction.

The four 32-bit arithmetic units are 710-7.
Thirteen. 710, 711, 712, and 713 have bit numbers 127-96 and 95-6 for internal processing, respectively.
4, 63-32 and 31-0 are assigned.

In one instruction, a 128-bit operation is performed, and the operation of dest [127: 0] = src1 [127: 0] op src2 [127: 0] is performed. Here, src1 and src2 are input data of the operation, and dest indicates a place where the operation result is substituted.
[a: b] is a notation from bit numbers a to b. The op is a generalization of the operation. For example, in the case of addition, op may be replaced with “+”. In this case, all four arithmetic units 710-713 are used.

In another instruction, a 32-bit operation is performed, and the operation of dest [31: 0] = src1 [31: 0] op src2 [31: 0] is performed. In this case, computing unit 713 is used, but computing units 710-712 are not used.

701 is a command signal. 702-705
Is an instruction decoder. Instruction decoders 702 to 705 decode whether or not arithmetic units 710 to 711 are used for each instruction. When used, four control signal lines 706-70 are connected to arithmetic units 710-713.
9 to issue an instruction for an operation mode in the low leak state.

The means for controlling the leak current for each circuit block will be described below with reference to a specific example at the circuit diagram level.
explain.

FIG. 8 shows an example of the leak current control means. Reference numerals 801 to 803 denote PMOSs. 804-806
Is an NMOS. Here, PMOS 802 and NMOS 8
The set of 04 or the set of PMOS 803 and NMOS 805 forms a CMOS inverter. These two inverters are described as representatives of the internal circuit of the circuit block for explanation. A node 809 (local positive power supply line) to which the source terminals of the PMOSs 802 and 803 are connected is connected to a positive power supply via the PMOS 801. A node 810 (local ground line) to which the source terminals of the NMOSs 804 and 805 are connected is NM
It is connected to ground via OS 806. The substrate potential of the PMOS transistors 802 and 803 is connected to the local positive power supply line 809 by the NMOS transistor 8.
04, 805 is a local ground line 81
Connected to 0. MOS transistors 801 and 80
6 functions as a switch MOS transistor. Of course, even if only one of the MOS transistors 801 and 806 is provided, it can function as a switch MOS transistor.

The threshold voltage Vtp of the PMOS 801 is PM
It is higher by 1 V than the threshold voltage of the OSs 802 and 803 (that is, hardly leaks). The threshold voltage Vtn of the NMOS 806
Is 1 V higher than the threshold voltages of the NMOSs 804 and 805 (that is, hardly leaks). When there is no difference between the threshold values, even if the switch MOS transistors 801 and 806 are turned off, the switch MOS transistor 80
1, 806 itself does not have a smaller leak current than the internal circuit leak current, so there is no power reduction effect.

In order to reduce the leak current, a control signal 808 instructs to reduce the leak current. In this example, Lo
w is a low leak instruction, and High is a high leak instruction. The control signal 808 controls the gate of the NMOS 806, and its logical inversion signal (the output of the inverter 807) is
The gate of 801 is controlled. Therefore, when the control signal 808 is L
In the case of ow, the MOS transistor 8 which does not easily leak
Since 01,806 has low leakage (stronger off state), leakage current can be reduced.

FIG. 9 shows another example of the leak current control means. 901-910 of FIG. 9 are respectively 801-910 of FIG.
The description is omitted because it is the same as 810. 8 is that the substrate potentials of the PMOSs 902 and 903 are connected to the true positive power supply line 912 instead of the local positive power supply line 909, and the substrate potentials of the NMOSs 904 and 905 are local ground lines. 910, and is connected to a true ground line 913.

In this structure, the local positive power supply line 909 and the local ground line 9 are set in a mode in which the switch MOS transistors 901 and 906 are turned off.
10 causes a power supply drop between the true positive power supply line 912 and the true ground line 913, respectively, so that the substrate potential bias effect is generated and the effect of reducing the leak current is also obtained by the internal inverter itself. There is an advantage that it can be.

FIG. 10 shows still another example of the leak current control means. The substrate potentials of the PMOSs 1001 and 1002 are controlled by a PMOS substrate bias generation circuit 1005. Similarly, the substrate potentials of the NMOSs 1003 and 1004 are controlled by an NMOS substrate bias generation circuit 1006. It is the same as FIG. 8 that two internal inverters are described as representatives of the internal circuit of the circuit block.
The higher the substrate potential of the PMOS, the smaller the leakage current. N
The lower the substrate potential of the MOS, the smaller the leak current. For example, in an operation mode in which the leakage current is large, a PMOS transistor is used.
The substrate potential is a positive power supply potential, and the NMOS substrate potential is a ground power supply potential.
The OS substrate potential is a positive power supply potential +1.0 V, and the NMOS substrate potential is a ground power supply potential -1.0 V.

Further, SOI may be used for the substrate. By adopting the SOI structure, the capacity of the depletion layer below the gate is reduced, the tailing coefficient (reciprocal of the slope of the Vgs-logIds characteristic) is reduced, and the subthreshold current can be further reduced.

[0045]

As described above, according to the present invention, the operation can be controlled by the instruction signal for each circuit block, and the leakage current during the operation of the processor can be reduced. In particular, when the threshold value of the CMOS is low in order to increase the operation speed, the reduction of the leak current has a great significance in reducing the power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment having one circuit block.

FIG. 2 is a block diagram of an embodiment having three circuit blocks.

FIG. 3 is an instruction set table in the example shown in FIG. 2;

FIG. 4 is a logic circuit diagram of the instruction decoder 203 in the example shown in FIG.

FIG. 5 is a block diagram of an embodiment in which the present invention is applied to a pipeline type processor.

6 is a timing chart when one instruction in the example shown in FIG. 5 is executed.

FIG. 7 is a block diagram of an embodiment in which the present invention is applied to a single instruction multiple data type processor.

FIG. 8 is a circuit diagram of a leakage current control unit.

FIG. 9 is a circuit diagram of a leakage current control unit.

FIG. 10 is a circuit diagram of a leakage current control unit.

[Explanation of symbols]

101-command signal, 102-determination circuit, 103-signal indicating operation mode of circuit block, 104-circuit block, 201-command signal, 202, 203, 204-determination circuit, 205, 206, 207-circuit block Signals indicating operation mode, 208, 209, 210-circuit block, 301-311-instruction, 312-instruction name, 313-information indicating whether or not circuit block 1 (208) is used, 314-circuit block 2 (209) ), Information indicating whether or not the circuit block 3 (210) is used, 401, 402, 403-inverter, 404-2 input OR gate, 405-3 input OR gate, 406, 407-3. Input AND gate, 408-4 input AND gate, output signal of 409-406, 410-4
07 output signal, 411-408 output signal, 501-
Instruction signal, 502, 503-instruction decoder, 504-5
08, 513 to 519, 521, 525 to 528-timing latch, 505, 507, 509, 520, 52
2-Circuit block, 510-512, 523, 524-
2-input OR gate, period of 600 to 605-1 clocks, 606-clock signal, 701-command signal, 702
705-determination circuit, 706-709-signals indicating the operation mode of the circuit block, 710-713-circuit block, 801-803-PMOS transistor, 804
806-NMOS transistor, 807-inverter, 808-signal indicating operation mode of circuit block, 809-local positive power supply, 810-local ground, 811-internal circuit, 901-903-PMOS transistor, 904-906-NMOS Transistors,
907—inverter, 908—signal indicating operation mode of circuit block, 909—local positive power supply, 910—
Local ground, 911-internal circuit, 1001, 1
002-PMOS transistor, 1003, 1004-
NMOS transistor, 1005-substrate potential generator of PMOS transistor, 1006-substrate potential generator of NMOS transistor.

Claims (15)

[Claims] 1. A plurality of circuit blocks selectively used by an instruction signal included in an instruction set, and a circuit block provided corresponding to each of the plurality of circuit blocks, decoding the instruction signal and corresponding to the instruction block And a plurality of determination circuits for determining whether or not is used in the command signal, wherein the plurality of circuit blocks include a first P-channel MOSFET serially connected between a first potential and a second potential; First
A complementary MOSFET comprising an N-channel MOSFET, wherein the circuit block is in a first operating state when used in the command signal, and in a second operating state when not used in the command signal; In one operation state, the first P-channel MOS
When the gate-source voltage of the FET or the first N-channel MOSFET is 0 V, the complementary MOS
A first current flows through a series-connected source / drain path of the FET, and in the second operating state, the first P-channel MOS
When the gate-source voltage of the FET or the first N-channel MOSFET is 0 V, the complementary MOS
An information processing apparatus, wherein a second current smaller than the first current flows through a source-drain path of a FET connected in series. 2. The information processing apparatus according to claim 1, wherein a first substrate potential generating circuit for generating a substrate potential of said first P-channel MOSFET, and a second substrate potential generating circuit for generating a substrate potential of said first N-channel MOSFET. A circuit, wherein in the first operating state, the first potential is applied to the substrate of the first P-channel MOSFET, and the second potential is applied to the substrate of the first N-channel MOSFET; In the second operation state, the first P-channel MOS
A potential higher than the first potential generated by the first substrate potential generating circuit is applied to the FET substrate, and the first N
An information processing apparatus, wherein a potential lower than the second potential generated by the second substrate potential generating circuit is applied to a substrate of a channel MOSFET. 3. The information processing apparatus according to claim 1, wherein the plurality of circuit blocks have a source / drain path between the first potential and a third potential higher than the first potential. Second P-channel MOSF having a threshold voltage higher than the threshold voltage of 1P-channel MOSFET
ET, wherein the second P-channel MOSFET is in an on state in the first operation state, and the second
An information processing apparatus, wherein the second P-channel MOSFET is in an off state in an operation state. 4. The information processing device according to claim 3, wherein said third P-channel MOSFET has a third substrate potential.
An information processing device to which a potential is applied. 5. The information processing apparatus according to claim 1, wherein the plurality of circuit blocks have a source / drain path between the second potential and a fourth potential lower than the second potential. Second N-channel MOSF having a threshold voltage higher than the threshold voltage of 1N-channel MOSFET
ET, wherein the circuit block has the second N-channel MOSFET in an on state in the first operation state;
An information processing apparatus, wherein the second N-channel MOSFET is off in an operating state. 6. An information processing apparatus according to claim 5, wherein said fourth N-channel MOSFET has a substrate potential of said fourth N-channel MOSFET.
An information processing device to which a potential is applied. 7. The information processing apparatus according to claim 1, wherein each of the plurality of circuit blocks is an arithmetic unit having a predetermined bit width, and wherein the determination circuit is configured to perform an operation based on information on the arithmetic bit width included in the instruction signal. An information processing apparatus for determining whether a corresponding circuit block is used in the instruction signal. 8. A circuit block controlled to a first operation mode or a second operation mode in accordance with an instruction signal included in an instruction set; and a control for decoding the instruction signal and indicating an operation mode of the circuit block. A control circuit for outputting a signal, wherein the circuit block includes a complementary MOSFET consisting of a first P-channel MOSFET and a first N-channel MOSFET connected in series between a first potential and a second potential. In one operation mode, the first P-channel MO
When the gate-source voltage of the SFET or the first N-channel MOSFET is 0 V, the complementary MO
The first is connected to the series-connected source-drain path of the SFET.
Current flows, and in the second operation mode, the first P-channel MO
When the gate-source voltage of the SFET or the first N-channel MOSFET is 0 V, the complementary MO
An information processing apparatus, wherein a second current smaller than the first current flows through a source-drain path connected in series with an SFET. 9. A semiconductor device comprising: a plurality of circuit blocks used by an instruction signal included in an instruction set; and an instruction decoder for decoding the instruction signal and outputting a control signal instructing use of the plurality of circuit blocks. Each of the plurality of circuit blocks is used in a predetermined pipeline stage, the control signal is transmitted in synchronization with the pipeline stage, and the plurality of circuit blocks are connected between a first potential and a second potential. A first P-channel MOSFET and a first
The circuit block includes a complementary MOSFET composed of an N-channel MOSFET.
In the operating state, the second operating state is set according to the end of use of the circuit block. In the first operating state, the first P-channel MOS
When the gate-source voltage of the FET or the first N-channel MOSFET is 0 V, the complementary MOS
A first current flows through a series-connected source / drain path of the FET, and in the second operating state, the first P-channel MOS
When the gate-source voltage of the FET or the first N-channel MOSFET is 0 V, the complementary MOS
An information processing apparatus, wherein a second current smaller than the first current flows through a source-drain path of a FET connected in series. 10. The information processing apparatus according to claim 9, wherein the control signal is transmitted prior to the start of use of the circuit block, and a period from the transmission of the control signal to the start of use of the circuit block is: An information processing apparatus including a period in which the circuit block transitions from the second operation state to the first operation state. 11. The information processing apparatus according to claim 9, wherein a first substrate potential generating circuit for generating a substrate potential of said first P-channel MOSFET, and a second substrate potential generating circuit for generating a substrate potential of said first N-channel MOSFET. A circuit, wherein in the first operating state, the first potential is applied to the substrate of the first P-channel MOSFET, and the second potential is applied to the substrate of the first N-channel MOSFET; In the second operation state, the first P-channel MOS
A potential higher than the first potential generated by the first substrate potential generating circuit is applied to the FET substrate, and the first N
An information processing apparatus, wherein a potential lower than the second potential generated by the second substrate potential generating circuit is applied to a substrate of a channel MOSFET. 12. The information processing apparatus according to claim 9, wherein said plurality of circuit blocks have a source / drain path between said first potential and a third potential higher than said first potential. Second P-channel MOSF having a threshold voltage higher than the threshold voltage of 1P-channel MOSFET
ET, wherein the second P-channel MOSFET is in an on state in the first operation state, and the second
An information processing apparatus, wherein the second P-channel MOSFET is in an off state in an operation state. 13. An information processing apparatus according to claim 12, wherein said third P-channel MOSFET has a substrate potential of said third P-channel MOSFET.
An information processing device to which a potential is applied. 14. The information processing device according to claim 9, wherein said plurality of circuit blocks have a source / drain path between said second potential and a fourth potential lower than said second potential. Second N-channel MOSF having a threshold voltage higher than the threshold voltage of 1N-channel MOSFET
ET, wherein the circuit block has the second N-channel MOSFET in an on state in the first operation state;
An information processing apparatus, wherein the second N-channel MOSFET is off in an operating state. 15. An information processing apparatus according to claim 14, wherein said fourth potential is set to a substrate potential of said first N-channel MOSFET.
An information processing device to which a potential is applied.