JP2000209585A - Image encoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To combine data and output the combined data without the need for notice of the coded data amount generated from each encoding circuit and without the need for comparison between the coded data amount and the read data amount. SOLUTION: Encoding circuits 104-109 add a division area final code denoting the end of an area to coded data 124-129 of a final block of a coded unit block in each area. Furthermore, coded data of the coded unit block in the final area of one picture receive a picture boundary code denoting a boundary with a picture signal of a succeeding picture. Read control circuits 116-121 detect the division area final code to discriminate and output the final processing block of each area. Furthermore, a block combining circuit 122 detects the picture boundary code to discriminate a boundary of the succeeding picture and to combine and output the image signals for one picture.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image code for parallel processing using a high-efficiency coding technique for dividing an image signal into a plurality of regions and encoding the image signals divided into the respective regions simultaneously and in parallel. The present invention relates to a gasifier.

[0002]

2. Description of the Related Art In the field of digital transmission of moving images, MPs used in digital broadcasting
EG2 (Moving Picture Experts
2. Description of the Related Art An image coding apparatus using a high-efficiency coding technique based on motion compensation prediction represented by Group Phase 2) has been realized. They employ a parallel processing method using a plurality of encoding circuits in order to process a large amount of image data at high speed.

FIG. 8 is a schematic block diagram of an image parallel encoding apparatus using a plurality of encoding circuits using a conventional high-efficiency encoding technique disclosed in, for example, Japanese Patent Application Laid-Open No. 7-95572. The conventional parallel encoding device shown in FIG. 8 converts an analog-to-digital (hereinafter, referred to as A / D) conversion circuit 804 for converting an analog signal into a digital signal into n (one field or one frame) image signals. here,
It is assumed to be six for convenience. ), A plurality of encoding circuits 808 to 818 for performing variable length encoding using motion compensation of an image signal, and buffer memories 820 to 8 for temporarily storing data.
30, a read control circuit 832 for controlling the reading of data from the buffer memories 820 to 830, detecting the amount of data stored in the buffer memories 820 to 830,
A data amount calculation circuit 834 for calculating the sum, an encoding parameter control circuit 838 for controlling the amount of data generated by the encoding circuits 808 to 818, the image signal of one field or one frame is divided into m blocks. It comprises a 1 / m reference signal generation circuit 842 for generating a 1 / m time unit reference signal for division, and a block synthesis circuit 846 for synthesizing the n divided blocks. 808 to 818, buffer memory 8
20 to 830 operate in parallel.

Next, the operation will be described. The analog image signal input to the input terminal 802 is converted into a digital signal by the A / D conversion circuit 804. The digitized image signal is divided by a block dividing circuit 806 into n blocks per field or per frame.
The divided blocks are supplied to n encoding circuits 808 to 818 provided corresponding to the respective blocks.

[0005] Coded data 850 to 860 encoded by the encoding circuits 808 to 818 are written to buffer memories 820 to 830, respectively.

The buffer memories 820 to 830 temporarily store encoded data 850 to 860 generated at irregular rates from the encoding circuits 808 to 818, and sequentially control them at a constant data rate by the address control of the read control circuit 832. Read data.

The data read from each of the buffer memories 820 to 830 is supplied to a block synthesizing circuit 846.
The areas divided into n blocks are combined and output from the output terminal 848.

[0008]

However, in the above-described conventional image coding apparatus, each of the coding circuits 808 to 818 is used.
When the coded data 850 to 860 generated from are synthesized by the block synthesis circuit 846, the coded data 850 to 860
60 is generated at an irregular rate, the coded data amount is notified in advance to the read control circuit 832 or the block synthesizing circuit 846, and the read control circuit 832 controls the address so that the data is sequentially transmitted at a constant data rate. And at the same time, it is necessary to judge the end of reading of each encoded data while always comparing each encoded data amount with the read data amount.

In order to determine the end of block synthesis in the block synthesis circuit 846, each encoded data 8
It is necessary to determine that all of the data 50 to 860 have been read by comparing each encoded data amount with the read data amount.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has been made in consideration of the problems that occur when combining encoded data generated from each encoding circuit to form encoded data of one image. It is an object of the present invention to provide an image encoding apparatus which does not need to notify the encoded data amount and does not need to compare the encoded data amount with the read data amount when each encoded data is read.

Further, according to the present invention, when the coded data generated from each coding circuit are combined to form coded data for one image, the coded data amount is determined in order to determine that the structure has been completed. It is an object of the present invention to provide an image encoding device that does not need to compare the read data amount.

[0012]

In order to achieve the above object, according to the present invention, there are provided a plurality of encoding apparatuses for dividing an image signal into a plurality of regions and encoding the image signals divided into the respective regions simultaneously in parallel. An image encoding device having means, wherein the plurality of encoding means are respectively provided for each of the regions, and the image signals divided for each of the regions are simultaneously and in parallel for each predetermined coding unit. The encoding is performed, and the final code of the divided area is added to the image signal of the final encoding unit for each area.

[0013] In the next invention, the image signal encoded by the plurality of encoding means is input, and the divided area final code added to the image signal of the final encoding unit for each area. Is detected, and when the final code of the divided area of each area is detected, the image processing apparatus includes a synthesizing unit that synthesizes each image signal encoded for each area.

Further, in the following invention, there is provided an image encoding apparatus having a plurality of encoding means for dividing an image signal into a plurality of regions and encoding the image signals divided into the respective regions simultaneously in parallel. Encoding means for encoding an image signal of a final area of the plurality of encoding means, the image signal of the final encoding unit in the final area includes an image boundary code indicating a boundary with the next image. It is characterized by being added.

Further, in the next invention, the image signals encoded by the plurality of encoding means are input and synthesized, and the image added to the image signal of the final encoding unit in the final area is further added. When the boundary code is detected and the image boundary code is detected, the synthesized image signal is output.

Further, in the following invention, the image signal is divided into a plurality of regions based on the object, and the plurality of encoding means respectively convert the image signal divided for each region based on the object into a predetermined region. It is characterized in that coding is performed simultaneously and in parallel for each coding unit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram illustrating a schematic configuration of an image encoding device according to Embodiment 1 of the present invention. This image coding apparatus includes an A / D conversion circuit 102 for converting an analog signal into a digital signal,
An area dividing circuit 103 for dividing an image of one field or one frame into n (in the first embodiment, n = 6 for convenience of explanation), a variable-length code using motion compensation of an image signal Encoding circuits 104 to 10 for performing encoding
9. Buffer memories 110 to 115 for temporarily storing the encoded data generated from the encoding circuits 104 to 109, and read control circuits 116 to 12 for reading the encoded data temporarily stored in the buffer memories 110 to 115.
1, a block synthesis circuit 122 for synthesizing encoded data read by the read control circuits 116 to 121, and the encoding circuits 104 to 109, the buffer memories 110 to 115, and the read control circuits 116 to 121 are respectively arranged in parallel. It is configured to work.

In the actual encoding process, other components are required, but they are not related to the gist of the present invention, so that the description is omitted. Further, the internal configuration of the encoding circuits 104 to 109 may be regarded as being equivalent to, for example, an encoding circuit that realizes a well-known motion compensation encoding process.

Next, the operation of the image coding apparatus according to the first embodiment will be described. An analog image signal input from the input terminal 101 in a frame unit or a field unit is A / A
The signal is converted into a digital signal by the D conversion circuit 102. The digitized image signal is input to an area dividing circuit 103, and the area dividing circuit 103 outputs 1
The image signal is divided into n (= 6) areas of area 0 to area n-1 (= 5) for each image signal of a frame unit or a field unit, and each of the n divided areas is further encoded. The blocks are divided into m blocks for each predetermined coding unit in the circuits 104 to 109, and input to the corresponding coding circuits 104 to 109 for each of n regions.

Each of the encoding circuits 104 to 109 receives a digital image signal divided into m blocks for each of n regions, and uses the divided blocks as a predetermined encoding processing unit. Coding is performed simultaneously and parallel independently of each other.

At this time, each of the encoding circuits 104 to 109
As shown in FIG. 2, a code indicating the end of the area (hereinafter, referred to as a divided area final code) is added to the encoded data 124m-1 to 129m-1 of the last block of each area divided into n. A code representing the final image data (hereinafter referred to as an image boundary code C2) is added to the encoded data 129m-1 of the final processing block of one image.

FIGS. 3A to 3C show an encoding circuit 104.
10 shows an example of the data structure of the encoded data of the last block of each area which is output by each of. (A) shows the coded data 124m-1 to 124m-1 to 12n of the last block of the area 0 to the area n-2 output by the coding circuits 104 to 108, respectively.
The data structure of 8m-1 is shown, and the divided area final code C1 is added to the encoded data 124m-1 to 128m-1 of each last block. (B) and (c) show the data structure of the encoded data 129m-1 of the last block of the area n-1 outputted by the encoding circuit 109. In the case of (b), the data is divided into encoded data. The area end code C1 and the image boundary code C2 are added. In the case of (c), the divided area end code C1 is omitted, and the read control circuit 121 detects the image boundary code C2. , The end of the divided area and the boundary of the image are simultaneously recognized. Therefore, in the case of the encoded data 129m-1 of the last block of the area n-1, the divided area final code C1
May be omitted.

Thereafter, each of the encoding circuits 104-1
09 is a buffer memory 110 having an irregular rate, i.e., independently of each other as in the case of encoding, using the encoded image signals as encoded data 124 to 129, respectively.
To 115. The buffer memories 110 to 11
It is assumed that the content of 5 is previously cleared to, for example, “0”.

Next, each of the read control circuits 116-121
Reads the encoded data 124 to 129 from the buffer memories 110 to 115 and outputs them to the block synthesis circuit 122, respectively.

FIG. 4 shows read control circuits 116 to 121.
1 shows an example of the read operation flow. First, each of the read control circuits 116 to 121 performs the asynchronous operation, that is, independently of each other, from the corresponding buffer memories 110 to 115 in step S <b> 401.
129 and the codes C1 and C2 added to the encoded data 124 to 129 are read out by a fixed amount, that is, for each block or code C1 or C2 of the encoding processing unit divided into m. The read encoded data 124 to 129 are temporarily stored in, for example, an internal buffer (not shown) of each of the read control circuits 116 to 121. It should be noted that the internal buffer is to be read with a data length that is long enough to determine the divided area final code C1 and the image boundary code C2.

Next, each of the read control circuits 116 to 121
In step S402, respectively, the data read into the internal buffer is compared with the previously stored divided area final code C1 to detect whether the read data is the divided area final code C1.

Here, when the read data is the divided area final code C1 (step S402 "Ye").
s "), the encoded data 12 of the last block in the area
Since 4m-1 to 129m-1 have already been read, the process proceeds to step S403, where the divided area final code detection flags 130 to 135 are set to, for example, a low state, and the process returns to step S401. Is read.

On the other hand, if the read data is not the divided area final code C1 (step S402 "N
o ″) Then, in order to detect whether or not it is the image boundary code C2, the process proceeds to step S404, where the data read into the internal buffer is compared with the image boundary code C2 stored in advance and read. In the first embodiment, since the image boundary code C2 is added only by the encoding circuit 109, the read control corresponding to the encoding circuit 109 is performed. Only the circuit 121 performs the processing of step S404 and the next step S405, and the other read control circuits 1
Reference numeral 21 denotes this step S404 and the next step S40.
The processing of step 5 may be omitted.

Here, when the read data is the image boundary code C2 (in this case, only in the case of the read control circuit 121 which may read the image boundary code C2) ("Yes" in step S404). "), The process proceeds to step S405, and the read control circuit 121
The image boundary code detection flag 141 is set to, for example, a Low state, and the above-described read processing ends. In the case of the first embodiment, as described above, only the encoding circuit 109 adds the image boundary code C2 and the read control circuit 1
Since only 21 detects the image boundary code C2, the image boundary code detection flags 136 to 140 other than the image boundary code detection flag 141 may be omitted.

On the other hand, if the read data is not the image boundary code C2 (step S404 "N
o '') Then, the process proceeds to step S406, where each of the read control circuits 116 to 121 checks the state of the divided area final code 130 to 135, respectively, and if it is set to the low state (step S406 “ Ye
s ''), since the last divided data of each area has been output to the block synthesizing circuit 122, the above-described read processing is terminated. Note that the read processing is terminated through the processing of step S406 only in the read operation. Control circuit 12
In the case of the read control circuit 121 other than 1 and the read control circuit 121, the processing ends at step S404 “Yes” and step S405 as described above, so that the determination processing of step S406 is unnecessary.

On the other hand, in the judgment of step S406,
When each of the read control circuits 116 to 121 checks the state of the divided area final codes 130 to 135, if the state is not set to the Low state (“No” in step S406), the process proceeds to step S407. Each of the read control circuits 116 to 121 respectively
The encoded data read into the internal buffer is output to the block synthesis circuit 122. In this case, since each of the read control circuits 116 to 121 has not finished reading the encoded data of each area, the process returns to step S401 and the above process is performed again.

As described above, the read control circuit 11
6 to 121 are the read encoded data 124 to 129
Is output to the block synthesis circuit 122, the divided area final code C1 and the image boundary code C2 are detected,
When the divided area final code C1 is detected, the divided area final code C1 is deleted from the encoded data, and the detection of the divided area final code C1 is performed by using the divided area final code detection flags 130-135. 122
On the other hand, if the image boundary code C2 is detected, the image boundary code C2 is deleted from the encoded data,
The detection of the image boundary code C2 is performed by using the image boundary code detection flags 136 to 141 and the block synthesis circuit 12
Notify 2.

In the first embodiment, the image boundary code detection flag C1, the divided area final code detection flag C2,
Then, the encoded data is read from the read control circuits 116 to 12.
1 to the block synthesizing circuit 122, respectively. However, as shown in the following FIG. 5, it is possible to output the data in an integrated data structure to support software processing and the like.

FIG. 5 shows read control circuits 116 to 121.
Shows an example of a data structure output from the block synthesis circuit 122 to the block synthesis circuit 122. In the figure, 501 is an image boundary code detection flag, 502 is a division area final code detection flag, 50
Reference numeral 3 denotes encoded data. Image boundary code detection flag 5
01 are image boundary code detection flags 136 to 136, respectively.
141, which is output from the read control circuits 116 to 121 to the block synthesis circuit 122. The divided area final code detection flags 502 are divided area final code detection flags 130 to 135, respectively.
16 to 121 are output to the block synthesis circuit 122. The encoded data 503 includes encoded data 124 to 12
9, the division area final code C1 and the image boundary code C2
From the read control circuits 116 to 121 and the block synthesis circuit 122
Is output to

Next, the operation of the block synthesis circuit 122 will be described. FIG. 6 shows an example of an operation flow of the block synthesis circuit 122. It is assumed that the block synthesis circuit 122 reads the encoded data in the order of the read control circuits 116 to 121. In step S601, N = 1 indicates that encoded data is read from the read control circuit 116. In step S602, the state of the image boundary code detection flag 136 output from the read control circuit N (read control circuit 116) to the block synthesizing circuit 122 is checked, and the flow advances to the next step S603.

In step S603, step S602
Of the image boundary code detection flag 136
Is not in the Low state (step S603 “N”).
o ″), the process proceeds to the next step S604, and the process proceeds to step S60.
2 and the same read control circuit N (read control circuit 11
The state of the divided area final code detection flag 130 output from 6) to the block synthesis circuit 122 is checked, and the process proceeds to the next step S605.

Since the encoded data 124 read by the read control circuit 116 is in the area 0, the read control circuit 116 does not output the low-level image boundary code detection flag 136. Step S604 of checking the divided area final code detection flag
Checks the image boundary code C2 in step S60.
In the case of the first embodiment, as shown in FIG. 3 (c), the processing before the second block 2 is omitted from the coded data 129m-1 of the last block of the area n-1. Alternatively, the division region final code detection flag 135 may be omitted.

In step S605, step S604
Is determined and the divided area final code detection flag 1
If 30 is in the Low state (step S606 “Y
es "), since it is determined in step S603 that the data is not the encoded data of the last block of the image, the process proceeds to the next step S606 to input the encoded data of the next divided area, and N is incremented. , The block synthesis circuit 122 prepares to read the encoded data from the next read control circuit 117.

Then, in the next step S607, N
Is the number n of parallel connections of the encoding circuits 104 to 109 (=
6) is monitored to see if N> n (=
6) If not (“No” in step S607), the process returns to the above-described step S602, and N> n
(= 6) (step S607 “Ye”).
s ″), the final reading of the encoded data from the read control circuit 121 ends, and the read control circuit 116
To read the encoded data of area 0 from
According to 608, a process of setting N = 1 is performed.

If it is determined in step S605 that the divided area final code detection flag 130 is not in the Low state, it is determined that the read control circuit 116 has not yet read all the encoded data in the area 0 from the buffer memory 110. Therefore, the process proceeds to step S609 to read the next encoded data from the read control circuit N (read control circuit 116), returns to step S602, and repeats the above processing.

If it is determined in step S603 that the image boundary code detection flag 136 is in the low state ("Yes" in step S603), the final read control circuit 1
21 means that all the encoded data in the area 5 has been read from the corresponding buffer memory 115,
Proceeding to 610, the block synthesis circuit 122 outputs encoded data for one image to the output terminal 123.

By the above processing, the output terminal 123
The encoded data for the image is output.

Next, the read operation will be specifically described focusing on a certain read control circuit.

For example, the operation of the read control circuit 116 for reading the coded image signal of the area 0 from the buffer memory 110 and the operation of the read control circuit 116 for reading the coded image signal of the area 1
Attention is paid to the operation of the read control circuit 117 for reading from the address “1”.

First, encoding of each area is started simultaneously,
Operating in parallel, the divided area final code detection flag 13
0, 131, image boundary code detection flags 136, 137
Is in a High state.

The read control circuit 116 reads the encoded data 124 from the buffer memory 110 and outputs the encoded data to the block synthesizing circuit 122 until the divided area final code C1 is detected. When the read control circuit 116 detects the divided area final code C1, it does not output the data of the divided area final code C1, changes the divided area final code detection flag 130 to a low state, and outputs the encoded data 1
The block synthesizing circuit 122 is notified that all the signals 42 have been output.

The block synthesizing circuit 122 detects that the divided area final code detection flag has changed from High to Low in the processing of step S604 in FIG. 6, and ends the input of the encoded data 142.

At this time, the block synthesizing circuit 122 detects the data amount of the encoded data 142 input to the block synthesizing circuit 122 and the read control circuit 11 by detecting the change of the divided area final code detection flag from High to Low.
6, the encoded data 142 of the area 0 is calculated without comparing the data amount read from the buffer memory 110 and the like.
Can be determined.

Next, since the image boundary code detection flag 136 from the read control circuit 116 remains in the High state and remains unchanged, the block synthesizing circuit 122 starts to input the encoded data 143 from the next read control circuit 117. I do.

Similarly, the block synthesizing circuit 122
In the process of step S604 in FIG.
17 is set to Hi in the divided area final code detection flag 131
When the change from gh to Low is detected, the input of the encoded data 143 of the area 1 ends.

Next, a read control circuit 121 for reading the coded image signal of the area n-1 from the buffer memory 115
Notice the behavior of. Note that, at the time of encoding in the encoding circuit 109, as shown in FIGS. 3B and 3C, the encoded data 129m-1 of the last block of the encoded data 129 includes not only the divided area final code C1 but also the encoded data 129m-1. (Only in the case of FIG. 3B), the image boundary code C2 is added.

The read control circuit 121 reads out the coded data 129 from the buffer memory 115, and when the coded data 129m-1 of the last block of the coded data 129 is read out, the image boundary 129 is obtained by the processing of step S404 in FIG. The code C2 is detected and the encoded data 147
At the same time, the image boundary code detection flag 141 is changed from High to L by the processing of step S405.
ow.

The block synthesizing circuit 122 determines the image boundary code detection flag 141 in step S602 in FIG.
Is changed from High to Low, it is determined that all the coded data divided into n as shown in FIG. 2 is input, and one frame of coded data is output from the output terminal 123. .

At this time, the block synthesizing circuit 122 does not calculate the total sum of the encoded data 142 to 147 input from the read control circuits 116 to 121, and detects that the image boundary code detection flag 141 has changed from High to Low. Only by detecting, it is possible to determine the end of encoding for one frame.

Therefore, according to the image coding apparatus of the first embodiment, the block synthesizing circuit 122 is used by the divided final area code C1 added to the final encoded data of each area.
Is the amount of input encoded data and the read control circuit 11
Since the final coded data from each area can be recognized without comparing the amount of coded data read out by 6 to 121, an image can be synthesized.

Further, since the image final code C2 is added to the encoded data of the last block in the final divided area, the block synthesizing circuit 122 calculates one image from the data amount of each encoded data. , It is possible to easily determine the boundary with the next image and output the image signal of one synthesized image without determining the end of reading the encoded data.

In the description of the first embodiment, the number n of area divisions for code parallelization has been described as 6. However, the present invention is not limited to this value. Can be taken.

The area dividing circuit 10 according to the first embodiment
In part 3, processing other than area division is performed in actual encoding, but is omitted in this specification.

In the first embodiment, when the area is divided, the image is divided in parallel with the horizontal direction. However, the division method is not limited to this. For example, the image may be divided vertically or divided horizontally. The method of further vertically dividing the set area and the case of dividing the area into an arbitrary shape do not exceed the scope of the present invention.

When the number of divisions n increases, it is not economical to configure an image encoding device with n encoding circuits, buffer memories, and read control circuits. In such a case, in the present invention, even with p (p is an integer of 2 or more that satisfies p <n) encoding circuits, buffer memories, and read control circuits, one encoding circuit, buffer memory, In addition, an image encoding device can be economically realized by causing the read control circuit to encode a maximum of (n 読 み 出 し p + 1) regions.

Embodiment 2 In the description of the image coding apparatus according to the first embodiment, as shown in FIG. 2, each region is divided in the horizontal direction in the input image signal in the unit of a field or the unit of a frame. In order to encode the input image signal for each object according to the MPEG-4 system, the area dividing circuit 103 divides the input image signal into areas according to the object, and each encoding circuit performs the input image processing for each area divided according to the object. The signal is matched. Therefore, the second embodiment differs from the first embodiment only in the method of dividing the region dividing circuit. Therefore, the method of dividing the region dividing circuit in the second embodiment will be described. still,
Otherwise, the configuration is the same as that of the image coding apparatus according to the first embodiment. Therefore, the description will be made with reference to the configuration of FIG. 1 showing the configuration of the first embodiment.

FIG. 7 shows a method of dividing the area dividing circuit according to the second embodiment. As shown in FIG. 7, there is an image in a frame unit or a field unit composed of two objects of a background A such as a person A and a mountain.
If each of the objects 04 to 109 performs encoding with its own encoding efficiency for each object of the background B such as the person A or the mountain according to MPEG-4, the region dividing circuit 103 extracts the edge of the person A or the mountain by extracting the edge or the like. The image signal of the divided area is output to the encoding circuit 104, for example, the image signal of the divided area is output to the encoding circuit 104, and the image signal of the divided area is output to the encoding circuit 104. The divided image signal is output to the encoding circuit 105.

Then, the encoding circuit 104 encodes the image signal of the object of the person A, which has been divided into regions, and at this time, as in the first embodiment, the divided final region code C
On the other hand, the encoding circuit 105 encodes an image signal of an object of the background B such as a mountain divided into regions,
At this time, the division final area code C1 and the image boundary code C2 are added as in the case of the first embodiment.

In this case, for example, since the person A has more movement than the background B such as a mountain, the degree of attention is higher, and the amount of encoded data is larger, the image signal of the object of the person A is encoded. The encoding circuit 104 includes a background B such as a mountain.
Coding circuit 10 for coding the image signal of the object
For example, prepare an encoding circuit with higher processing capacity than 5,
Of course, the processing capability may be changed between the encoding circuits.

Therefore, according to the image encoding apparatus of the second embodiment, the final coded data from each area is determined by the final divided area code C1 and the final image code C2 in the same manner as in the first embodiment. In addition, encoded data of one image can be easily recognized and synthesized.

In particular, in the second embodiment, the MPEG-
4 and the like, the region is divided for each object and the encoding is performed, so that the encoding processing capability, the encoding efficiency such as the compression ratio, and the encoding processing time may differ for each encoding circuit. , The final encoded data from each area and the encoded data of one image without checking the input amount, readout amount, etc. of the encoded data of each area by the divided final area code C1 and the image final code C2. Can be easily recognized and synthesized.

[0067]

As described above, according to the present invention,
Since the divided area final code C1 is added to each encoded data, an image can be synthesized using the data amount of the encoded data temporarily stored in the buffer memory without final determination of each encoded data. .

Since the image boundary code is added to the encoded data of the last block in the final area, the next image can be read without judging the end of reading the encoded data of one image from the data amount of each encoded data. Easily determine the boundary with
An image signal of one combined image can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image encoding device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating an example of division of an image signal on a screen by a region division circuit according to the first embodiment;

FIG. 3 is a diagram illustrating an example of a data structure of encoded data of a last block of each area output by the encoding circuit according to the first embodiment;

FIG. 4 is a flowchart illustrating an example of a read operation of the read control circuit according to the first embodiment;

FIG. 5 is a diagram illustrating an example of a data structure output from a read control circuit to a block synthesis circuit according to the first embodiment;

FIG. 6 is a flowchart illustrating an example of an operation of the block synthesis circuit according to the first embodiment;

FIG. 7 is a diagram illustrating an example of dividing an image signal on a screen by a region dividing circuit according to the second embodiment;

FIG. 8 is a block diagram of a conventional example.

[Explanation of symbols]

101 input terminal, 102 A / D conversion circuit, 103
Region dividing circuit, 104 to 109 encoding circuit, 110 to 110
115 buffer memory, 116 to 121 read control circuit, 122 block synthesis circuit, 123 output terminal, C1 divided area final code, C2 image boundary code.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shozo Kondo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term within Mitsubishi Electric Corporation (reference) 5B057 CA16 CB18 CG02 CG07 CH04 5C059 KK37 LA01 LC08 MA05 MB02 MB21 ME01 NN01 PP28 RB02 RC24 UA02 UA34 UA38

Claims (5)

[Claims] 1. An image encoding apparatus comprising: a plurality of encoding means for dividing an image signal into a plurality of regions and encoding the image signals divided into the respective regions simultaneously and in parallel; Encoding means are provided for each of the regions, respectively, and simultaneously code the image signals divided for each of the regions for each predetermined coding unit in parallel, and for each region, the final coding unit An image coding apparatus, wherein a final code of a divided area is added to an image signal. 2. An image signal encoded by the plurality of encoding means is input, and a divided area final code added to an image signal of a final encoding unit for each area is detected. 2. The image coding apparatus according to claim 1, further comprising a synthesizing means for synthesizing each of the image signals coded for each of the regions when the divided region final code of each of all the regions is detected. 3. An image encoding apparatus comprising: a plurality of encoding means for dividing an image signal into a plurality of regions and encoding the image signals divided into the regions simultaneously and in parallel; Encoding means for encoding an image signal in a final area of the encoding means, wherein an image boundary code indicating a boundary with a next image is added to an image signal of a final encoding unit in the final area. Image encoding device. 4. An image signal encoded by the plurality of encoding means is input and synthesized, and an image boundary code added to an image signal of a final encoding unit in a final area is detected. 4. The image encoding apparatus according to claim 3, wherein when the image boundary code is detected, the combined image signal is output. 5. An image signal is divided into a plurality of regions based on an object, and a plurality of encoding means respectively convert the image signals divided for each region based on the object into predetermined coding units. 5. The image coding apparatus according to claim 1, wherein coding is performed simultaneously and in parallel.