JP2000208883A - Electronic circuit unit - Google Patents

Electronic circuit unit

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Publication number
JP2000208883A
JP2000208883A JP11002682A JP268299A JP2000208883A JP 2000208883 A JP2000208883 A JP 2000208883A JP 11002682 A JP11002682 A JP 11002682A JP 268299 A JP268299 A JP 268299A JP 2000208883 A JP2000208883 A JP 2000208883A
Authority
JP
Japan
Prior art keywords
insulating substrate
pattern
electronic circuit
circuit unit
ground pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11002682A
Other languages
Japanese (ja)
Other versions
JP3772033B2 (en
Inventor
Takeshi Tanemura
武 種村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP00268299A priority Critical patent/JP3772033B2/en
Publication of JP2000208883A publication Critical patent/JP2000208883A/en
Application granted granted Critical
Publication of JP3772033B2 publication Critical patent/JP3772033B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce warping at the periphery of an insulating substrate by mounting an electric part on a circuit pattern provided on one surface of the insulating substrate while a grid-like ground pattern comprising a pattern removing part is formed on the entire of the other surface. SOLUTION: An electronic circuit unit 1 comprises an insulating substrate 2 where insulators are laminated in multiple layers, and electric parts 3 such as resistors, capacitors, and IC parts, etc., which are, connected to a circuit pattern provided on an upper surface 2a of the insulating substrate 2, mounted on the upper surface 2. Further, a resist 6 is provided which is formed on the upper surface of a ground pattern 5 formed in grid comprising many pattern removing parts 5a over almost entire of a lower surface 2c except for a side electrode 4 drawn out to the lower surface 2c through a side edge part 2b of the insulating substrate 2 while connected to the circuit pattern. The pattern removing part 5a is rectangular while the ground pattern 5 is grid-like.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、携帯電話機に使用
される送受信ユニット等の電子回路ユニットに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit unit such as a transmission / reception unit used for a portable telephone.

【0002】[0002]

【従来の技術】従来の電子回路ユニットを図5〜図7に
基づいて説明すると、図5は従来の電子回路ユニットを
マザー基板に取り付けた状態を示す側面図、図6は従来
の電子回路ユニットに係り、レジストを取り除いた状態
の下面図、図7は従来の電子回路ユニットの反りの状態
を示す説明図である。
2. Description of the Related Art A conventional electronic circuit unit will be described with reference to FIGS. 5 to 7. FIG. 5 is a side view showing a state in which the conventional electronic circuit unit is mounted on a mother board, and FIG. FIG. 7 is an explanatory view showing a warped state of a conventional electronic circuit unit with the resist removed.

【0003】そして、従来の電子回路ユニット21は、
図5〜図7に示すように、絶縁体が多層に積層されてな
る絶縁基板22と、この絶縁基板22の上面22aに設
けられた回路パターン(図示せず)に接続されて、上面
22aに搭載された抵抗、コンデンサ、IC部品等の電
気部品23と、回路パターンに接続された状態で、絶縁
基板22の側縁部22bを通して下面22cに引き出さ
れたサイド電極24と、サイド電極24を除いて下面2
2cの全面に、銅箔がベタ状に形成された接地パターン
25と、接地パターン25の上面に形成されたレジスト
26とで構成されている。
[0003] The conventional electronic circuit unit 21 comprises:
As shown in FIGS. 5 to 7, an insulating substrate 22 formed by laminating insulators in multiple layers and a circuit pattern (not shown) provided on the upper surface 22 a of the insulating substrate 22 are connected to the upper surface 22 a. Except for the mounted electrical components 23 such as resistors, capacitors, and IC components, the side electrodes 24 drawn out to the lower surface 22c through the side edges 22b of the insulating substrate 22 while being connected to the circuit pattern, and the side electrodes 24 are excluded. Lower surface 2
On the entire surface of 2c, a ground pattern 25 in which copper foil is formed in a solid shape and a resist 26 formed on the upper surface of the ground pattern 25 are formed.

【0004】そして、このような電子回路ユニット21
は、図5に示すように、マザー基板27上に載置され、
マザー基板27に設けた導電パターン(図示せず)にサ
イド電極24を半田28付けして取り付けられ、電子回
路ユニット21がマザー基板27に面実装されるように
なっている。このような電子回路ユニット21は、一般
に種々の試験が行われるが、マザー基板27に電子回路
ユニット21を面実装した状態で、温度サイクル試験を
行った結果、絶縁基板22の外周部の反りが大きく、マ
ザー基板27の導電パターンとサイド電極24との間の
半田28による接続が破壊して、接続不良が多く発生し
た。
Then, such an electronic circuit unit 21
Is placed on the motherboard 27 as shown in FIG.
A side electrode 24 is attached to a conductive pattern (not shown) provided on the motherboard 27 by soldering 28, and the electronic circuit unit 21 is surface-mounted on the motherboard 27. In general, various tests are performed on such an electronic circuit unit 21. As a result of performing a temperature cycle test in a state where the electronic circuit unit 21 is surface-mounted on the motherboard 27, warpage of the outer peripheral portion of the insulating substrate 22 is found. As a result, the connection between the conductive pattern of the mother board 27 and the side electrode 24 by the solder 28 was broken, and many connection failures occurred.

【0005】そこで、このような半田28の接続破壊を
分析した結果、図7に示すように、厚さが1mmの絶縁
基板22を使用した時、絶縁基板22の中央部を基準と
して、外周部で反りが発生し、その反りTが0.2mm
の大きさであった。
Therefore, as a result of analyzing the connection breakdown of the solder 28, as shown in FIG. 7, when the insulating substrate 22 having a thickness of 1 mm is used, the outer peripheral portion is determined with reference to the center of the insulating substrate 22. Warpage occurs, and the warp T is 0.2 mm
It was the size of.

【0006】[0006]

【発明が解決しようとする課題】従来の電子回路ユニッ
トは、絶縁基板22の下面22cのほぼ全面に、ベタ状
態で接地パターン25が設けられた構成であるため、側
縁部22bの周辺での反りが大きく、電子回路ユニット
21をマザー基板27に半田28付けした状態で、外部
環境下で使用した際、接続不良を多く発生するという問
題がある。
The conventional electronic circuit unit has a configuration in which the ground pattern 25 is provided in a substantially solid state on almost the entire lower surface 22c of the insulating substrate 22, so that the periphery of the side edge portion 22b is provided. When the electronic circuit unit 21 is used in an external environment in a state in which the electronic circuit unit 21 is soldered to the mother board 27 in a state where the electronic circuit unit 21 is soldered to the mother board 27, there is a problem that a large number of connection failures occur.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
の第1の解決手段として、絶縁基板の一方の面には、回
路パターンが設けられて、この回路パターンに電気部品
が接続されて搭載され、また、前記絶縁基板の他方の面
には、ほぼ全面に、パターン除去部を有する網目状の接
地パターンを形成した構成とした。また、第2の解決手
段として、前記接地パターンは、前記絶縁基板の外周部
における前記接地パターンの面積を、前記絶縁基板の中
央部における前記接地パターンの面積よりも少なくした
構成とした。また、第3の解決手段として、前記絶縁基
板の外周部における前記接地パターンの幅を、前記絶縁
基板の中央部における前記接地パターンの幅よりも狭い
幅で形成した構成とした。
As a first means for solving the above problems, a circuit pattern is provided on one surface of an insulating substrate, and electric components are connected to the circuit pattern and mounted. In addition, on the other surface of the insulating substrate, a mesh-like ground pattern having a pattern removing portion is formed on almost the entire surface. As a second solution, the ground pattern has a configuration in which an area of the ground pattern at an outer peripheral portion of the insulating substrate is smaller than an area of the ground pattern at a central portion of the insulating substrate. Further, as a third solution, the width of the ground pattern at the outer peripheral portion of the insulating substrate is formed to be smaller than the width of the ground pattern at the center of the insulating substrate.

【0008】[0008]

【発明の実施の形態】本発明の電子回路ユニットを図1
〜図4に基づいて説明すると、図1は本発明の電子回路
ユニットをマザー基板に取り付けた状態を示す側面図、
図2は本発明の電子回路ユニットの第1の実施例に係
り、レジストを取り除いた状態の下面図、図3は本発明
の電子回路ユニットの第2の実施例に係り、レジストを
取り除いた状態の下面図、図4は本発明の電子回路ユニ
ットの反りの状態を示す説明図である。
FIG. 1 shows an electronic circuit unit according to the present invention.
FIG. 1 is a side view showing a state where the electronic circuit unit of the present invention is mounted on a mother board,
FIG. 2 is a bottom view of the electronic circuit unit according to the first embodiment of the present invention with the resist removed, and FIG. 3 is a view of the second embodiment of the electronic circuit unit of the present invention with the resist removed. FIG. 4 is an explanatory view showing a warped state of the electronic circuit unit of the present invention.

【0009】そして、本発明の電子回路ユニット1の第
1の実施例は、図1、図2に示すように、絶縁体が多層
に積層されてなる絶縁基板2と、この絶縁基板2の上面
2aに設けられた回路パターン(図示せず)に接続され
て、上面2aに搭載された抵抗、コンデンサ、IC部品
等の電気部品3と、回路パターンに接続された状態で、
絶縁基板2の側縁部2bを通して下面2cに引き出され
たサイド電極4と、サイド電極4を除いて下面2cのほ
ぼ全面に、多数のパターン除去部5aを有する網目状に
形成された接地パターン5と、接地パターン5の上面に
形成されたレジスト6とで構成されている。
A first embodiment of an electronic circuit unit 1 according to the present invention, as shown in FIGS. 1 and 2, comprises an insulating substrate 2 in which insulators are laminated in multiple layers, and an upper surface of the insulating substrate 2. The electrical component 3 such as a resistor, a capacitor, and an IC component mounted on the upper surface 2a is connected to a circuit pattern (not shown) provided on the upper surface 2a.
A side electrode 4 drawn out to the lower surface 2c through the side edge 2b of the insulating substrate 2 and a ground pattern 5 formed in a mesh shape having a large number of pattern removing portions 5a on almost the entire lower surface 2c except for the side electrode 4. And a resist 6 formed on the upper surface of the ground pattern 5.

【0010】また、第1の実施例では、図2に示すよう
に、パターン除去部5aは、矩形状で形成されて、接地
パターン5が網目状となっており、この実施例では、パ
ターン除去部5aの幅A1を0.4mm、パターン除去
部5a間の幅A2を同じく0.4mmとして、整列され
たパターン除去部5aを備えた網目状の接地パターン5
を形成したものである。
In the first embodiment, as shown in FIG. 2, the pattern removing section 5a is formed in a rectangular shape, and the ground pattern 5 has a mesh shape. The width A1 of the portion 5a is 0.4 mm, the width A2 between the pattern removing portions 5a is also 0.4 mm, and the mesh-like ground pattern 5 having the aligned pattern removing portions 5a.
Is formed.

【0011】また、図3は本発明の第2の実施例を示
し、この実施例における接地パターン5は、絶縁基板2
の外周部における接地パターン5の面積を、絶縁基板2
の中央部における接地パターン5の面積よりも少なくし
たものである。そして、その具体的な構成の一例とし
て、図3に示すように、絶縁基板2の外周部におけるパ
ターン除去部5aの幅A3を0.6mm、パターン除去
部5a間の幅A4を0.2mmとし、また、絶縁基板2
の中央部におけるパターン除去部5aの幅A5を0.4
mm、パターン除去部5a間の幅A6を同じく0.4m
mとして、絶縁基板2の外周部における接地パターン5
の幅A4を、絶縁基板2の中央部における接地パターン
5の幅A6よりも狭く形成して、外周部における接地パ
ターン5の面積を、中央部における接地パターン5の面
積よりも少なくしたものである。
FIG. 3 shows a second embodiment of the present invention. In this embodiment, the ground pattern 5 is
The area of the ground pattern 5 in the outer peripheral portion of the
Is smaller than the area of the ground pattern 5 in the central portion of FIG. As an example of the specific configuration, as shown in FIG. 3, the width A3 of the pattern removing portion 5a at the outer peripheral portion of the insulating substrate 2 is 0.6 mm, and the width A4 between the pattern removing portions 5a is 0.2 mm. And the insulating substrate 2
The width A5 of the pattern removing portion 5a at the center of
mm, and the width A6 between the pattern removing portions 5a is also 0.4 m.
m, the ground pattern 5 on the outer peripheral portion of the insulating substrate 2
Is smaller than the width A6 of the ground pattern 5 at the center of the insulating substrate 2 so that the area of the ground pattern 5 at the outer periphery is smaller than the area of the ground pattern 5 at the center. .

【0012】そして、このような電子回路ユニット1
は、図1に示すように、マザー基板7上に載置され、マ
ザー基板7に設けた導電パターン(図示せず)にサイド
電極4を半田8付けして取り付けられ、電子回路ユニッ
ト1がマザー基板7に面実装されるようになっている。
このような電子回路ユニット1は、一般に種々の試験が
行われるが、マザー基板7に電子回路ユニット1を面実
装した状態で、温度サイクル試験を行った結果、絶縁基
板2の反りが小さく、マザー基板7の導電パターンとサ
イド電極4との間の半田8による破壊が少なく、接続不
良の発生を少なくできる結果を得た。
Then, such an electronic circuit unit 1
As shown in FIG. 1, the electronic circuit unit 1 is mounted on a mother board 7, and a side electrode 4 is attached to a conductive pattern (not shown) provided on the mother board 7 by soldering 8. It is designed to be surface-mounted on the substrate 7.
Generally, various tests are performed on such an electronic circuit unit 1. As a result of performing a temperature cycle test in a state where the electronic circuit unit 1 is surface-mounted on the mother board 7, the warpage of the insulating board 2 is small, As a result, there was little breakage due to the solder 8 between the conductive pattern of the substrate 7 and the side electrode 4 and the occurrence of poor connection was reduced.

【0013】そして、上記第1と第2の実施例における
絶縁基板2の反りを分析した結果、図4に示すように、
厚さが1mmの絶縁基板22を使用した時、第1の実施
例においては、絶縁基板2の中央部を基準として、外周
部で反りが発生するが、その反りt1が0.1mm、ま
た、第2の実施例においては、その反りt1が0.03
mmとなり、何れも従来に比して小さくできるものであ
った。
As a result of analyzing the warpage of the insulating substrate 2 in the first and second embodiments, as shown in FIG.
When the insulating substrate 22 having a thickness of 1 mm is used, in the first embodiment, a warp occurs at an outer peripheral portion with respect to a central portion of the insulating substrate 2, and the warp t1 is 0.1 mm. In the second embodiment, the warp t1 is 0.03
mm, which could be made smaller than before.

【0014】[0014]

【発明の効果】本発明の電子回路ユニットは、絶縁基板
2の下面2cにおいて、ほぼ全面に、パターン除去部5
aを有する網目状の接地パターン5を設けたもであるた
め、従来に比して、絶縁基板2の外周部における反りを
小さくでき、マザー基板7との半田8による接続不良を
少なくできる電子回路ユニットを提供できる。また、接
地パターン5は、絶縁基板5の外周部における接地パタ
ーン5の面積を、絶縁基板2の中央部における接地パタ
ーン5の面積よりも少なくすることにより、一層、絶縁
基板2の外周部における反りを小さくできて、接続不良
の極めて少ない電子回路ユニットを提供できる。また、
絶縁基板2の外周部における接地パターン5の幅を、絶
縁基板2の中央部における接地パターン5の幅よりも狭
い幅で形成することにより、一層、絶縁基板2の外周部
における反りを小さくできて、接続不良の極めて少ない
電子回路ユニットを提供できる。
According to the electronic circuit unit of the present invention, the pattern removing portion 5 is provided on almost the entire lower surface 2c of the insulating substrate 2.
Since the mesh-shaped ground pattern 5 having a is provided, the warpage in the outer peripheral portion of the insulating substrate 2 can be reduced as compared with the related art, and the connection failure due to the solder 8 with the mother substrate 7 can be reduced. Units can be provided. Further, the ground pattern 5 is formed such that the area of the ground pattern 5 at the outer peripheral portion of the insulating substrate 5 is smaller than the area of the ground pattern 5 at the central portion of the insulating substrate 2, thereby further warping the outer peripheral portion of the insulating substrate 2. Can be reduced, and an electronic circuit unit with extremely few connection failures can be provided. Also,
By forming the width of the ground pattern 5 at the outer peripheral portion of the insulating substrate 2 to be smaller than the width of the ground pattern 5 at the central portion of the insulating substrate 2, warpage at the outer peripheral portion of the insulating substrate 2 can be further reduced. Thus, an electronic circuit unit with extremely few connection failures can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子回路ユニットをマザー基板に取り
付けた状態を示す側面図。
FIG. 1 is a side view showing a state where an electronic circuit unit of the present invention is mounted on a mother board.

【図2】本発明の電子回路ユニットの第1の実施例に係
り、レジストを取り除いた状態の下面図。
FIG. 2 is a bottom view of the electronic circuit unit according to the first embodiment of the present invention, with a resist removed.

【図3】本発明の電子回路ユニットの第2の実施例に係
り、レジストを取り除いた状態の下面図。
FIG. 3 is a bottom view of a second embodiment of the electronic circuit unit according to the present invention, with a resist removed.

【図4】本発明の電子回路ユニットの反りの状態を示す
説明図。
FIG. 4 is an explanatory diagram showing a warped state of the electronic circuit unit of the present invention.

【図5】従来の電子回路ユニットをマザー基板に取り付
けた状態を示す側面図。
FIG. 5 is a side view showing a state in which a conventional electronic circuit unit is mounted on a mother board.

【図6】従来の電子回路ユニットに係り、レジストを取
り除いた状態の下面図。
FIG. 6 is a bottom view of a conventional electronic circuit unit with a resist removed.

【図7】従来の電子回路ユニットの反りの状態を示す説
明図。
FIG. 7 is an explanatory view showing a warped state of a conventional electronic circuit unit.

【符号の説明】[Explanation of symbols]

1 電子回路ユニット 2 絶縁基板 2a 上面 2b 側縁部 2c 下面 3 電気部品 4 サイド電極 5 接地パターン 5a パターン除去部 6 レジスト 7 マザー基板 8 半田 A1 幅 A2 幅 A3 幅 A4 幅 A5 幅 A6 幅 Reference Signs List 1 electronic circuit unit 2 insulating substrate 2a upper surface 2b side edge 2c lower surface 3 electric component 4 side electrode 5 ground pattern 5a pattern removing portion 6 resist 7 mother substrate 8 solder A1 width A2 width A3 width A4 width A5 width A6 width

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板の一方の面には、回路パターン
が設けられて、この回路パターンに電気部品が接続され
て搭載され、また、前記絶縁基板の他方の面には、ほぼ
全面に、パターン除去部を有する網目状の接地パターン
を形成したことを特徴とする電子回路ユニット。
1. A circuit pattern is provided on one surface of an insulating substrate, and an electric component is connected to and mounted on the circuit pattern. An electronic circuit unit, wherein a mesh-like ground pattern having a pattern removing portion is formed.
【請求項2】 前記接地パターンは、前記絶縁基板の外
周部における前記接地パターンの面積を、前記絶縁基板
の中央部における前記接地パターンの面積よりも少なく
したことを特徴とする請求項1記載の電子回路ユニッ
ト。
2. The ground pattern according to claim 1, wherein an area of the ground pattern in an outer peripheral portion of the insulating substrate is smaller than an area of the ground pattern in a central portion of the insulating substrate. Electronic circuit unit.
【請求項3】 前記絶縁基板の外周部における前記接地
パターンの幅を、前記絶縁基板の中央部における前記接
地パターンの幅よりも狭い幅で形成したことを特徴とす
る請求項2記載の電子回路ユニット。
3. The electronic circuit according to claim 2, wherein a width of the ground pattern at an outer peripheral portion of the insulating substrate is smaller than a width of the ground pattern at a central portion of the insulating substrate. unit.
JP00268299A 1999-01-08 1999-01-08 Electronic circuit unit Expired - Fee Related JP3772033B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP00268299A JP3772033B2 (en) 1999-01-08 1999-01-08 Electronic circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00268299A JP3772033B2 (en) 1999-01-08 1999-01-08 Electronic circuit unit

Publications (2)

Publication Number Publication Date
JP2000208883A true JP2000208883A (en) 2000-07-28
JP3772033B2 JP3772033B2 (en) 2006-05-10

Family

ID=11536077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00268299A Expired - Fee Related JP3772033B2 (en) 1999-01-08 1999-01-08 Electronic circuit unit

Country Status (1)

Country Link
JP (1) JP3772033B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009290606A (en) * 2008-05-29 2009-12-10 Kyocera Corp Branching filter and wireless communication device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009290606A (en) * 2008-05-29 2009-12-10 Kyocera Corp Branching filter and wireless communication device

Also Published As

Publication number Publication date
JP3772033B2 (en) 2006-05-10

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