JP2000208724A - Storage element, its drive method and storage device, and image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write and delete data in a short time and accurately. SOLUTION: A transparent electrode 10a is formed as the bottom electrode of a double gate memory 11 on a glass substrate 10. A bottom insulation film 11a is formed thereon, and a semiconductor layer 11b made of a-Si is formed corresponding to the position of the bottom electrode. A source electrode 11d and a drain electrode 11e are formed on both sides of the semiconductor layer 11b via an n+Si layer 11c. Furthermore, a top gate insulation film 11f and a top gate electrode 11g are formed sequentially thereon. Both the bottom gate insulation film 11a and top gate insulation film 11f are made of SiN, and the latter has a higher ratio of Si, so that a trap region is formed. A light emitted from an organic EL layer 11a is made to enter the semiconductor layer 11b via the transparent electrode 10a, and carriers (holes and electrons) to be trapped by the trap region is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage element for writing and erasing data at high speed by irradiating light, a driving method thereof, and a storage device. The present invention also relates to an imaging device configured using such a function of the storage element.

[0002]

2. Description of the Related Art A non-volatile memory (EEPROM; Electric Erasa) which allows a user to write data and electrically erase the data.
As a ble Programmable Read Only Memory, a double gate memory including a thin film transistor in which a coplanar structure and an inverted staggered structure are combined is known.

FIG. 12 is a sectional view showing the structure of a conventional double gate memory. As shown, in this double gate memory, a bottom gate electrode 14a made of aluminum is formed on a glass substrate 10. S is formed on the substrate 10 so as to cover the bottom gate electrode 14a.
Bottom gate insulating film 14 made of iN (silicon nitride)
b is formed.

A semiconductor layer 14c made of a-Si (amorphous silicon) is formed on the bottom gate insulating film 14b so as to face the bottom gate electrode 14a.
On both sides of the semiconductor layer 14c, a source electrode 14e and a drain electrode 14f are formed via an n + Si layer 14d. Bottom gate insulating film 1
4b, a top gate insulating film 14 made of SiN
g is formed. A top gate electrode 14h made of aluminum is formed on the top gate insulating film 14g at a position facing the semiconductor layer 14c.

The bottom gate electrode 14a and the top gate electrode 14h are formed so as to partially overlap the source electrode 14e and the drain electrode 14f, respectively. Also, the bottom gate insulating film 14
b has a higher Si ratio in the vicinity of the interface with the semiconductor layer 14c than in the other portions and has a ratio of Si: N ≒ 1: 1, and has a trap region for trapping carriers (“−” in the figure).
− − − − ”) Is formed. In the region of the bottom gate insulating film 14b near the glass substrate 10 and the top gate insulating film 14g, Si: N ： 3: 4.

Next, the operating principle of the double gate memory will be described with reference to FIG. First, when data is erased (set to 0), as shown in FIG.
-20 (V) is applied to each of the bottom gate electrode 14a and the top gate electrode 14h, and 0 (V) is applied to each of the source electrode 14e and the drain electrode 14f. At this time, in the semiconductor layer 14c, the bottom gate electrode 14
A small amount of heat excites holes at the overlapping portion of the source electrode 14e or the drain electrode 14f to generate holes. The generated holes correspond to -20 of the bottom gate electrode 14a.
(V), the bottom gate insulating film 14
b is trapped in the trap region. However, it takes about 1 second for holes to be trapped in the trap region in the semiconductor layer 14c at normal temperature and normal pressure.

Next, when data is written (set to 1), as shown in FIG.
+20 (V) for 4a, 0 for top gate electrode 14h
(V) to apply the source electrode 14e and the drain electrode 14
0 (V) is applied to each of f and f. At this time, electrons as majority carriers in the semiconductor layer 14c are attracted by +20 (V) of the bottom gate electrode 14a and trapped in the trap region of the bottom gate insulating film 14b.

[0008] When data is read, FIG.
As shown in (c) and (d), the bottom gate electrode 14a
+10 (V), 0 (V) to the top gate electrode 14h,
0 (V) is applied to the source electrode 14e and + is applied to the drain electrode 14f.
10 (V) is applied. At this time, if the data is in the erased state, as shown in FIG. 13C, the electric field generated by the holes trapped in the trap region or the electric field generated by the trapped holes Does not hinder the electric field of the bottom gate electrode 14a, an n-channel is formed in the semiconductor layer 14c. Thus, a current flows between the source electrode 14e and the drain electrode 14f, and data can be read as the erased state (0).

On the other hand, when the data is in the written state (1), as shown in FIG. 13D, even if a positive voltage is applied to the bottom gate electrode 14a, it is trapped in the trap region. Disturbed by the electric field created by the electrons,
The n-channel in the semiconductor layer 14c is pinched off. That is, a state in which a continuous n-channel is not formed is obtained. As a result, the source electrode 14e and the drain electrode 1
Even if there is a potential difference with respect to 4f, current does not flow and data can be read in the write state (1).

In forming the n-channel in the semiconductor layer 14c, an electric field generated by +10 (V) of the bottom gate voltage VBG applied to the bottom gate electrode 14a and a trap region in the bottom gate insulating film 14b are trapped. Both the electric field due to the electric charge has an effect. Therefore, as shown in the current-voltage characteristic diagram of FIG. 14, the potential difference Vd between the source electrode 14e and the drain electrode 14f is +10 (V), the channel length of the semiconductor layer 14c is 10 μm, and the channel width is 100 μm. When the top gate voltage VTG applied to the top gate electrode 14h is shifted in the direction of the arrow, hysteresis occurs in the read current in such a double gate memory. When the top gate voltage VTG is applied to the top gate electrode 14h, the hysteresis causes a difference in the drain current Id flowing after erasing and after writing. However, since the region of the semiconductor layer 14c where the channel is formed is close to the trap region of the bottom gate insulating film 14b, carriers trapped in the trap region are reduced by the channel. As indicated by the broken line in FIG. 14, the trapped holes after erasing are particularly reduced, so that there is a problem that the difference in the drain current Id at the time of reading is reduced and the detection accuracy is deteriorated.

The data erase state (0) is achieved by trapping holes in the trap region of the bottom gate insulating film 14b. The holes to be trapped must be generated by thermal excitation. For this reason, it takes time to generate a sufficient amount of holes, and there is a time difference of two digits or more in data writing as compared with data writing in which electrons, which are majority carriers, are injected into the trap region. I was Therefore, it has been difficult to practically use a storage element using such a double-gate memory.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage element, a driving method thereof, and a storage device which can perform both writing and erasing of data with high accuracy in a short time.

Another object of the present invention is to provide an image pickup apparatus which can obtain various mass production advantages by using such a storage element also as an image pickup element.

[0014]

In order to achieve the above object, a storage element according to a first aspect of the present invention has a first element to which a predetermined voltage corresponding to each of data erasing, writing, and reading is supplied. A gate electrode, a first gate insulating film formed on the first gate electrode, and a carrier generated inside by being excited by incident light;
A semiconductor layer that forms a channel by a voltage supplied to the gate electrode; a drain electrode and a source electrode that allow a current to flow through a channel formed in the semiconductor layer according to the supplied voltage; the semiconductor layer and the drain A second gate insulating film formed on an electrode and a source electrode and forming a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; and the semiconductor on the second gate insulating film. A predetermined voltage is formed at a position corresponding to the layer, and a predetermined voltage corresponding to each of data erasing, writing or reading is supplied, and carriers in the semiconductor layer are trapped in the second gate insulating film according to the supplied voltage. A second gate electrode to be trapped in a region, and a light emitting device that emits light in accordance with a supplied voltage and makes light incident on the semiconductor layer. Characterized in that it comprises an element.

In the above storage element, a voltage corresponding to data reading is supplied to the second gate electrode and the first gate electrode depending on whether carriers trapped in the trap region of the second gate insulating film are holes or electrons. Sometimes, a channel is formed or not in the semiconductor layer due to carrier charge. That is, the type of carriers to be trapped determines whether or not a current flows between the drain electrode and the source electrode when reading data. Therefore, it is possible to read whether data is in an erased state or a written state. it can. Here, carriers trapped in the trap region are quickly generated in the semiconductor layer by making the light emitted by the light emitting element incident thereon, so that the number of carriers is larger than the amount of carriers generated by thermal excitation, so that data is erased. Alternatively, writing can be performed at high speed. The voltage and time applied to the second gate electrode for trapping holes are +20 (V) or more and several ns.
A time of about tens ns is sufficient. The voltage and time applied to the second gate electrode for trapping electrons may be -20 (V) or less and about 0.1 ms to several ms.

In the above-mentioned storage element, the first gate insulating film and the second gate insulating film may be made of, for example, silicon nitride. in this case,
The trap region can be formed in the second gate insulating film by setting the composition of silicon nitride in the second gate insulating film such that the proportion of silicon is higher than that in the first gate insulating film. .

In the above memory element, the semiconductor layer is
For example, it may be made of amorphous silicon having electrons as majority carriers. In this case, the semiconductor layer may form a channel on the opposite side of the interface with the second gate electrode according to the voltage supplied to the first gate electrode.

Due to this structure, the channel does not lose the carriers trapped in the trap region,
A stable hysteresis loop can be obtained.

In the above storage element, the first gate electrode is constituted by a transparent electrode extending to the outside of the first gate insulating film, and the light emitting element transmits light emitted through the transparent electrode to the semiconductor. The light may be incident on the layer.

In this case, a portion extending to the outside of the first gate electrode can also serve as one electrode of the light emitting element.

In the above memory element, the second gate electrode is constituted by a transparent electrode also serving as one electrode of the light emitting element, and the light emitting element transmits light emitted through the transparent electrode to the semiconductor layer. Can be incident.

In the storage element, for example, a state in which holes are trapped in the trap region of the second gate insulating film is a data erased state, and electrons are trapped in the trap region of the second gate insulating film. The state in which data is written can be a data write state.

In order to achieve the above object, a method for driving a storage element according to a second aspect of the present invention comprises a first gate electrode to which a predetermined voltage is supplied according to each of data erasing, writing and reading. A first gate insulating film formed on the first gate electrode, and a semiconductor layer which is excited by incident light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode And, according to the supplied voltage, a drain electrode and a source electrode that cause a current to flow through a channel formed in the semiconductor layer, and the semiconductor layer is formed on the semiconductor layer and the drain electrode and the source electrode. A second gate insulating film forming a trap region for trapping carriers generated in the semiconductor layer at an interface of the second gate insulating film; A predetermined voltage is formed at a position corresponding to the semiconductor layer, and a predetermined voltage is supplied according to each of data erasing, writing, and reading, and carriers in the semiconductor layer are transferred to the second gate insulating film according to the supplied voltage. A light-emitting element of a memory element including a second gate electrode trapped in a trap region of the light-emitting element and a light-emitting element that emits light according to a supplied voltage and causes light to enter the semiconductor layer; Supplying a voltage for trapping one of holes or electrons of carriers generated by the incident light into a trap region of the second gate insulating film to the second gate electrode; A data erasing step of causing the element to be in a data erasing state; and causing the light emitting element to emit light so that light is incident on the semiconductor layer. Said second holes or electrons of the other among the carriers generated by light
Supplying a voltage for trapping in the trap region of the gate insulating film to the second gate electrode to cause the storage element to be in a data write state; and applying a predetermined voltage to the drain electrode and the source electrode. And reading a voltage that changes with a current flowing through the semiconductor layer to read data stored in the storage element.

In order to achieve the above object, a storage device according to a third aspect of the present invention comprises a first gate electrode to which a predetermined voltage is supplied according to each of data erasing, writing, and reading, A first gate insulating film formed on one gate electrode, a semiconductor layer that is excited by incident light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode; A drain electrode and a source electrode that allow a current to flow through a channel formed in the semiconductor layer in accordance with the applied voltage; and a drain electrode and a source electrode formed on the semiconductor layer and the drain electrode and the source electrode, and at an interface with the semiconductor layer. A second gate insulating film forming a trap region for trapping carriers generated in the semiconductor layer; and a semiconductor on the second gate insulating film. A predetermined voltage is formed at a position corresponding to the layer, and a predetermined voltage corresponding to each of data erasing, writing or reading is supplied, and carriers in the semiconductor layer are trapped in the second gate insulating film according to the supplied voltage. A memory panel in which a plurality of storage elements each including a second gate electrode trapped in a region are formed; a light-emitting element which emits light according to a supplied voltage and causes light to enter the semiconductor layer; and a storage element in which data is to be erased or written. Selecting means for selecting a light emitting element corresponding to the light emitting element, and emitting one of holes or electrons among carriers generated in the semiconductor layer by the light emitted from the light emitting element by the selecting means. Erasing means for supplying a voltage for trapping in a trap region to the second gate electrode to bring the data into an erased state; Supplying a voltage to the second gate electrode to trap the other of the holes or the electrons of the carriers generated in the semiconductor layer by the light emitted by the light emitting element to the trap region of the second gate insulating film; A writing unit for writing data, a predetermined voltage is applied between the drain electrode and the source electrode of a storage element from which data is to be read, and a voltage that changes according to a current flowing through the semiconductor layer is applied. Reading means for reading data from a corresponding storage element by reading.

In the above storage device, whether each storage element is in the data erased state or the written state is determined by the type of carriers trapped in the trap region.
Which carrier is trapped in the trap region depends on the voltage supplied to the second gate electrode by the erasing means or the writing means. Here, carriers trapped in the trap region are generated in the semiconductor layer by making light emitted by the light emitting element incident thereon, so that data can be erased or written at high speed.

To achieve the above object, an imaging apparatus according to a fourth aspect of the present invention comprises a first gate electrode to which a predetermined voltage is selectively supplied, and a first gate electrode formed on the first gate electrode. (1) a gate insulating film, a semiconductor layer which is excited by incident light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode;
A drain electrode and a source electrode that allow a current to flow through a channel formed in the semiconductor layer in accordance with the supplied voltage; and an interface formed on the semiconductor layer and the drain electrode and the source electrode, and A second gate insulating film forming a trap region for trapping carriers generated in the semiconductor layer, and formed at a position corresponding to the semiconductor layer on the second gate insulating film;
A predetermined voltage is selectively supplied, and a second gate electrode for trapping carriers in the semiconductor layer in a trap region of the second gate insulating film according to the supplied voltage is provided in a predetermined arrangement. The arranged memory panel,
An all-light emitting unit that generates carriers in all semiconductor layers by emitting light, an imaging unit that forms an optical image of an imaging target on the memory panel, and an optical image of the imaging target that is formed by the imaging unit. A voltage for trapping one of holes or electrons among carriers generated in the semiconductor layer by a light image formed on the memory panel in the trap region of the second gate insulating film is applied to the second gate insulating film. Writing means for supplying an electrode; and reading means for applying a predetermined voltage between the drain electrode and the source electrode, and sequentially reading a voltage that changes according to a current flowing through the semiconductor layer for each storage element. It is characterized by having.

In the above-described image pickup apparatus, light is incident on the semiconductor layers of all storage elements by the all light emitting means, and the trapped carriers are emitted by the all light emitting means in order to erase the carriers trapped before. Since carriers are generated in the semiconductor layer for rapid removal, fingerprints and the like can be sensed quickly and with high sensitivity. Further, the storage element on the memory panel is set in a data writing state by the brightness of the light formed on the memory panel by the imaging means. Then, the image to be imaged can be obtained as a binary image depending on whether the data read from each storage element by the reading means is in the written state or not. That is, the imaging device is substantially the same as the storage device according to the third aspect only by changing the method of controlling the light emission of the light emitting element and the method of controlling the voltage supplied to the second gate electrode and the first gate electrode. Since the configuration can be adopted, various mass production advantages can be obtained by sharing parts.

[0028]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] In this embodiment, a nonvolatile storage element (EEPROM) and a device capable of electrically writing and erasing data include:
The case where the present invention is applied will be described.

FIG. 1 is a block diagram showing the configuration of the storage device according to this embodiment. As shown, the storage device includes a memory panel 1 and a W / E / R (Write / Er).
ase / Read) selection driver 2, EL drive power supply circuit 3,
S / P (serial / parallel) converter 4 and buffer 5
, R (Read) selection driver 6, buffer 7, P /
It comprises an S (parallel / serial) converter 8 and a control unit 9.

The memory panel 1 includes a memory cell section 1A and an optical address section 1B. In the memory cell section 1A, a double gate memory 11, which is a nonvolatile storage element capable of electrically writing and erasing data, is arranged in a matrix. One line of this matrix corresponds to one word of data. The double gate memory 11 is configured by a transistor having two gates, a bottom gate and a top gate, as described later in detail.

The bottom gate of the double gate memory 11 is connected to the W / E / R selection driver 2 via a bottom gate line BGL. The top gate is connected to the buffer 5 via a top gate line TGL. The source is connected to the buffer 7 via the source line SL. The drain is connected to the R selection driver 6 via the drain line DL. The structure of the double gate memory 11 and writing, erasing, and reading of data in the double gate memory 11 will be described later in detail.

On the other hand, in the optical address section 1B, an organic EL is provided corresponding to the line (word) of the double gate memory 11.
An element 12 is provided. The anode of the organic EL element 12 is connected to the W / E / R selection driver 2 via the bottom gate line BGL, similarly to the bottom gate of the double gate memory 11. The cathode of the organic EL element 12 is connected to the EL drive power supply circuit 3 via the cathode line CL. The light emitted from the organic EL element 12 is incident on the bottom gate of the double gate memory 11 on the same line as described later.

According to a control signal W / E / Rcnt from the control unit 9, the W / E / R selection driver 2 applies a predetermined voltage via the bottom gate line BGL when erasing, writing, or reading data. To the bottom gate of the double gate memory 11 and the anode of the organic EL element 12. In the case of erasing and writing data, the W / E / R selection driver 2 sends a signal to the bottom gate line BG
The voltage output to L is 0 (V) on the line on which erasing or writing is performed, and -5 (V) on the other lines.
In the case of reading data, the voltage output from the W / E / R selection driver 2 to the bottom gate line BGL is +10 (V) on the line for reading and 0 (V) on the other lines.

The EL drive power supply circuit 3 supplies a voltage for causing the organic EL element 12 to emit light when erasing or writing data in the double gate memory 11 according to a control signal ELcnt from the control section 9, for example, -5 ( V) is supplied to the cathode of the organic EL element 12 via the cathode line CL. In the case of reading data, EL
The drive power supply circuit 3 supplies a voltage of +10 (V) to the cathode of the organic EL element 12 via the cathode line CL.

The S / P converter 4 converts the data DATA serially supplied from the control unit 9 for writing or erasing data into a parallel data signal and supplies the parallel data signal to the buffer 5.

The buffer 5 receives a control signal W from the control unit 9.
In accordance with / Ecnt, the data signals supplied in parallel from S / P converter 4 are respectively converted into predetermined voltage levels, and supplied to the top gate of double gate memory 11 via top gate line TGL. Buffer 5
Further, according to a control signal W / Ecnt from the control unit 9,
It has a function of discharging the top gate line TGL.

The R selection driver 6 supplies a predetermined voltage to the drain of the double gate memory 11 via the drain line DL according to the control signal Rcnt1 from the control unit 9. When reading data, the R selection driver 6 outputs +10 (V) to the drain line DL corresponding to the line of the double gate memory 11 from which data is read. In other cases, the R selection driver 6 outputs 0 (V) to the drain line DL.

The buffer 7 is provided with a control signal R from the control unit 9.
According to cnt2, the signal voltages read in parallel from the double gate memory 11 via the source line SL in word units are respectively converted into data signals of a predetermined level, and supplied to the P / S converter 8 in parallel. The buffer 7 also has a function of discharging the source line SL according to a control signal Rcnt2 from the control unit 9.

The P / S converter 8 is a double gate memory 1
1 and the data signal whose level is converted by the buffer 7 and supplied in parallel is converted into serial data d.
The data is converted to data and supplied to the control unit 9.

The control unit 9 controls the W / E / R selection driver 2 and EL
Control signals W / E / Rcnt,
ELcnt, W / Ecnt, Rcnt1, and Rcnt2 are supplied. The control signals W / E / Rcnt, Rcnt
Reference numeral 1 denotes an address signal of a line for erasing, writing, or reading data. The control unit 9 also supplies the serial data DATA to the S / P converter 4 and receives the serial data data from the P / S converter 8.

Next, the structure of the memory panel 1 of FIG. 1 will be described in detail. FIG. 2A is a plan view showing the structure of the memory panel 1, and FIG. 2B is a cross-sectional view (partially omitted) taken along line XX of FIG. 2A. Here, FIG.
Now, writing data to the double gate memory 11,
Only the parts necessary for erasure are shown. FIG.
2B, only one of the double gate memories 11 closest to the organic EL element 12 is shown.

As shown in FIGS. 2A and 2B, in the memory panel 1, first, an IT
The transparent electrode 10a corresponding to the number of storable data words composed of O (Indium Tin Oxide) or the like
From one side of the glass substrate 10 toward the opposite side,
That is, they are formed parallel to each other from the memory cell section 1A to the optical address section 1B. Transparent electrode 10a
Are also used as the bottom gate line BGL in FIG.

The transparent electrode 10a is used as a bottom gate electrode of the double gate memory 11 in the memory cell section 1A, and as an anode electrode of the organic EL element 12 in the light address section 1B, and is used as the organic EL layer 12a.
The light emitted in step (1) is guided to enter the semiconductor layer 11b of the double gate memory 11 on the corresponding line.

In the memory cell section 1A, a bottom gate insulating film 11a made of SiN is formed on the glass substrate 10 so as to cover the transparent electrode 10a. On the bottom gate insulating film 11a, at the intersection of the transparent electrode 10a and the top gate electrode 11g,
A semiconductor layer 11b made of -Si is formed, and on both sides of the semiconductor layer 11b, a source electrode 11d and a drain electrode 11e are formed on both ends of a top gate electrode 11g to be described later in plan view via an n + Si layer 11c. It is formed so as to overlap. A top gate insulating film 11f made of SiN is formed on the bottom gate insulating film 11a so as to cover them.

The memory panel 1 is formed so as to include a position on the top gate insulating film 11f facing the semiconductor layer 11b.
A top gate electrode 11g made of aluminum is formed extending from the upper part to the lower part of the substrate. The top gate electrode 11g also serves as the top gate line TGL in FIG. 1 and is connected to the buffer 5.

The top gate insulating film 11f has a higher Si ratio in the vicinity of the interface with the semiconductor layer 11b or the bottom gate insulating film 11a than in other portions.
N ≒ 1: 1 and a trap region (“−−−−−” in the figure) for easily trapping positive and loaded carriers.
− ”) Is formed. Note that in the regions near the top gate electrode 11g of the bottom gate insulating film 11a and the top gate insulating film 11f, Si: N ≒ 3: 4.

Although not shown, the semiconductor layer 11 is located between the bottom gate insulating film 11a and the top gate insulating film 11f.
In a position where b is not formed, a source line SL shown in FIG. 1 is formed extending vertically and connected to the source electrode 11d for each column (vertical direction). A drain line DL shown in FIG. 1 connected to the drain electrode 11e is formed for each (lateral direction).

On the other hand, in the optical address portion 1B, the organic E is extended from the upper part to the lower part of the memory panel 1 on the glass substrate 10 so as to cover one end of the transparent electrode 10a.
An L layer 12a is formed. And the organic EL layer 12
On a is formed a cathode electrode 12b made of MgAg, MgIn, AlLi or the like. The cathode electrode 12b corresponds to the cathode line CL in FIG. 1, and is connected to the EL drive power supply circuit 3.

The organic EL layer 12a is made of, for example, the transparent electrode 1
A hole transport layer formed of N, N'-di (α-naphthyl) -N, N'-diphenyl-1,1'-biphenyl-4,4'-diamine formed on the 0a side, and a cathode electrode Screw formed on the side of 12b
It has a two-layer structure with an electron transporting light-emitting layer made of beryllium (10-hydroxybenzo [h] quinoline), and in this case, emits light in a green wavelength range. The light in this wavelength range can generate carriers by photoexciting the semiconductor layer 11b of the double gate memory 11.

Next, the double gate memory 1 shown in FIGS.
The principle of operation 1 will be described in detail with reference to FIG. In the double gate memory 11, the transparent electrode 10
Since a functions as a bottom gate electrode, it will be described below as the bottom gate electrode 10a.

First, when data is to be erased (set to 0), as shown in FIG.
0 (V) for a, -20 (V) for top gate electrode 11g
And 0 (V) is applied to each of the source electrode 11d and the drain electrode 11e. At this time, the semiconductor layer 11b is irradiated with light from the bottom gate electrode 10a via the bottom gate insulating film 11a. Thereby, the semiconductor layer 11b
Is photoexcited and a large amount of carriers (holes and electrons) are generated more quickly than when no light is incident. The generated holes are attracted by -20 (V) of the top gate electrode 11g and are quickly trapped in the trap region of the bottom gate insulating film 11f. The trapped holes correspond to the top gate voltage V applied to the top gate electrode 11g.
Even when TG becomes 0 (V), it remains in the trap region until a certain period.

Next, when data is written (set to 1), as shown in FIG.
0 (V) for a, +20 (V) for top gate electrode 11g
And 0 (V) is applied to each of the source electrode 11d and the drain electrode 11e. At this time, the semiconductor layer 14
Electrons, which are usually majority carriers in c, are attracted by +20 (V) of the top gate electrode 11g and trapped in the trap region of the top gate insulating film 11g. When the semiconductor layer 11b is irradiated with light from the bottom gate electrode 10a via the bottom gate insulating film 11a, carriers are generated by photoexcitation, so that the time until electrons are trapped in the trap region becomes shorter. The trapped electrons are transferred to the top gate electrode 11g.
Is kept in the trap region until a certain period even if the top gate voltage VTG applied to the gate electrode becomes 0 (V).

When data is read out, FIG.
As shown in (c) and (d), the bottom gate electrode 10a
+10 (V), 0 (V) to the top gate electrode 11g,
0 (V) is applied to the source electrode 11d and + is applied to the drain electrode 11e.
10 (V) is applied. At this time, when the data is in the erased state (0), as shown in FIG. 3C, the semiconductor is caused by the electric field of the bottom gate electrode 10a and the electric field generated by the holes trapped in the trap region. An n-channel is formed in the layer 11b. As a result, a current flows between the source electrode 11d and the drain electrode 11e, and data can be read as the erased state (0).

On the other hand, when the data is in the written state (1), as shown in FIG. 3D, even if a voltage of +10 (V) is applied to the bottom gate electrode 10a, the trap region is trapped. The n-channel in the semiconductor layer 11b is pinched off because of the electric field generated by the electrons. That is, a state in which a continuous n-channel is not formed is obtained. Accordingly, even if there is a potential difference between the source electrode 11d and the drain electrode 11e, no current flows and data can be read in the written state (1).

The formation of the n-channel in the semiconductor layer 11b is performed by adding +10 applied to the bottom gate electrode 10a.
Both the electric field due to (V) and the electric field due to the charges trapped in the trap region of the top gate insulating film 11f influence. However, in this double gate memory 11, when the bottom gate electrode 10a and the trap region are located so as to sandwich the semiconductor layer 11b and the n + Si layer 11c is formed by wet etching, as shown in the current-voltage characteristic diagram of FIG. Then, hysteresis occurs in the read current. That is, when the n + Si layer 11c, which is a constituent member of the double gate memory 11, is patterned by wet etching, the etchant cannot have a sufficient selectivity with the semiconductor layer 11b made of a-Si, and as shown in FIG.
It etches inward from the partial n + Si layer 11c and the semiconductor layer 11b of length _{L E} source electrode 11d and the drain electrode 11e. Since this etching solution has a selectivity with respect to the source electrode 11d and the drain electrode 11e made of metal, the electrodes 11d and 11e are hardly etched. For this so-called offset structure, even by applying a voltage of about +10 (V) to the top gate electrode 11g, the portion of the length L _E of the channel length of the semiconductor layer 11b is,
The influence of the top gate voltage VTG of the top gate electrode 11g depends on the source electrode 11d and the drain electrode 11e, respectively.
And is substantially extinguished by the voltage applied to Therefore, an n-channel is not formed continuously in the channel length direction of the semiconductor layer 11b, and it becomes difficult for the drain current Id to flow sufficiently. Therefore, the formation of the n-channel is achieved by applying a positive voltage to the bottom gate electrode 10a which is formed continuously in the channel direction of the semiconductor layer 11b and has only the gate insulating film interposed therebetween. Therefore, even if holes are trapped in the top gate insulating film 11f, if the bottom gate electrode 10a is 0 (V), a continuous n-channel is not formed. In the double gate memory 11 used in FIG. 4, the channel length of the semiconductor layer 11b is set to 10 μm, the channel width is set to 100 μm, and the potential difference Vd between the source electrode 11d and the drain electrode 11e is set to +10 (V). The top gate voltage VTG applied to the top gate electrode 11g is set to 0 (V), and the bottom gate voltage VBG applied to the bottom gate electrode 10a is shifted in the direction of the arrow.

In the double gate memory 11, the region where holes are trapped during data erasing is the top gate insulating film 1.
Since the voltage for forming a channel at the time of reading is applied to the bottom gate electrode 10a on the semiconductor layer 11b side, the channel region, that is, the path through which electrons flow is generated on the bottom gate electrode 10a side in the semiconductor layer 11b. The electrons of the drain current are less likely to recombine with the trapped holes, and the hysteresis loop is stable irrespective of the formation of the n-channel.

The operation of the storage device according to this embodiment will be described below. The operation of the storage device according to this embodiment can be divided into three operations: (1) data writing, (2) data erasing, and (3) data reading.
These are all performed in units of words. Less than,
Each of these three operations will be described in detail.

(1) Writing of Data First, the controller 9 supplies one word of data to be written to the S / P converter 4 as serial data DATA. The supplied data for one word is converted into parallel data by the S / P converter 4, and the corresponding data signal is supplied to the buffer 5.

The control unit 9 then controls the control signals W / E / Rc
nt, the bottom gate line BGL (transparent electrode 10) to which data is to be written from the W / E / R selection driver 2
From a), a voltage of 0 (V) is output. At this time, W
The / E / R selection driver 2 supplies a voltage of −5 (V) to the other bottom gate lines BGL (transparent electrodes 10 a), but the bottom gate lines BGL have a top gate insulation where carriers are already trapped. Since it is located on the opposite side to the film 11f, the negative voltage of -5
The electric field of (V) does not eliminate electrons or holes trapped in the top gate insulating film 11f.

The control section 9 supplies a voltage of -5 (V) to the cathode line CL (cathode electrode 12b) from the EL drive power supply circuit 3 according to the control signal ELcnt. As a result, a potential difference is generated between the anode electrode (transparent electrode 10a) and the cathode electrode 12b of the organic EL element 12 on the line to which data is to be written, and the organic EL layer 12a of the organic EL element 12 on that line emits light and becomes transparent. The light is incident on the semiconductor layer 11b of the double gate memory 11 on the corresponding line via the electrode 10a.

When light is incident on the semiconductor layer 11b on the line to which data is to be written, carriers (holes and electrons) are generated in the semiconductor layer 11b. ,
The amount of electrons inside is larger than that of other lines.

In this state, control unit 9 controls signal W / E
cnt, the top gate line TGL corresponding to the bit whose data signal is “1” from the buffer 5
A voltage of +20 (V) is output to the (top gate electrode 11g) for about 10 ns while light is being irradiated.

Then, light is irradiated through the bottom gate line BGL (transparent electrode 10a), and in the double gate memory 11 in which a voltage of +20 (V) is applied to the top gate electrode 11g, an electric field generated by the voltage causes the top gate electrode 11g to generate a top voltage. The semiconductor layer 11 is formed in the trap region of the gate insulating film 11f.
Electrons generated by light irradiation from b are trapped. Also in the double gate memory 11 that has been erased before writing, holes are removed and electrons are trapped. Thereby, the double gate memory 11
Becomes the data write state (1). The double gate memory 1 in which a voltage of +20 (V) is applied to the top gate electrode 11g without irradiating the semiconductor layers 11b in the same row with light.
In the case of No. 1, in the case of the double gate memory 11 in which few electrons were generated in the semiconductor layer 11b and the applied voltage time was as short as 10 ns, almost no electrons were trapped in the trap region and the state before writing was erased. The trapped holes can be maintained without being removed.

(2) Erasure of Data First, the control section 9 supplies the S / P converter 4 with data in which one word is all "0" as serial data DATA. The supplied data for one word is
The data is converted into parallel data by the S / P converter 4, and the corresponding data signal is supplied to the buffer 5.

The control unit 9 then controls the control signals W / E / Rc
nt, the bottom gate line BGL (transparent electrode 10) from which data should be erased from the W / E / R selection driver 2
From a), a voltage of 0 (V) is output. At this time, W
The / E / R selection driver 2 supplies a voltage of −5 (V) to the other bottom gate lines BGL (transparent electrodes 10 a), but removes the carriers trapped in the top gate insulating film 11 f. I can't. This operation is performed collectively with the above-described write operation.

The control section 9 supplies a voltage of -5 (V) from the EL drive power supply circuit 3 to the cathode line CL (cathode electrode 12b) according to the control signal ELcnt. Thereby, the organic EL element 1 on the line from which data is to be erased
2 anode electrode (transparent electrode 10a) and cathode electrode 1
2b, a potential difference is generated, the organic EL layer 12a of the organic EL element 12 on that line emits light, and is incident on the semiconductor layer 11b of the double gate memory 11 on the corresponding line via the transparent electrode 10a. This operation is performed collectively with the above-described write operation.

Light is incident on the semiconductor layer 11b on the line from which data is to be erased, thereby causing the semiconductor layer 1b to be erased.
Carriers (holes and electrons) are generated in 1b, and the amount of internal holes in the semiconductor layer 11b of the double gate memory 11 in this line is larger than that in other lines.

In this state, control unit 9 controls signal W / E
cnt from buffer 5 to top gate line TG
A voltage of −20 (V) is output to L (top gate electrode 11g) for about 1 ms during the light irradiation period (in this case, the data signal is set to “0”). This operation is based on the above-mentioned top gate line TGL.
+20 (V) voltage writing operation is performed collectively.

Then, light is irradiated through the bottom gate line BGL (transparent electrode 10a), and in the double gate memory 11 in which a voltage of -20 (V) is applied to the top gate electrode 11g, the electric field generated by the voltage causes The semiconductor layer 11 is formed in the trap region of the top gate insulating film 11f.
Holes are trapped from b. Also in the double gate memory 11 which has been written before erasing, holes are trapped while electrons are removed. As a result, the double gate memory 11 enters the data erase state (0).

In the double gate memory 11 in which a voltage of -20 (V) is applied to the top gate electrode 11g without irradiating light to the semiconductor layers 11b in the same column, the number of electrons generated in the semiconductor layer 11b is small, and the applied voltage is low. Since the time is as short as 1 ms, almost no holes are trapped in the trap region, and in the case of the double gate memory 11 in which the state before the writing is the writing, the trapped electrons can be maintained without being removed. it can.

As described above, writing or erasing of data corresponding to each bit is performed simultaneously along the optical scanning. The write state of each bit continues until the erase state is overwritten, and the erase state continues until the write state is overwritten.

(3) Data reading The control unit 9 discharges the top gate line TGL (top gate electrode 11g) in accordance with the control signal W / Ecnt, and controls the buffer 7 in accordance with the control signal Rcnt2.
To discharge the source line SL.
Thereby, the potentials of the top gate line TGL (top gate electrode 11g) and the source line SL are all 0.
(V).

Next, the control unit 9 controls the control signal W / E / Rc.
nt, the bottom gate line BGL (transparent electrode 10) from which data is to be read from the W / E / R selection driver 2.
From (a), a voltage of +10 (V) is output. At this time, the W / E / R selection driver 2 supplies a voltage of 0 (V) to the other bottom gate lines BGL (transparent electrodes 10a).

The control section 9 supplies a voltage of +10 (V) to the cathode line CL (cathode electrode 12b) from the EL drive power supply circuit 3 by the control signal ELcnt.
Accordingly, no current flows between the anode electrode (transparent electrode 10a) and the cathode electrode 12b of the organic EL element 12 because the potential is equal or reverse, and neither organic EL layer 12a emits light. Therefore, no light is incident on the semiconductor layer 11b of any of the double gate memories 11.

In this state, the control unit 9 outputs the control signal Rcn
At t1, +10 (V) is output from the R selection driver 6 to the drain line DL of the line from which data is to be read. At this time, the semiconductor layer 11b of the double gate memory 11 in the data write state (1) has
As shown in FIG. 3D, n channels have disappeared. Further, as shown in FIG. 3C, the trapped holes do not act in the direction of decreasing the channel in the semiconductor layer 11b of the double gate memory 11 in the data erase state (0). A continuous n-channel is formed. Therefore, in the double gate memory 11 in the data write state (1), no current flows between the source electrode 11d and the drain electrode 11e, and the voltage of the source line SL remains almost 0 (V). Become. On the other hand, in the double gate memory 11 in the data erase state (0), a current flows between the source electrode 11d and the drain electrode 11e, and the voltage of the source line SL becomes +10 (V).

The control unit 9 causes the data signal corresponding to the voltage of the source line SL to be supplied from the buffer 7 to the P / S converter 8 in parallel for each row by the control signal Rcnt. Whether the data is write data or erase data is read as the serial data data.

As described above, the double gate memory 11 provided in the memory panel 1 used in the storage device according to this embodiment has the top gate insulating film 11f having a silicon-rich structure, and the trap region And the carriers trapped in the trap region are generated by making light incident from the transparent electrode 10a. For this reason, the time required for the carrier (hole or electron) to be trapped in the trap region, that is, the time until the data is in the erased state or the written state is shortened as compared with the conventional double gate memory. In particular, a-Si
The difference in the time until the data is erased, in which holes serving as minority carriers of the semiconductor layer 11b are trapped in the trap region, appears more remarkably than in the conventional double gate memory.

Further, since carriers are generated by photoexcitation in the semiconductor layer 11b, it is possible to prevent carriers from being injected into the trap region of the unselected double gate memory 11 and causing data corruption.

Further, since the position where the trap region is formed is on the side opposite to the surface where the n-channel is formed in the semiconductor layer 11b, the amount of carriers trapped in the trap region flows through the n-channel. It is not greatly attenuated by the current. For this reason, as shown in FIG. 4, the double gate memory 11 of this embodiment has a hysteresis of the read current which is smaller than that of the conventional double gate memory.
Even if writing and erasing are repeated many times, there is almost no change.

Further, the memory panels 1, 1-1 to 1-4
Has a so-called offset structure as shown in FIG. 9, so that the top gate voltage 11g cannot substantially form an n-channel even if a positive voltage is applied. In this case, the effect on the carriers trapped in the trap region of the top gate insulating film 11f by the voltage applied to the drain electrode 11e at the time of reading data is reduced, and the amount of carriers is less likely to change. Further, since the opposite side of the n-channel formed in the semiconductor layer 11b has an offset structure, the influence of the current flowing between the drain electrode 11e and the source electrode 11d is reduced.

In the present invention, not only the memory panel 1 described above but also various modifications are present. Hereinafter, other embodiments (first to fourth modified embodiments) of the memory panel included in the scope of the present invention will be described with reference to the corresponding drawings.

(First Modification) FIG. 5 is a sectional view showing a structure of a memory panel according to a first modification. As shown in the figure, in this memory panel 1-1, instead of the organic EL element 12 composed of the transparent electrode 10a, the organic EL layer 12a and the cathode electrode 12b, an optical address section 1B
Using an LED array unit 12 'for the optical joint 1
2 ". Thus, for optical addressing,
A light emitting element other than the organic EL element can be used.

(Second Modification) FIG. 6 is a sectional view showing a structure of a memory panel according to a second modification. As shown in the figure, in this memory panel 1-2, a double gate memory 11 is formed on one surface of a glass substrate 10, and the glass substrate 1 is opposed to each double gate memory 11.
0, the anode 12c, the organic EL layer 12
d, an organic EL element 12 comprising a cathode electrode 12e. The bottom gate electrode 11h is made of transparent ITO or the like. Here, the organic EL element 1
If light emission can be performed by selecting one by one, data can be erased or written in 1-bit units. Further, the anode electrode 12c is the transparent electrode 1
A plurality of bits can be collectively irradiated by extending like 0a.

(Third Modification) FIG. 7 is a sectional view showing a structure of a memory panel according to a third modification. As shown, in the memory panel 1-3, the top gate electrode 10b of the double gate memory 11 is transparent IT
The bottom gate electrode 11h is made of an opaque conductive material such as aluminum. Top gate electrode 1
Ob also serves as an anode electrode of the organic EL element 12, on which an organic EL layer 12c and a cathode electrode 12g are formed. In this case, if the organic EL layer 12c and the cathode electrode 12d are formed for each line, data can be erased or written in word units without using a light guide path.

(Fourth Modification) FIG. 8 is a sectional view showing a structure of a memory panel according to a fourth modification. As shown in the figure, in the memory panel 1-4, the bottom gate electrode 11h of the double gate memory 11 is made of aluminum or the like, and the top gate electrode 11i is made of transparent ITO. Further, no organic EL element is formed on the glass substrate 10, and the flat light emitting panel 13 is arranged so as to face the top gate electrode 11i. As a result, batch erasing can be performed for all bits or blocks.

[Second Embodiment] In this embodiment, the present invention is applied to a fingerprint sensor that captures a fingerprint image using the function of the memory panel described in the first embodiment. Will be described.

FIG. 10 is a sectional view schematically showing the structure of the fingerprint sensor according to this embodiment. As shown, the fingerprint sensor includes a memory panel 1 and a lamp 20.
, A prism 30 and a condenser lens 40. The memory panel 1 is provided with a condenser lens 40 on the glass substrate 10 side.
Are arranged in the direction of.

The lamp 20 irradiates light on the fingerprint placed on the prism 30. The prism 30 is for placing a fingerprint on the fingerprint collation unit 30a. The light emitted from the lamp 20 is incident on the prism 30, and the light is reflected on the contact surface with the fingerprint according to the fingerprint pattern to collect the light. The light is emitted toward the optical lens 40. The condenser lens 40 forms an image of light emitted from the lamp 20 and reflected by the fingerprint collation unit 30 a of the prism 30 on the memory panel 1. The light emitted from the lamp 20 is not directly incident on the memory panel 1.

In the fingerprint sensor according to this embodiment, the same drive circuit as that used in the storage device shown in FIG. 1 is used as a drive circuit for reading a fingerprint image. However, the control signal supplied from the control unit 9 to each unit is different from that of the first embodiment in terms of the signal supply timing, and the data DATA supplied from the control unit 9 to the S / P converter 4 is In order to trap electrons generated in accordance with the amount of light corresponding to the fingerprint pattern in the double gate memory 11, data similar to the data for performing writing in the first embodiment, that is, the buffer 5 The data is such that the voltage supplied to the top gate electrode 11g of the memory 11 becomes +20 (V).

Hereinafter, the operation of the fingerprint sensor according to this embodiment will be described. When taking fingerprint images,
First, the control unit 9 sends the serial data DATA to the S / P converter 4 so that the entire data for one word is in the erased state (0) of data or in a neutral state with almost no electrons or holes trapped in the trap region. In addition, the control signal W / Ecnt further supplies a data signal in which one word is completely erased or neutral from the buffer 5 from the top gate line TGL (top gate electrode 11).
f). As a result, a data signal for erasing data (0) or a neutral state is supplied to the top gate electrodes 11f of all the double gate memories 11. At this time, all the organic EL elements 12 and / or the lamps 20 emit light, light is forcibly incident to generate carriers, and the electrons trapped by the previous sense are quickly removed. When forced removal is performed only with the lamp 20, the organic E
The L element 12 does not need to be provided, but in that case, the fingerprint matching unit 3 is set so that all the double gate memories 11 are irradiated with light.
An operation of reflecting light by, for example, smoothly covering the entire surface of Oa with an opaque member is required.

Next, all the double gate memories 11 on the memory panel 1 are set to a data write state. That is, a voltage of 0 (V) is supplied from the W / E / R selection driver 2 to all bottom gate lines BGL (transparent electrodes 10a), and +20 is supplied from the buffer 5 to all top gate lines TGL (top gate electrodes 11f). (V). As a result, all the double gate memories 11 enter the data write state (1). During this time, even if the lamp 20 is turned on, the light is not reflected on the double gate memory 11 because the fingerprint is not in the fingerprint collating unit 30a, and therefore the lamp 20 may be turned on or off.
At this time, the organic EL element 12 does not emit light.

Next, the lamp 20 is turned on for a certain period, and light is applied to the fingerprint placed on the fingerprint collation unit 30a of the prism 30. This light reflects a considerable amount at the convex part of the fingerprint, but has a small amount of reflection at the concave part, becomes a light image, exits from the prism 30, and enters the double gate memory 11 via the condenser lens 40. .

At this time, in the double gate memory 11 in which the light from the lamp 20 enters the semiconductor layer 11b via the prism 30, the condenser lens 40, the glass substrate 10 and the transparent electrode 10b, the semiconductor layer 11b has sufficient light. Since an amount of electrons is generated, the electrons are trapped in the trap region of the top gate insulating film 11f in a short time, and the state becomes the data write state (1). On the other hand, the semiconductor layer 11
In the double gate memory 11 where the light incident on b is dark, the amount of electrons generated in the semiconductor layer 11b is small, so that nothing is trapped or holes are trapped in the trap region.

As a result, all the double gate memories 11 are fixed to either a data write state or a non-data write state.

Next, the reading operation will be described. In the read operation, +10 is applied to the drain line DL of a predetermined row.
(V) is applied to the bottom gate line BGL by +10
A voltage of (V) is applied to form an n-channel according to the reflected light. Here, since the double gate memory 11 corresponding to the bit of the fingerprint convex portion is in the write state (1), the source line SL remains at a voltage of about 0 (V) and corresponds to the bit of the fingerprint concave portion. Double gate memory 11
Since almost no trapped electrons hinder the formation of the n-channel, a drain current flows and a voltage signal of about +10 (V) is output to the buffer 7 via the source line SL. This reading operation is sequentially performed for each row, and the operation ends at the last row. The data data thus obtained from the P / S converter 8 becomes binary image data of dark and bright fingerprints, and the control unit 9 compares the data with data stored in advance.

The above imaging apparatus has a structure in which a plurality of double gate memories 11 are arranged vertically and horizontally in a matrix, and a fingerprint is fixed and sensed by a fingerprint collating unit 30a, as shown in FIG. A structure in which the double gate memories 11 are arranged in one row may be used. In this case, a finger is placed on the fingerprint collation unit 30a and slid in the column direction.

During the sliding, a voltage of +20 (V) is output from the buffer 5 to the top gate line TGL to trap electrons according to the reflected light that differs due to the unevenness of the fingerprint.
(V), a voltage of +10 (V) is applied to the drain line DL from the R selection driver 6 during or after the trap, +10 (V) is applied to the bottom gate line BGL, and the source line SL according to the reflected light. Are sequentially supplied to the buffer 7. The P / S converter 8 converts the data signal read from the double gate memory 11 and converted in level by the buffer 7 and supplied in parallel to the data signal for each row or for each of a plurality of repeated rows. The data is converted into data and supplied to the control unit 9. Immediately before the fingerprint sense, the electrons trapped by the previous sense are transferred to the organic EL element 12.
And / or the irradiation of the lamp 20 and the application of a negative voltage to the top gate line TGL are forcibly eliminated, so that the trap region has little carriers or an erased state in which holes are trapped. Needless to say, the organic EL element 12 does not need to be provided when forcibly removing with the lamp 20 alone, but in that case, the entire surface of the fingerprint collation unit 30a is smoothly covered so that light is applied to all the double gate memories 11. Is required.

In the case of the imaging device having this structure, the number of the double gate memories 11 is reduced, so that the manufacturing can be performed with a high yield.

As described above, in the fingerprint sensor according to this embodiment, as a circuit for photographing a fingerprint image, only the control signal output from the control unit 9 is changed.
The same circuit as the storage device (FIG. 1) described in the first embodiment can be used. Since this control circuit can be changed by changing software or firmware, hardware having the same configuration as the storage device can also be used as an imaging device for capturing a fingerprint image.

As described above, by applying hardware having the same configuration to two different uses, that is, a storage device and an imaging device, the amount of production as one piece of hardware increases, and various merits of mass production, such as cost reduction, are obtained. Advantages such as reduction and reduction of the amount of intermediate stock in the manufacturing process can be obtained.

In the first and second embodiments, the double gate memory 11 has an n-channel structure. However, it may be operated as a p-channel structure with the polarity of each drive voltage reversed.

The imaging device of the present invention can be used not only as a fingerprint sensor as described above, but also as another imaging device such as a scanner. Also, the memory panels 1-1 and 1-4 shown in FIG. 5 or FIG. 8 described as a modification of the first embodiment can be applied as the imaging device (however, the memory panel shown in FIG. In the panel 1-4, the top gate electrode 11i is arranged so as to face the condenser lens 40, and the flat light-emitting panel 13 is arranged out of the path of light from the condenser lens 40).

[0104]

As described above, according to the present invention,
Time for writing and erasing data to the storage element can be shortened.

Further, according to the imaging apparatus of the present invention, various mass production advantages can be obtained by sharing parts with the storage device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a storage device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a structure of a memory panel of FIG. 1,
(A) is a top view, (b) is XX sectional drawing of (a).

FIG. 3 is a diagram for explaining the operation principle of the double gate memory of FIGS. 1 and 2;

FIG. 4 is a current-voltage characteristic diagram of the double gate memory of FIGS. 1 and 2;

FIG. 5 is a cross-sectional view showing a structure of a memory panel according to a modification of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a structure of a memory panel according to a modification of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a memory panel according to a modification of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of a memory panel according to a modification of the first embodiment of the present invention.

FIG. 9 is a diagram showing a structure of a double gate memory according to a modification of the first embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a structure of an imaging device according to a second embodiment of the present invention.

FIG. 11 is a block diagram illustrating a circuit configuration of an imaging device according to a modification of the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a structure of a conventional memory panel.

FIG. 13 is a diagram showing the operation principle of the double gate memory of FIG.

14 is a current-voltage characteristic diagram of the double gate memory of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory panel, 1A ... Memory cell part, 1B ... Light address part, 2 ... W / E selection driver, 3 ... EL drive power supply circuit, 4 ... S / P ( Serial / parallel) converter, 5 ... buffer, 6 ... R selection driver, 7 ... buffer, 8 ... P / S (parallel / serial) converter, 9 ...
..Control unit, 10: glass substrate, 10a: transparent electrode, 1
0b: Top gate electrode (also serves as anode), 11:
Double gate memory, 11a ... bottom gate insulating film,
11b ... semiconductor layer, 11c ... n + Si layer, 11d ...
Source electrode, 11e Drain electrode, 11f Top gate insulating film, 11g Top gate electrode, 11h
Bottom gate electrode, 11h ... bottom gate electrode, 11
i: Top gate electrode, 12: Organic EL element, 12 ′
... LED array unit, 12 "... optical junction, 1
2a: Organic EL layer, 12b: Cathode electrode, 12c ...
-Anode electrode, 12d: Organic EL layer, 12e: Cathode electrode, 12f: Organic EL layer, 12g: Cathode electrode, 13: Flat light-emitting panel

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/788 H01L 27/14 A 29/792 29/78 371 H04N 5/335 // H05B 33/14

Claims (8)

[Claims] A first gate electrode to which a predetermined voltage corresponding to each of data erasing, writing, and reading is supplied; a first gate insulating film formed on the first gate electrode; A semiconductor layer that is excited by light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode; and a current flows through a channel formed in the semiconductor layer according to the supplied voltage. A drain electrode and a source electrode to be caused to flow, and a second trap region formed on the semiconductor layer and the drain electrode and the source electrode and trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer. A gate insulating film, formed at a position corresponding to the semiconductor layer on the second gate insulating film, for erasing, writing or A second gate electrode for supplying a predetermined voltage corresponding to each of the protrusions, and for trapping carriers in the semiconductor layer in a trap region of the second gate insulating film in accordance with the supplied voltage; A light emitting element that emits light according to the formula (1) and makes light incident on the semiconductor layer. 2. The semiconductor device according to claim 1, wherein the first gate insulating film and the second gate insulating film are made of silicon nitride, and a composition of silicon nitride of the second gate insulating film is smaller than that of the first gate insulating film. The storage element according to claim 1, wherein the ratio is high. 3. The semiconductor layer is made of amorphous silicon having electrons as majority carriers, and a channel is formed on an opposite side of an interface with the second gate electrode according to a voltage supplied to the first gate electrode. The storage element according to claim 1, wherein the storage element is formed. 4. The first gate electrode comprises a transparent electrode extending to the outside of the first gate insulating film, and the light emitting element makes light emitted through the transparent electrode incident on the semiconductor layer. The storage element according to any one of claims 1 to 3, wherein: 5. The memory device according to claim 4, wherein a portion extending to the outside of the first gate electrode also serves as one electrode of the light emitting device. 6. A first gate electrode to which a predetermined voltage corresponding to each of data erasing, writing, and reading is supplied, a first gate insulating film formed on the first gate electrode, and an incident light. A semiconductor layer which is excited by light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode, and a current flows through a channel formed in the semiconductor layer according to the supplied voltage. A drain electrode and a source electrode to be flowed, and a trap region formed on the semiconductor layer and the drain electrode and the source electrode and trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer. A gate insulating film formed at a position corresponding to the semiconductor layer on the second gate insulating film, for erasing, writing, or reading data; A predetermined voltage corresponding to each of the gate electrodes is supplied, a second gate electrode for trapping carriers in the semiconductor layer in a trap region of the second gate insulating film according to the supplied voltage, and A light-emitting element that emits light and causes the light to enter the semiconductor layer. The light-emitting element emits light to the semiconductor layer and emits light to the semiconductor layer. Or a data erasing step of supplying a voltage for causing one of the electrons to be trapped in the trap region of the second gate insulating film to the second gate electrode to bring the storage element into a data erased state; The semiconductor layer is caused to emit light and light is incident on the semiconductor layer, and the other of the holes or electrons of the carriers generated by the incident light is transmitted to the second gate. Supplying a voltage for trapping in a trap region of an insulating film to the second gate electrode to cause the storage element to be in a data write state; and applying a predetermined voltage to the drain electrode and the source electrode. A data read step of reading data stored in the storage element by reading a voltage that is applied and changed by a current flowing through the semiconductor layer, thereby driving the storage element. 7. A first gate electrode to which a predetermined voltage is supplied according to each of data erasing, writing, and reading, a first gate insulating film formed on the first gate electrode, A semiconductor layer which is excited by light to generate carriers therein and forms a channel by a voltage supplied to the first gate electrode, and a current flows through a channel formed in the semiconductor layer according to the supplied voltage. A drain electrode and a source electrode to be flowed, and a trap region formed on the semiconductor layer and the drain electrode and the source electrode and trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer. A gate insulating film formed at a position corresponding to the semiconductor layer on the second gate insulating film, for erasing, writing, or reading data; And a second gate electrode configured to supply a predetermined voltage corresponding to each of the second gate electrodes and trap carriers in the semiconductor layer in a trap region of the second gate insulating film in accordance with the supplied voltage. A formed memory panel, a light-emitting element that emits light according to a supplied voltage and causes light to enter the semiconductor layer, and a selection unit that selects and emits light by selecting a light-emitting element corresponding to a storage element from which data is to be erased or written. A voltage for trapping one of holes or electrons among carriers generated in the semiconductor layer by the light emitted from the light emitting element by the selection means in the trap region of the second gate insulating film is applied to the second gate electrode. An erasing unit that supplies the data to an erased state, and a carrier generated in the semiconductor layer by light emitted from the light emitting element by the selecting unit. A writing means for supplying a voltage for trapping the other of the holes or the electrons into the trap region of the second gate insulating film to the second gate electrode and setting a data write state; Reading means for reading data from a corresponding storage element by applying a predetermined voltage between the drain electrode and the source electrode of the storage element, and reading a voltage that is changed by a current flowing through the semiconductor layer. A storage device comprising: 8. A first gate electrode to which a predetermined voltage is selectively supplied, a first gate insulating film formed on said first gate electrode, and carriers excited by incident light to generate carriers therein. A semiconductor layer that is generated and forms a channel by a voltage supplied to the first gate electrode; and a drain electrode and a source electrode that cause a current to flow through a channel formed in the semiconductor layer according to the supplied voltage. A second gate insulating film formed on the semiconductor layer and the drain electrode and the source electrode, the second gate insulating film forming a trap region for trapping carriers generated in the semiconductor layer at an interface with the semiconductor layer; A predetermined voltage is selectively supplied at a position on the insulating film corresponding to the semiconductor layer, and carriers in the semiconductor layer are selectively supplied according to the supplied voltage. A memory panel in which storage elements each having a second gate electrode trapped in a trap region of the second gate insulating film are arranged in a predetermined arrangement; and a full light emitting means for emitting light to generate carriers in all semiconductor layers. Imaging means for forming an optical image of an imaging target on the memory panel; and an optical image of the imaging object formed by the imaging means on the memory panel in the semiconductor layer. Writing means for supplying, to the second gate electrode, a voltage for trapping one of the holes or electrons in the trapped carriers in the trap region of the second gate insulating film; Reading means for applying a predetermined voltage between the memory elements and sequentially reading, for each storage element, a voltage that changes according to a current flowing through the semiconductor layer. Imaging device according to claim and.