JP2000207892A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a serial read-out operation of data at a high speed and reducing the peak current by amplifying a signal with a sense amplifier operated by an activating signal temporally dispersed, also dividing a sense amplifier into two groups, and amplifying a read-out signal by the other side group while an output signal is outputted serially by one side group. SOLUTION: Even numbered data lines DL0, DL2 and odd numbered data lines DL1, DL3 are connected to a sense amplifier SA through transfer MOSFET (TRMOS) switch-controlled by selecting signals F0, F1. The sense amplifier SA outputs an output signal through a Y gate TG switch-controlled by selecting signals Y0-Y3. And, while a read-out signal amplified by the sense amplifier SA corresponding to the data lines DL0, DL2, is outputted and a sense amplifier SA corresponding to the data lines DL1, DL3 in which read-out output operation is already finished performs take-in of a read-out signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a technology which is effective when used for a high-speed read technology of a batch erase EEPROM (electrically erasable & programmable read only memory). .

[0002]

2. Description of the Related Art An electrically erasable EEPROM is a device that collectively collects all memory cells formed on a chip or collectively collects a group of memory cells among memory cells formed on a chip. This is a non-volatile storage device having a function of erasing information. Such a batch erase type EEPR
Regarding OM, in 1980, IEE, International, Solid-State Circuits Conference (IEEE INTERNATIONAL SOLID-STA)
TE CIRCUITS CONFERENCE) Pages 152-153, 1987, IEE, International, Solid-State Circuits Conference (IEEE IN
(TERNATIONAL SOLID-STATE CIRCUITSCONFERENCE) page 76
~ 77, IEE Journal of Solid State Circuits, Vol. 23, No. 5 (198
8 years) Pages 1157 to 1163 (IEEE, J. Solid-State Cic
uits, vol. 23 (1988) pp. 1157-1163).

FIG. 27 is a schematic diagram showing a cross-sectional structure of a memory cell of an electrically erasable EEPROM which was announced at the International Electron Device Meeting in 1987. The memory cell shown in the figure has a structure very similar to that of a normal EPROM memory cell. That is, a memory cell is an insulated gate field effect transistor (hereinafter, referred to as a MOS) having a two-layer gate structure.
FET or transistor). In the figure, 8 is a P-type silicon substrate, 11 is a P-type diffusion layer formed on the silicon substrate 8, 10 is a low-concentration N-type diffusion layer formed on the silicon substrate 8, 9
Are N-type diffusion layers formed on the P-type diffusion layer 11 and the N-type diffusion layer 10, respectively. 4 is a floating gate formed on the P-type silicon substrate 8 via a thin oxide film 7; 6 is a control gate formed on the floating gate 4 via an oxide film 7;
3 is a drain electrode and 5 is a source electrode. That is,
The memory cell shown in the figure is constituted by an N-channel type MOSFET having a two-layer gate structure, and information is stored in this transistor. Here, the information is substantially held in the transistor as a change in the threshold voltage.

Hereinafter, unless otherwise specified, a case where a transistor for storing information (hereinafter, referred to as a storage transistor) in a memory cell is of an N-channel type will be described. The operation of writing information into the memory cells shown in FIG. 27 is similar to that of the EPROM. That is, the write operation is performed by injecting hot carriers generated near the drain region 9 connected to the drain electrode 3 into the floating gate 4. Due to this write operation, the threshold voltage of the storage transistor as viewed from the control gate 6 becomes higher than that of the storage transistor which has not performed the write operation.

On the other hand, in the erasing operation, a high electric field is generated between the floating gate 4 and the source region 9 connected to the source electrode 5 by grounding the control gate 6 and applying a high voltage to the source electrode 5. Then, the electrons accumulated in the floating gate 4 are drawn out to the source electrode 5 through the source region 9 by utilizing the tunnel phenomenon through the thin oxide film 7. As a result, the stored information is erased. That is, the threshold voltage of the storage transistor as viewed from its control gate 6 is lowered by the erase operation.

In a read operation, a voltage is applied to the drain electrode 3 and the control gate 6 so that weak writing to the memory cell, that is, injection of undesired carriers into the floating gate 4 is not performed. Voltage is limited to relatively low values. For example, a low voltage of about 1 V is applied to the drain electrode 3 and a low voltage of about 5 V is applied to the control gate 6.
By detecting the magnitude of the channel current flowing through the storage transistor based on these applied voltages, “0” and “1” of the information stored in the memory cell are determined.

[0007]

A read operation from a storage transistor as described above requires about one memory cycle.
It is relatively slow, on the order of μs. The inventor of the present application pays attention to the fact that the next address signal can be input while data is output in a device using the storage transistor as described above, and data is serially read out continuously at high speed. I thought that.

An object of the present invention is to provide a semiconductor memory device which realizes a high-speed serial read operation of data and a reduction in peak current. Another object of the present invention is
An object of the present invention is to provide a semiconductor memory device in which the influence of coupling between adjacent data lines is reduced. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the data lines of a memory array in which storage transistors each having a high threshold voltage or a low threshold voltage according to storage information are arranged in a matrix are divided into a plurality of blocks, and time-dependent activation is performed. Signal amplification is performed by a sense amplifier that performs an amplification operation by a signal. Further, a first group of sense amplifiers and a second group of sense amplifiers are divided corresponding to the odd-numbered and even-numbered data lines arranged adjacent to each other, and the output signal of one of the sense amplifier groups is serially output. While the word line is switched, the other sense amplifier group is caused to perform an operation of amplifying a read signal from the memory cell corresponding to the switched word line.

According to the above-described means, since the sense amplifier operates in a time-dispersed manner, the peak current can be reduced, and the read operation of the odd-numbered data lines and the even-numbered data lines is performed alternately. As a result, coupling noise between adjacent data lines can be reduced, and continuous serial reading can be performed at high speed.

[0011]

FIG. 1 is a block diagram showing one embodiment of a batch erase type EEPROM according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, although not particularly limited, the memory array is composed of four memory mats MAT. Each memory mat MAT has a word line WL
Are provided. Since the pitch of the word lines is formed narrow for high integration, the sub-decoder SUB-DCR sandwiched between the memory mats MAT forms a word line selection signal for the memory mats MAT on both sides. Therefore, as exemplarily shown, the word line of the memory mat MAT has two sub-decoders SUB provided therebetween.
Alternately connected to every other DCR.

The main decoder MAN-DCR includes a selection MOSFET for selecting a plurality of memory cells as described later.
And a circuit for forming a selection level and a non-selection level of the sub-decoder SUB-DCR. The gate decoder GDCR is connected to the main decoder MAN-D.
1 in one memory block selected by CR
A selection signal for selecting one memory cell is formed.

Although the storage transistor formed in the memory mat MAT is not particularly limited, both the erasing operation and the writing operation inject and discharge charges to and from the floating gate by a tunnel current. Alternatively, the erase operation may be performed by a tunnel current as shown in FIG.

The sense amplifier SA is not particularly limited, but is divided into two groups as described later, and each of them is controlled in an amplification operation by the sense amplifier control circuit SAC. Although not particularly limited, in the first read cycle, both of the sense amplifiers are activated, and thereafter, in the case of continuous reading with word line switching, the read signal from one sense amplifier group is terminated and the other sense amplifier is terminated. While the serial readout signal is being output from the group, the word line is switched, and the one sense amplifier group starts the amplification operation.

The sense amplifier SA has a latch function. When receiving a read signal required for an amplification operation from a data line, the sense amplifier SA is separated from the data line to amplify and hold the fetched signal. Therefore, the signal selected by Y gate circuit YG is applied to data output buffer OB.
The word line corresponding to the next address can be switched in parallel with the signal output operation as described above.

The status register SREG outputs a signal TS
Thus, status data can be received, and the operation state can be monitored from the outside through the data output buffer OB as necessary. In this embodiment, the continuous access operation and the electrical writing and erasing operations are performed as described above, and it is necessary to know the internal state from the outside during each operation. A register SREG is provided.

A voltage generating circuit VG receives a power supply voltage VCC such as 5 V and a circuit ground potential VSS, and receives a control signal TV.
And functions as a DC-DC converter for forming various voltages Vpw, Vpv, Vew, Ved, Vev and Vr necessary for each operation of writing, reading and erasing.

The address buffer ADB takes in an address signal Ai supplied from an external terminal, and causes the address latch ALH to hold the address signal. Signal T
A is a control signal for latching the address signal, and TSC is an internal serial clock.

The address generation circuit ADG performs an address increment operation by an internal serial clock TSC generated in synchronization with a clock SC supplied from the outside, and activates a sense amplifier SA corresponding to an odd-numbered data line. An address signal Ayo, an address signal Aye for activating the sense amplifier SA corresponding to the even-numbered data line, and a word line switching signal AC are generated. That is, in the semiconductor memory device of this embodiment, only by inputting a designated start address, an address signal for subsequent continuous access is internally generated in response to a clock SC supplied from an external terminal. . The above signals Ayo and Aye
, And AC and / AC are supplied to a sense amplifier control circuit SAC. Here, / attached to the signal AC indicates that the signal is a bar signal, and the signal / AC indicates that the low level is the active level. This is the same for the other signals described below.

The Y gate YG is provided with a Y-system address signal Ay.
Thus, during a read operation, a select signal for one data line is formed, and an amplified signal of the corresponding sense amplifier is selected and transmitted to the data output buffer OB. In a write operation, a select signal for one data line is formed, and a signal corresponding to write data input from the data input buffer IB is transmitted to the data line.

The command decoder CDCR decodes the collide inputted from the data input buffer IB and transmits the command data Di to the control circuit CONT described below. The signal TC is a command decoder control signal, which takes in a command and controls the decoder.

The control circuit CONT receives a chip enable signal / CE, an output enable signal / OE, a write enable signal / WE, a clock SC and a reset signal RS supplied from external terminals, and operates the internal circuit. Form various necessary timing signals. Signal TM
X is a main decoder control signal, which is a signal for switching between positive / negative logic during program-program verify. Signal TXG is a gate decoder control signal.
Signal TV is a power supply circuit control signal. The signal TA is an address buffer control signal, and controls an address latch and the like. The signal TI is a data input buffer control signal, and performs control such as taking in data and commands.

The signal TO is a data output buffer control signal for controlling data output and the like. The signal TC is a common decoder control signal, and controls the capture and decoding of a command. The signal TS is a status register control signal, and performs control such as setting or resetting of the status register SREG. Signal TSA is a sense amplifier control signal, and is used for controlling activation timing. Signal TSC is an internal serial clock. The signal AC is a word line switching signal.

In addition, the signal Ax0 supplied from the address latch ALH to the main decoder MAN-DCR is an X-system address signal indicating the memory block to be selected, and supplied from the address latch ALH to the gate decoder GDCR. The signal Ax1 is an X-system address signal designating one word line in one memory block. The signal Ay supplied to the Y gate YG is a Y-system address signal.

Vpw is a word line voltage at the time of writing.
Vpv is a word line voltage at the time of write verification. V
ev is the word line voltage during erase verify. Vew is a word line voltage at the time of erasing. Ved is the data line voltage at the time of erasing. Vr is a data line precharge voltage.

The signal Oi is output data output from the data output buffer OB, the signal Do is status data, and the signal Di is command data. Also,
The signal RDY / BUSY is a signal for outputting the state of the chip.

FIG. 2 is a schematic circuit diagram showing one embodiment of the memory mat and its peripheral portion. The memory cell is a stacked gate MOS having a control gate and a floating gate similar to those of FIG.
FET. In this embodiment, as will be described later, both the writing operation and the erasing operation are performed using a tunnel current passing through a thin oxide film.

A plurality of the storage MOSFETs are formed as one block, and the drain and the source are shared. Memory M
The common drain of the OSFET is a selection MOSFET.
Connected to data line DL through T. Storage mosfe
The common source of T is supplied with the ground potential of the circuit through the selection MOSFET. The control gate of the storage MOSFET is connected to the word line WL. The selection MOSFET is selected by a selection line extending in parallel with the word line WL. That is, the selected MO
The SFET is regarded as a main word line selected by the main decoder MAN-DCR.

As described above, the memory cells are divided into blocks, each of which is connected to a data line DL via a selection MOSFET.
And a structure for applying a ground potential to a circuit can reduce stress on unselected memory cells. That is, a memory cell in which a word line is selected and a data line is deselected or, conversely, a word line is deselected,
By setting the data line to the non-selected state, the voltage for writing or erasing is prevented from being applied to a memory cell to hold data in a writing or erasing operation. In this configuration, the above-described stress is applied only to a small number of memory cells in the block.

In this embodiment, adjacent data lines DL are divided into odd and even data lines. Then, a short MOSFET is provided corresponding to each. This short MOSFET alternately selects the odd-numbered and even-numbered data lines DL, sets the unselected data lines DL to a fixed level of the circuit ground potential, and sets the mutual coupling between adjacent data lines DL. This is to reduce ring noise. Corresponding to such a configuration of the data line DL, the Y gate YG is also selected for the odd number and the even number for the sense amplifier SA for amplifying the read signal appearing on the data line DL. This Y gate YG is realized by a transfer MOSFET described later.

One of the memory cells in the block selected by the main decoder MAN-DCR is selected by the sub-decoder SUB-DCR. The sub-decoder SUB-DCR selects one word line WL in the block. Such a selection signal for one word line is formed by the gate decoder GDCR. That is, the sub-decoder SUB-DCR receives the word line selection signal formed by the gate decoder GDCR and the selection / non-selection level formed according to the operation mode formed by the main decoder MAN-DCR. , And a drive signal for selecting / non-selecting a word line in the block.

(Table 1)

The storage MOSFET in each of read, write, and erase operation modes.
T gate voltage (word line WL) Vg, drain voltage V
As d and the source voltage Vs, voltages as shown in Table 1 above are given. As described above, the gate voltage Vg and the drain voltage V
d and the relative potential relationship with each voltage Vs,
By generating a tunnel current through a thin gate insulating film and injecting or discharging charges to / from the floating gate, the threshold voltage is changed to perform a write operation and an erase operation. In Table 1, in non-selection, two voltages or states separated by /
It corresponds to the selected block / non-selected block.

FIG. 3 is a circuit diagram of one embodiment for explaining the relationship between the data lines and the sense amplifiers.
In the figure, four data lines DL0 to DL3 and four corresponding sense amplifiers SA are exemplarily shown. The data lines DL0 to DL3 include even-numbered data lines DL0 and DL2 and odd-numbered data lines DL1 and DL2.
It is divided into three. These even-numbered data lines DL0 and DL2 have MOSFE receiving precharge voltage Vr0.
T is provided, and the odd-numbered data lines DL1 and DL3 are provided with MOSFETs for receiving the precharge voltage Vr1. As described above, the pretension for the read operation can be independently performed for each of the even-numbered and odd-numbered data lines.

The even-numbered data lines DL0 and DL2
Is a sense amplifier S via a transfer MOSFET (TRMOS) switch-controlled by a selection signal F0.
A is connected. The odd-numbered data lines DL1 and DL
Reference numeral 3 is connected to the sense amplifier SA via a transfer MOSFET (TRMOS) that is switch-controlled by the selection signal F1. The output signal of the sense amplifier SA is Y controlled by the selection signals Y0 to Y3.
The signal is output via the gate YG. As described above, the data lines of the memory mat or the memory array are divided into odd-numbered and even-numbered data lines, and the read operation of the memory cells can be performed by temporally dispersing the data lines by the selection signals F0 and F1. . Thus, the same memory mat M
The reason why the sense amplifier SA in the AT and the data line DL are not simultaneously activated is as follows.

By activating the sense amplifiers SA in a zigzag manner as an even number and an odd number, signals from memory cells can be alternately taken in and amplified. For example,
As shown by hatching in the figure, even-numbered data lines DL0
While the read signal amplified by the sense amplifier SA corresponding to the data lines DL1 and DL2 is being output, the word lines are switched in the sense amplifiers SA corresponding to the odd-numbered data lines DL1 and DL3 for which the read output operation has already been completed. Then, a read signal from a memory cell to be output next can be fetched.

In the case where the above-described sense amplifier is divided into two parts and is temporally dispersed to perform the amplification operation, the peak current accompanying the amplification operation of the sense amplifier is temporally dispersed. Can be reduced by almost half.

On the memory mat side, read signals do not appear simultaneously from the memory cells in adjacent data lines.
That is, the coupling noise can be substantially eliminated by setting the inactive data line to a fixed level such as the ground potential of the circuit by using the short MOSFET as shown in FIG. 2 to provide a shielding effect. Since the parasitic capacitance between the data lines DL can be neglected by such a reduction in coupling noise, the pitch of the data lines DL can be formed as narrow as possible and the memory array can be highly integrated. Becomes possible.

As described above, the data line in the inactive state is
Instead of providing a short MOSFET and setting it to a fixed level such as the ground potential of the circuit, it may be placed in a floating state. In this case, since the floating data line DL is interposed,
The parasitic capacitance between the activated adjacent data lines DL can be significantly reduced. In addition, a parasitic capacitance exists between the data line DL in a floating state and the ground potential of the circuit, and serves to release a noise component to the ground potential side of the circuit. Noise generated between DLs can be substantially ignored.

FIG. 4 is a circuit diagram of another embodiment for explaining the relationship between data lines and sense amplifiers. In the figure, two adjacent lines DL0, DL1 and DL
MOSFETs receiving the precharge voltages Vr0 and Vr1 are provided separately for the precharge voltages Vr0 and Vr1. In this way, pre-ready for a read operation can be independently performed for every two adjacent data lines.

The two data lines DL divided as described above
0 and DL1 are connected to a sense amplifier SA via a transfer MOSFET (TRMOS) that is switch-controlled by a selection signal F0, and the remaining two data lines DL2 and DL3 are transfer MOSFETs (switch-controlled by a selection signal F1). TRMOS) via the sense amplifier SA. The output signal of the sense amplifier SA is output via a Y gate YG that is switch-controlled by selection signals Y0 to Y3.

This configuration is basically the same as that of the embodiment of FIG. 3, and the method of dividing the data lines is not divided into odd and even staggered patterns as shown in FIG. The difference is that they are divided. With this configuration as well, the peak current due to the activation of the sense amplifier can be reduced to almost half, as in the embodiment of FIG. 3, and continuous access involving switching of word lines can be performed at high speed. Since the coupling between the data lines also occurs only between the two adjacent data lines, the effect of the effective noise can be reduced as compared with the case where the coupling noise is received from the left and right adjacent ones.

FIG. 5 is a circuit diagram of still another embodiment for explaining the relationship between data lines and sense amplifiers. The figure shows an example in which the data lines DL0 to DL3 are divided into four. Precharge voltages are also provided in four ways like Vr0 to Vr3 corresponding to these four divisions, and a pusher charge MOSFET is provided corresponding to each of them. By dividing the data into four in this manner, a pretige for the read operation can be independently provided for each of the data lines DL0 to DL3.

The four data lines D divided as described above
L0 to DL3 are connected to the sense amplifier SA via transfer MOSFETs (TRMOS) that are switch-controlled by the selection signals F0 to F3. The output signal of the sense amplifier SA is output via a Y gate YG that is switch-controlled by selection signals Y0 to Y3.

When divided into four parts as in this embodiment,
The selection signals Y0 to Y4 for the Y gate YG and the selection signals F0 to F3 can be formed by the same address decode signal. With the division of the data line DL into four as described above, the number of sense amplifiers SA operating simultaneously can also be divided into four, so that the peak current accompanying the activation of the sense amplifier can be further reduced. Even when a floating state is supplied without supplying a fixed level to an inactive data line, three data lines are simultaneously activated.
Since the floating data line intervenes, the coupling noise is reduced by the short MOSF.
It can be substantially eliminated without adding ET.

By the way, as shown in FIG.
When the division is not performed, when the precharge operation of the data lines DL0 to DL3, the read operation from the memory cell, and the sense amplifier SA are performed simultaneously, the parasitic capacitance between the data lines DL0 to DL3 causes Changes in the readout signals have mutual influence. In the worst case, the data line DL
When the storage transistor connected to 1 is off and the data line DL1 is to be maintained at the precharge level, when both of the adjacent data lines DL0 and DL1 change to low level, the potential of the data line DL1 is reduced by the coupling. Will drop. Due to this coupling, a level margin with respect to the reference potential is reduced, and in the worst case, a malfunction such that a low level is determined occurs.

When the above-described sense amplifiers SA are simultaneously activated, the peak current flowing through the circuit increases. This peak current flows through the power supply line formed in the semiconductor integrated circuit, and generates noise in the power supply voltage and the ground potential of the circuit due to the distributed resistance there and the inductance component in the bonding wire. The drain voltage of such a storage transistor is set to about IV in order to prevent loss of stored information due to a read operation. As a result, the amplitude of the signal read from the storage transistor to the data line is relatively small, so that the operating margin of the sense amplifier is reduced due to the influence of power supply noise as described above.

The element is miniaturized to increase the storage capacity, and the current flowing through the storage transistor is small, but the large parasitic capacitance is obtained by connecting a large number of storage MOSFETs to one data line. Is done. For this reason, the change in the signal level read from the selected storage transistor to the data line is slow, and when performing a high-speed read operation, it is necessary to activate the sense amplifier SA before the read signal level of the data line becomes sufficiently large. Therefore, the deterioration of the operation margin of the sense amplifier due to the noise cannot be ignored. On the other hand, as in the present application, the data lines in the memory mat are divided, and the sense amplifiers are correspondingly divided, and these are time-dispersed and activated, so that the operation margin of the sense amplifier is reduced. Secure and high-speed reading can be realized. Further, by alternately activating the divided data lines and sense amplifiers, it is possible to perform high-speed continuous access with switching word lines.

FIG. 7 is a basic waveform diagram for explaining the read operation of the internal circuit of the semiconductor memory device according to the present invention. When the chip enable signal / CE changes from the high level to the low level, the address buffer is activated to take in the address signal Ai. Although omitted in the figure, the fetched address signal Ai is held in the address latch circuit.

The word line selection operation and the data line precharge operation are started by the fetched address signal. That is, the selected word line is set to a selection level such as 0 V to Vcc. The precharge voltage Vr is set to a voltage higher than the precharge level of the data line DL, such as about 1 V, by the threshold voltage Vthn of the precharge MOSFET. That is, the precharge MOSF
ET operates as a source follower circuit, and the data line D
L is set to a precharge level such as Vr-Vthn.

When the data line DL is set to the precharge level as described above, the precharge voltage Vr is set to the low level, and the precharge MOSFET is turned off. Storage MOSF for the selected level of word line WL
When the threshold voltage of ET is high, the potential of the data line DL is maintained at a high level (precharge level), and the storage information “0” is read. When the threshold voltage of the storage MOSFET is lower than the selected level of the word line WL, the potential of the data line DL is pulled to a low level, and the storage information "1" is read.

While the parasitic capacitance of the data line DL is relatively large as described above, the storage MO that is turned on
Since the current flowing through the SFET is small, a transfer MOSFET (TRMOS) is set after a lapse of time after the signal amplitude required for the operation of the sense amplifier is obtained.
Is turned on. When the transfer MOSFET is turned on, a read signal is input to the sense amplifier SA, the signal is amplified, and when the data line DL is at the high level (precharge level), the power supply voltage Vcc is applied.
And when the data line DL is at a low level, it is amplified to a low level such as the ground potential of the circuit.

Although not particularly limited, the sense amplifier S
The amplified output of A is held by the latch circuit of the output unit,
One sense amplifier is selected by the Y selection signal, the level is inverted through the data output buffer, the storage information "1" is output as a high level, and the storage information "0" is output as a low level.

FIG. 8 is a waveform chart for explaining an example of the read operation corresponding to the embodiment of FIG.
FIG. 1 shows an example of a continuous read operation accompanied by word line switching.

The word line W is set by the first memory cycle.
When L0 is selected, all data lines DL0-D0
L3 and the like are activated, and accordingly, all sense amplifiers are activated. The details of the operation waveforms so far are the same as those shown in FIG. The dotted line in the figure shows the precharge voltage Vr and the transfer MO
This is an SFET selection signal. The selection signal Y0 is generated to output the data Dout corresponding to the data line DL0, and subsequently the selection signal Y2 is generated to output the data line DL0.
The data Dout corresponding to No. 2 is output.

Subsequently, the word line is switched in parallel with the output of the data Dout corresponding to the odd-numbered data line DL1 in response to the selection signal Y1. That is, the word line WL0 is deselected, and the word line WL1 corresponding to the next address is selected instead. In response to the selection operation of the word line WL1, the precharge operation and the amplification operation of the sense amplifier are performed on the even-numbered data lines DL0 and DL2 for which the read operation has been completed. In response to such switching of the word lines, the transfer MOSFETs of the data lines DL1 and DL3 corresponding to the odd-numbered ones for which the output is performed as described above are turned off. That is, as the output of the data Dout corresponding to the odd-numbered data line DL1, the data held by the sense amplifier SA is output.

The data Dou corresponding to the data line DL1
After the output of the data line t, the selection signal Y3 outputs the data line DL.
The data Dout corresponding to No. 3 is output. Thereafter, the selection signal Y0 is generated again, and the data Dout of the data line DL0 corresponding to the word line WL1 is output.
During this time, the data line D is selected by the operation of selecting the word line WL2.
The signals read to L1 and DL3 are amplified by the sense amplifier. Thereafter, data Dout corresponding to the data lines DL2, DL1 and DL3 are sequentially output in response to the selection signals Y2, Y1 and Y3. If the word line is switched again, the switching is performed at the timing when the output of the data Dout corresponding to the even-numbered data line DL2 is completed.

FIG. 9 is a timing chart of one embodiment of the continuous read operation in the semiconductor memory device according to the present invention. Although not particularly limited, the low level of the chip enable signal / CE and the write enable signal / WE
Are set to low level, a command (COMMAND) is fetched from the input data Ii.
If this command specifies the mode to input one set of start address and end address, / C
The start address STA1 and the end address ED1 are fetched while E remains at a low level or at a low level together with / WE.

Thereafter, the signal / CE is changed to low level,
WE is reset to a high level to supply the clock SC. As a result, the output data Oi is output from the clock S
In synchronization with C, continuous serial data from data D0 corresponding to the start address STA1 to data 7 at the end address EDA1 is obtained.

FIG. 10 is a timing chart of another embodiment of the continuous read operation in the semiconductor memory device according to the present invention. In the same manner as described above, when both the low level of the chip enable signal / CE and the low level of the write enable signal / WE are set to the low level, the command (COMMAND) is fetched from the input data Ii. If this command specifies the mode to input two sets of start address and end address, / CE
Is kept at a low level, or at a low level together with / WE, the first start address STA1, the end address ED1, and the second start address ST
A2 and the end address ED2 are fetched.

Thereafter, the signal / CE is set to low level,
WE is reset to a high level to supply the clock SC. As a result, the output data Oi is output from the clock S
C, the first end address E in order from data D0 corresponding to the first start address STA1.
After serial output by D1, the second start address STA2 to the second end address ED
Output up to 2 serially. In the figure, waveform diagrams of data D0 to D4 corresponding to the first start address STA1 are exemplarily shown.

FIG. 11 is a timing chart showing still another embodiment of the continuous read operation in the semiconductor memory device according to the present invention. Similarly to the above, the low level of the chip enable signal / CE and the write enable signal / W
By setting both E to low level, the input data Ii
, A command (COMMAND) is fetched. With this command, the following three types of serial reading are performed. The start address START is taken in while / CE is kept at a low level or at a low level together with / WE.

In the first mode, serial reading is performed for one word line. That is, the signal /
CE is set to low level, / WE is reset to high level, and clock SC is supplied. As a result, the output data Oi becomes the start address ST of the selected word line.
The data from the ART D0 to the final address of the Y system are sequentially output in synchronization with the clock SC.

In the second mode, serial reading is performed for one block of memory cells. That is, the signal / CE is set to low level, / WE is reset to high level, and the clock SC is supplied. As a result, the output data Oi causes the storage information of the memory cells from the data D0 at the start address START to the last address of the Y system in the last word line in the block to be sequentially output in synchronization with the clock SC. For this reason, if the start address START corresponds to the last word line, it becomes substantially the same as in the first mode.

In the second mode, serial reading is performed as long as the clock SC is continuously supplied. That is, the signal / CE is set to low level, / WE is reset to high level, and the clock SC is supplied. Thus, the output data Oi is read from the data D0 at the start address START until the supply of the clock SC is stopped. In the figure, in each of the above modes, D0 is sequentially set from the start address START.
Waveform diagrams of D9 to D9 are exemplarily shown as representatives.

FIG. 12 is a flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. When it is determined from the command that the mode is the multi-select mode, the even address Ye and the odd address Y
o is reset, it is determined whether the mode is one set shade, and if it is determined that the mode is the one set mode, the X address is set to the start address Xs and the read operation is started.

In this embodiment, since the odd-numbered data and the even-numbered data are alternately output as described above, when the operation shifts to the data output to the even-numbered address, the odd-numbered address is connected to the data line in parallel. Data read, amplification of the sense amplifier and latch operation are performed in parallel, and when the operation shifts to data output to the odd address, data read to the data line and amplification and latch operation of the sense amplifier are performed in parallel with the even address. Are performed in parallel.

The determination of the selector end is to determine whether or not the reading of all the even data lines or the odd data lines in the selected word line is completed. That is, in this embodiment, the memory cells for one word line are divided into odd and even numbers, and each is treated as one sector. Correspondingly, a second-stage Y gate is provided at the subsequent stage of the Y gate YG in FIG. 3 and the like. By switching the second-stage Y gate, other Y gates in the memory mat are provided. Are sequentially read from the even-numbered or odd-numbered data lines.

FIGS. 13 and 14 are flow charts for explaining the operation of the internal circuit corresponding to the operation mode of FIG. If it is determined from the command that the mode is the multi-select mode, and if the mode is determined to be the two-set mode in FIG. 12, as shown in FIG. 13, the X address is set to the first start address Xs1, and the read operation is started.

The X address is the first end address X
When it becomes larger than e1, the second start address Xs2
Is set, the corresponding data line is activated, the sense amplifier is amplified, and the latch operation is performed. When reading is completed up to the odd-numbered last sector, the X address is set to the second start address Xs2. And a second end address Xe2 as shown in FIG.
Up to this point, data is output serially.

FIG. 15, FIG. 16 and FIG.
A flowchart for explaining the operation of the internal circuit corresponding to one operation mode is shown. FIG. 15 is a flowchart showing a part of the first half of the first mode and the second mode. If it is determined that the mode is not the multi-select mode, and if the sector read (first mode) is determined in FIG. 15, the X address is set to the start address Xs1, and the read operation is started. The end of the read operation is determined depending on whether the sector is at the end.
That is, the end is determined when the Y address is the last address.

In FIG. 15, if it is determined that the read operation is the block read (second mode), the X address is set to the start address Xs1, and the read operation is started. In this read operation, when the reading of the odd address in one sector is completed, the operation shifts to the output of the even address as shown in FIG. 16, and at the odd address side, switching of the word line and the corresponding odd data are performed. The activation of the line side, the amplification operation of the sense amplifier, and the data latch are performed in parallel.

In FIG. 16, if the block end address Xe is not accessed due to the output operation on the even-numbered side and the end of the sector, the output shifts to the odd-numbered side shown in FIG. The amplifier performs an amplification operation and a data latch operation. If the end address Xe has been accessed, the block read is terminated.

In FIG. 17, if it is not determined that the read operation is the block read operation (the second mode), the operation automatically switches to the third mode, sets the start address Xs1, and starts the read operation. This read operation is performed until the end of the serial read is instructed by stopping the supply of the clock SC.

FIG. 18 is a block diagram showing a main part of another embodiment of the semiconductor memory device according to the present invention. In this embodiment, a differential amplifier is used as the sense amplifier SA. Although not particularly limited, the differential sense amplifier SA includes a pair of CMs as used in a dynamic RAM (random access memory).
A power switch MOSFET composed of a P-channel MOSFET and an N-channel MOSFET in a latch configuration by cross-connecting an input and an output of an OS inverter circuit.
The activation of the operation is performed via.

In this embodiment, a pair of memory mats is arranged above and below the sense amplifier SA. The sense amplifiers SA are divided into those for even-numbered (EVEN) data lines and those for odd-numbered (ODD) data lines. Although the sense amplifiers SA are drawn so as to be arranged vertically for even numbers and for odd numbers in the same figure, they may be arranged in a straight line in practice.

A pair of inputs of the even-numbered sense amplifier are
It is connected to the even-numbered data lines of the upper and lower memory mats. A pair of inputs of the odd-numbered sense amplifier are connected to odd-numbered data lines of the upper and lower memory mats. Sub-decoder S provided corresponding to memory mat
The UB-DCR, main decoder MAN-DCR, and gate decoder GDCR (not shown) are the same as those in FIG.

The sense amplifier control circuit SAC generates sense amplifier activation signals / D0 and D0 for even numbers and sense amplifier activation signals / D1 and D1 for odd numbers. The signal / D0 is supplied to the gate of a P-channel MOSFET for supplying a power supply voltage to the even-numbered sense amplifier SA, and the signal D0 is supplied to the N-channel MOSFET for supplying a circuit ground potential to the even-numbered sense amplifier SA. Supplied to the gate. Similarly, the signal / D1 is a P-channel MOSF that supplies a power supply voltage to the odd-numbered sense amplifier SA.
The signal D1 is supplied to the gate of the ET, and the signal D1 is supplied to the gate of an N-channel MOSFET that supplies the ground potential of the circuit to the odd-numbered sense amplifier SA. The address buffer, input / output buffer, control circuit, voltage generation circuit, etc.
Since it is the same as the embodiment of FIG. 1, it is omitted in FIG.

FIG. 19 is a circuit diagram of one embodiment for explaining the relationship between the data lines and the differential sense amplifier. The figure shows four data lines DL0 to DL of two memory mats arranged with a sense amplifier SA interposed therebetween.
L3 and four sense amplifiers SA corresponding thereto are exemplarily shown as representatives.

The sense amplifier SA is composed of a pair of CMOS inverter circuits whose inputs and outputs are cross-connected as shown in a circuit diagram in a portion surrounded by a dotted line. As described above, a power supply switch MOSFET is provided in the latch circuit including the CMOS inverter circuit.
Since the activation is performed by a so-called deca MOS, the operation is substantially the same as that of the clocked inverter circuit. Therefore, in the figure, the two CMOS inverter circuits are shown in the form of a clocked inverter circuit.

A MOSFET Q1 for setting an input node to 0 V is provided at a pair of inputs of the sense amplifier. Thus, the input signal is set to 0 V before starting the amplification operation. A pair of inputs of the sense amplifier SA is connected to data lines DL0 to DL3 via a transfer MOSFET (TRMOS). The transfer MOSFET is divided into two corresponding to the even-numbered data lines DL0 and DL2 and the odd-numbered data lines DL1 and DL2, and supplied with selection signals F0 and F1, respectively. Correspondingly, a precharge voltage Vr0 is supplied to the gates of the precharge MOSFETs provided on the even data lines DL0 and DL2, and a precharge voltage is supplied to the gates of the precharge MOSFETs provided on the odd data lines DL1 and DL3. The voltage Vr1 is supplied.

A pair of inputs of the sense amplifier SA are
Switch MOSFEs each constituting a Y gate YG
T is provided, and selection signals Y0 to Y
3 are supplied. This configuration is the same as in FIG.
The output of the Y gate YG is shared and the second stage Y
It is connected to an input / output data line led to a data input buffer and a data output buffer via a switch MOSFET forming a gate.

In this embodiment, when one of the pair of memory mats is activated, the other is inactivated. The memory mat to be deactivated has the above-mentioned transfer MOS even though it is deactivated.
The FET is turned on, and the corresponding data line is connected to the input of the sense amplifier. Then, on the inactive memory mat side, the precharge voltage Vr is reduced to the normal precharge voltage, and the potential of the data line becomes an intermediate potential between the high level and the low level of the data line of the activated memory mat. It is set as follows. As a result, the data line of the inactive memory mat is used to form the reference voltage (Ref. DL) of the sense amplifier.

In this embodiment, the sense amplifier SA is CM
Corresponding to the configuration by the OS latch circuit, at the time of a write operation, each latch is held with write data. That is, after the Y gates YG are sequentially opened to set write data, the transfer MOSFETs for the even number and the odd number are simultaneously turned on to perform the write operation at the same time. In response to such a write operation, the operating voltage of the sense amplifier is switched to a voltage such as 4V. On the other hand, at the time of read operation and write verify, even and odd data lines are alternately activated in a staggered manner except for the first memory cycle, as in the embodiment of FIG.

FIG. 20 is a circuit diagram of another embodiment for explaining the relationship between the data lines and the differential sense amplifier. In this embodiment, an automatic writing function is added to the embodiment of FIG.

FIG. 21 is a waveform chart for explaining an example of the operation of the circuit of the embodiment shown in FIG. FIG.
FIG. 1A shows a waveform diagram of the write operation (Program) and the write verify operation (Program Verify). The above-described automatic writing function will be described with reference to this waveform diagram. In the write operation, the write data T
Data is input through the Y gate. At this time, the sense amplifier is activated with the deca MOS turned on and holds the write data. Signal PW
0 turns the MOSFET on. When the write data T Data is low level, the MOSFET of the automatic write circuit receiving the write data T Data is in the off state, so that the potential of the data line DL1 is kept at the low level. And charged up by the power supply voltage Vcc through the MOSFET turned on by the signal PW0.

Next, the signal TS0 is raised to Vcc or higher. As a result, the transfer MOSFET is turned on, and the potential of the data line DL1 is increased to about 4 V required for the write operation. Although not shown in the figure, since the word line is set to a voltage such as -10 V, a high voltage toward the drain is applied between the floating gate and the drain, and the voltage is applied from the floating gate to the drain. A write operation in which a tunnel current flows is performed.

Upon completion of the write operation as described above, the signal PW0 is set to low level, the set MOSFET is turned on, the potential of the data line DL1 is set to low level, and the operation shifts to write verify. That is,
The signal RR0 is set to the precharge voltage Vr and the data line D
L1 is precharged. On the other hand, since the signal PR1 on the non-selected memory mat side is set to the potential corresponding to the reference voltage as described above, the potential of the data line DL1 on the non-selected memory mat side is set to the reference voltage Ref. DL.

The deca MOSFET is turned off, and the sense amplifier is temporarily deactivated. If the threshold voltage of the storage MOSFET in which the writing is performed is lowered, the potential of the data line DL1 is lowered to a low level (OK Data). If the writing is insufficient and the threshold voltage is still high, the potential of the data line DL1 is high. NG Dat
a) Left as is. The transfer MOSFET is turned on by the signals TS0 and TS1, the read data is supplied to the input of the sense amplifier with the reference voltage Ref.DL, and the deca MOSFET is turned on and activated.

If the result of the verification is insufficient as described above, the write operation is performed again, and the write operation is repeatedly performed up to a predetermined number of times until the low-level signal is obtained. If it is determined that the writing is insufficient even after reaching the certain number of times, the memory cell is determined to be defective and switched to the redundant circuit as necessary.

FIG. 21B is a waveform chart for explaining the read operation. By the end of the previous read operation, the deca-MOSFET is turned off. The potential of the data line DL is set to low level by the set MOSFET. Then, the drain-side select MOSFET of the memory cell divided into the blocks is turned on. Then, the precharge voltages PR0 and PR1 set the pair of data lines to the precharge voltage and the reference voltage according to the selection / non-selection of each memory mat. Thereafter, the select MOSFETs on each side of the memory cells divided into the above blocks are turned on, and the potential of the data line on the selected memory mat side is changed to the selected storage MO.
If the SFET is off, it is kept at the precharge level; if it is on, it is pulled low by the memory current.

The signals TS0 and TS1 are set to the high level, the transfer MOSFET is turned on, and the pair of data lines is connected to the input of the sense amplifier. Then, the set MOSFET is turned off, and the
The FET is turned on, the sense amplifier is activated, and the read signal is amplified.

In the embodiment of FIG. 20, the MOSFET receiving the input voltage of the sense amplifier is provided as an all "1" detection circuit. That is, a MOSFET provided at the input of another similar sense amplifier and a wired-OR logic are employed, and when all the read data lines are at a low level, all the MOSFETs are turned off and a high-level detection signal is output. Obtainable. If the input of any one of the sense amplifiers is high level, MOS
Since the FET is turned on to generate a low-level detection signal, "1" of all signals can be detected when all MOSFETs are off. That is, in the figure, the data line on the left side of the sense amplifier is in the erased state when reading from the memory cell is "1".

On the other hand, in a configuration in which the output of the sense amplifier is output by a circuit similar to the left circuit, the logic levels of writing and erasing are reversed in the data line provided on the right. That is, the memory cell provided on the data line on the right side of the differential sense amplifier is brought into the erased state with a low level output, but when viewed from the external terminal, it is determined that the memory cell is in the erased state when all are "0". .

FIG. 22 is a circuit diagram of still another embodiment for explaining the relationship between the data lines and the differential sense amplifier. In this embodiment, the precharge M
OSFET is omitted. In other words, the precharge MOSFE is made to have a read precharge function in combination with the write signals PW0 and PW1.
T is to be reduced.

FIG. 23 is a waveform chart for explaining an example of the operation. FIG. 3A shows a write operation and a verify operation, and FIG. 3B shows a read operation. As shown in the figure, the signal PW is used also in the write operation, the verify operation, and the read operation, and the voltage level is changed according to each operation mode. That is, the signals PW and PR in FIG. 21 are realized by one signal PW.

The precharge MOSFET is provided corresponding to each data line. In a semiconductor memory device having a large storage capacity such as about 32 Mbits, the number of data lines is 4096, for example. Book or 81
Since a large number such as 92 are provided, the number of precharge MOSFETs to be deleted also increases correspondingly.

FIG. 24 is a block diagram showing another embodiment of the read system circuit of the semiconductor memory device according to the present invention. In this embodiment, a main amplifier (Main Amp) is provided after the sense amplifier. A data latch (Data Latch) is provided downstream of the main amplifier, and read data is output through the data latch through a data output buffer (Dout Buffer).

Although not particularly limited, in this embodiment, the sense amplifier SA is divided into three, and the main amplifier amplifies data Data1 from the first sense amplifier by the first pulse 1 of the clock SC. When the clock SC is at the low level 1L, the data latch latches the data Data1 amplified by the main amplifier. With the second pulse 2 of the clock SC, the main amplifier amplifies the data Data2 from the second sense amplifier. In parallel with this, the data output buffer outputs the data Data1 captured by the data latch. When the clock SC is at the low level 2L, the data latch latches the data Data2 amplified by the main amplifier.

Then, the third pulse 3 of the clock SC
Accordingly, the main amplifier amplifies the data Data3 from the third sense amplifier. In parallel with this, the data output buffer stores the data Data2 captured by the data latch.
Output. When the clock SC is at the low level 3L, and when the next clock SC (not shown) is at the high level, the data output buffer outputs the data Data3 captured by the data latch.
Data can be output at high speed by such a pipelined serial operation. In this embodiment, the data latch may be omitted, and the output of the main amplifier may be supplied to the data output buffer.

FIG. 25 is a circuit diagram of still another embodiment for describing the relationship between the data lines and the sense amplifiers. In this embodiment, two data lines are allocated to the sense amplifier. That is, for the four sense amplifiers described above, eight data lines DL in total are used.
0 to DL7 are assigned two by two. The column selection function is provided for the selection signals F00, F01 and F10, F11. By the combination of the signals F00 to F11, the data line D is switched without switching the word line.
The signals L0 to DL7 can be output continuously. Although omitted in the figure, the precharge MOSFETs provided on the data lines DL0 to DL7 corresponding to such transfer MOSFETs are also divided into four.
Precharge voltages Vr0 to Vr3 are supplied to each of them.

For example, in the continuous read operation, the signal F
When four data lines are read by 00 and F10, four data lines are subsequently read by F01 and F11. F00, F10 and F01
After the data lines for eight lines have been read by the FF11 and the FF11, the word lines are switched. In this configuration,
The number of sense amplifiers can be reduced to half the number of data lines.

FIG. 26 is a block diagram showing one embodiment of an information processing system such as a microcomputer using the semiconductor memory device according to the present invention. The flash memory shown in the figure is constituted by the semiconductor memory device as in the above embodiment.

The system of this embodiment includes a central processing unit (or microprocessor) CPU, an add decoder,
It includes a timing controller, a data buffer, a data register, a relay and a flash memory as described above. Although one flash memory is exemplarily shown as a representative, a plurality of flash memories are connected in parallel to obtain a desired storage capacity. Note that a memory RAM, a ROM, and an input / output device required to configure a system such as a microcomputer are omitted because they are not directly related to the present invention.

The SC pin of the flash memory is a serial clock input terminal. Data is serially output in synchronization with the clock SC input from this input terminal. Although the serial clock SC is generated by the timing controller, the serial clock SC may directly input the system clock of the CPU.

In the serial read from the flash memory, data is output from the I / O pin while the internal address is incremented by synchronizing with the SC when / CE and / OE are at the low level. At this time, the address bus is set free. When an output is obtained from a second flash memory or the like (not shown) at the time of serial output from the first flash memory, the signal / OE may be separated so that data does not conflict with the data bus.

The functions and effects obtained from the above embodiment are as follows. (1) A data line of a memory array in which storage transistors having a high threshold voltage or a low threshold voltage according to storage information are arranged in a matrix is divided into a plurality of blocks, and the data lines are temporally dispersed and amplified. By performing signal amplification by the sense amplifier that performs the operation, it is possible to reduce the peak current and thereby increase the operation merge.

(2) A first group of sense amplifiers and a second group of sense amplifiers are divided corresponding to the odd-numbered and even-numbered data lines arranged adjacent to each other, and the output signal of one of the sense amplifier groups is serialized. While the word lines are switched, and the other sense amplifier group performs the operation of amplifying the read signal from the memory cell corresponding to the switched word line, whereby the odd-numbered and even-numbered By alternately performing the read operation of the data line, coupling noise between adjacent data lines can be reduced, and an effect that serial readout at high speed can be performed is obtained.

(3) Addresses for reading from the odd-numbered and even-numbered data lines and for switching word lines are formed by an address generation circuit that is incremented in synchronization with a clock supplied from an external terminal. By doing so, an effect that a large amount of data can be read at high speed and easily can be obtained.

(4) A data line is connected to a common drain of a storage MOSFET having a stacked gate structure composed of a plurality of transistors via a first selection MOSFET, and a second source is connected to a common source of the storage MOSFET. Select MO
By connecting to the ground potential via the SFET, an effect is obtained that the stress at the time of writing / erasing to the unselected storage MOSFET can be greatly reduced.

(5) The memory array is composed of a pair of memory mats, and the data lines of each memory mat are input to a differential sense amplifier, and the data line potential of the unselected memory mat is used as a reference voltage for the selected memory mat. By performing the sensing of the data line potential, an effect that a high-sensitivity and high-speed sense amplifier can be obtained is obtained.

(6) The sense amplifier is provided with a MOSFET for receiving the amplified signal, and is connected in a wired-OR manner. With this simple configuration, it is possible to obtain an effect that a detection signal of an erased state of all data lines can be obtained. Can be

(7) The sense amplifier uses a CMOS latch circuit to input and hold write data, and performs simultaneous write operations on memory cells corresponding to a plurality of data lines based on the held data. By doing so, the effect of increasing the speed of the write operation can be obtained.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, the differential sense amplifier may use a differential MOSFET as an amplifying MOSFET as used in a static RAM. Storage MOSFET
Is, in addition to the above-mentioned flash type EEPROM,
It may constitute an EPROM or a mask ROM.

The present invention can be widely applied to a semiconductor memory device having a high threshold voltage or a low threshold voltage according to stored information. This semiconductor memory device has 1
It may be built in a digital integrated circuit such as a chip microcomputer.

[0117]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the data lines of a memory array in which storage transistors each having a high threshold voltage or a low threshold voltage according to storage information are arranged in a matrix are divided into a plurality of blocks, and time-dependent activation is performed. Signal amplification is performed by a sense amplifier that performs an amplification operation by a signal. Then, a first group of sense amplifiers and a second group of sense amplifiers are divided corresponding to the odd-numbered and even-numbered data lines arranged adjacent to each other, and the output signal of one of the sense amplifier groups is serially output. During this period, the word line is switched and the other sense amplifier group is caused to perform the operation of amplifying the read signal from the memory cell corresponding to the switched word line, thereby reducing the peak current and the odd and even numbers. By alternately performing the read operation of the second data line, coupling noise between adjacent data lines can be reduced and continuous high-speed serial read can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a batch erase type EEPROM according to the present invention.

FIG. 2 is a schematic circuit diagram showing an embodiment of the memory mat and peripheral portions thereof.

FIG. 3 is a circuit diagram showing one embodiment for describing a relationship between a data line and a sense amplifier of the semiconductor memory device according to the present invention.

FIG. 4 is a circuit diagram showing another embodiment for describing a relationship between a data line and a sense amplifier of the semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram showing still another embodiment for describing a relationship between a data line and a sense amplifier of the semiconductor memory device according to the present invention.

FIG. 6 is a circuit diagram showing an example of a data line and a sense amplifier studied prior to the present invention.

FIG. 7 is a basic waveform diagram for describing a read operation of an internal circuit of a semiconductor memory device according to the present invention.

FIG. 8 is a waveform chart for explaining an example of a read operation corresponding to the embodiment of FIG. 3;

FIG. 9 is a timing chart showing one embodiment of a continuous read operation in the semiconductor memory device according to the present invention.

FIG. 10 is a timing chart showing another embodiment of the continuous read operation in the semiconductor memory device according to the present invention.

FIG. 11 is a timing chart showing still another embodiment of the continuous read operation in the semiconductor memory device according to the present invention.

FIG. 12 is a flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. 9;

FIG. 13 is a partial flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. 10;

FIG. 14 is a flowchart of the remaining part for describing the operation of the internal circuit corresponding to the operation mode of FIG. 10;

FIG. 15 is a partial flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. 11;

FIG. 16 is another partial flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. 11;

FIG. 17 is a remaining part flowchart for explaining the operation of the internal circuit corresponding to the operation mode of FIG. 11;

FIG. 18 is a main part block diagram showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 19 is a circuit diagram showing one embodiment for explaining a relationship between a data line and a differential sense amplifier in the semiconductor memory device according to the present invention.

FIG. 20 is a circuit diagram showing another embodiment for describing a relationship between a data line and the differential sense amplifier in the semiconductor memory device according to the present invention.

FIG. 21 is a waveform chart for explaining an example of the operation of the embodiment circuit of FIG. 20;

FIG. 22 is a circuit diagram showing still another embodiment for describing the relationship between the data lines and the differential sense amplifier in the semiconductor memory device according to the present invention.

FIG. 23 is a waveform chart for explaining an example of the operation of the embodiment circuit of FIG. 22;

FIG. 24 is a configuration diagram showing another embodiment of the readout circuit of the semiconductor memory device according to the present invention.

FIG. 25 is a circuit diagram showing still another embodiment for describing a relationship between a data line and a sense amplifier in the semiconductor memory device according to the present invention.

FIG. 26 is a block diagram showing one embodiment of an information processing system such as a microcomputer using the semiconductor storage device according to the present invention.

FIG. 27 is a schematic sectional view showing an example of a conventional memory cell.

[Explanation of symbols]

MAT: memory mat, SUB-DCR: sub decoder, MAN-DCR: main decoder, GDCR: gate decoder, CONT: control circuit, ADB: address buffer, ALH: address latch, ADG: address generation circuit, VG: voltage generation circuit , CDCR: command decoder, SREG: status register, ASC: sense amplifier control circuit, SA: sense amplifier, YG: Y gate, IB: data input buffer, OB: data output buffer, DL: data line, WL: word line, CPU: Central processing unit.

Claims (8)

[Claims] A plurality of word lines; a plurality of data lines; a plurality of memory cells; a clock terminal; an address generator and a data terminal; A semiconductor region, a floating gate and a control gate, wherein the control gate is coupled to one word line of the plurality of word lines, and the first semiconductor region of each memory cell is An external clock signal is supplied to the clock terminal, the address generator outputs a word line switching signal in synchronization with the external clock signal, and the data terminal is connected to the data terminal. Outputting data stored in a memory cell coupled to a selected word line, while the external clock signal is supplied to the clock terminal; A word line is selected from the plurality of word lines according to the word line switching signal, and data stored in a memory cell coupled to the selected word line is output from the data terminal. Semiconductor storage device. 2. The method according to claim 1, wherein when a predetermined command is supplied from the data terminal,
A semiconductor memory device, wherein each of data stored in the plurality of memory cells is output from the data terminal while an external clock signal is supplied to the clock terminal. 3. The semiconductor memory device according to claim 2, further comprising an address latch for latching a start address signal. 4. The semiconductor memory device according to claim 3, wherein said address generator performs an address increment operation with a start address stored in said address latch in synchronization with said external clock signal. 5. A semiconductor device comprising a plurality of word lines, a plurality of main data lines, a plurality of sub data lines, a plurality of source lines, a plurality of memory cells, a clock terminal, an address generator and a data terminal. Each of the memory cells has first and second semiconductor regions, a floating gate and a control gate, and the control gate is coupled to one of the plurality of word lines, and The first semiconductor region of the memory cell is coupled to one of the plurality of sub data lines, and the sub data lines are respectively coupled to one main data line on the same column; A second semiconductor region of the upper memory cell is coupled to one of the plurality of source lines; an external clock signal is supplied to the clock terminal; The address generator outputs a word line switching signal in synchronization with the external clock signal, the data terminal outputs data stored in a memory cell coupled to a selected word line, and the clock terminal A word line is selected from the plurality of word lines in response to the word line switching signal while the external clock signal is being supplied to the memory cell coupled to the selected word line; Data is output from the data terminal. 6. The method according to claim 5, wherein when a predetermined command is supplied from the data terminal,
A semiconductor memory device, wherein each of data stored in the plurality of memory cells is output from the data terminal while the external clock signal is supplied to the clock terminal. 7. The semiconductor memory device according to claim 6, further comprising an address latch for latching a start address signal. 8. The semiconductor memory device according to claim 7, wherein said address generator performs an address increment operation with a start address stored in said address latch in synchronization with said external clock signal.