JP2000206208A - Semiconductor integrated circuit device and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device which can precisely execute the test of a digital circuit by using a control terminal for performing power saving operation of an analog circuit, in a digital analog hybrid integrated circuit, and a testing method of the semiconductor integrated circuit device. SOLUTION: In this semiconductor integrated circuit device, a control terminal 12 for performing power saving operation of an analog circuit, and a selector circuit 7 which switches a signal for test in order to input it in a digital circuit when the analog circuit performs the power saving operation by the control terminal 12 are arranged. As a result, the test of the digital circuit can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a test method therefor, and more particularly to a semiconductor integrated circuit device capable of easily testing a digital / analog mixed circuit and a test method therefor.

[0002]

2. Description of the Related Art When testing a digital / analog mixed IC at the time of shipment, a test mode is often set and a mechanism for directly inputting a signal to a digital (logic) unit is provided. For this purpose, it is necessary to provide a dedicated switching terminal and a dedicated digital signal input terminal. However, in many cases, such a terminal cannot actually be provided. As a solution to this, a measure is proposed in which a terminal for performing a power saving operation of the IC is also used as the test mode setting terminal.

[0003] In the actual operation of most ICs, signal processing is possible, but there is a case where a signal to be processed is not input. This is generally called a standby state. In particular, when an IC equipped with an analog circuit has a circuit configuration in which a bias current always flows when there is no signal, loss is extremely large in terms of energy consumption.

[0004] For this reason, when there is no input signal, it is often the case that the amount of the no-signal bias current is reduced or cut. For this control, a special circuit may be built in the IC to perform self-control, but it is much easier to provide a dedicated terminal for controlling the bias current. Therefore, an example in which a dedicated terminal is provided in an actual product is often seen.

[0005] It is considered that the bias current control terminal is used together to realize a test mode. The target block is usually a logic circuit that is often located next to the analog circuit. Also, this logic circuit is CMO
In many cases, the S configuration is used. In the case of CMOS, it is not necessary to flow a bias current when there is no signal. For this reason, if the logic circuit can be directly tested by switching the bias current control terminal, there is no need to provide a dedicated terminal for the test mode setting.

FIG. 10 shows a digital / analog mixed I
9 is an example of a circuit configuration of C. 1 is an amplifier circuit for amplifying an input signal, 2 is a waveform generated by the amplifier circuit 1,
A comparison circuit (comparator) 3 for converting a rectangular wave represented by "L" or "H" into a buffer circuit for receiving the output of the comparator 2 and ensuring current supply capability to the next stage and an output terminal; Is a logic circuit that receives the output of the buffer circuit 3 and performs signal processing.

Reference numeral 5 denotes a reference voltage generation circuit,
The reference voltage is supplied to the comparator 2 and the comparator 2. Reference numeral 6 denotes an oscillation circuit which generates and supplies a reference clock for operating the logic circuit 4. Reference numeral 7 denotes a selector circuit for selecting whether to input a signal in actual operation or a signal for a logic test to the logic circuit 4.

[0008] Also, 8, 9, 10, 11, 12, 20,
Reference numeral 21 denotes an I / O terminal of the semiconductor integrated circuit. 8 is an analog signal input terminal, 9 is a logic output terminal, 10 and 1
Reference numeral 1 denotes a logic mode switching terminal to which a DC level voltage of "L" or "H" is input in actual operation. For example, the terminal may be considered as a terminal for switching the count number of the counter, switching the polarity of the output signal, and the like. Reference numeral 12 denotes a terminal for switching between a power save mode and an operation mode of the analog circuit. If no signal is input,
Cuts bias current of analog circuit and saves power. Reference numeral 20 denotes a terminal for supplying a test signal to the logic circuit. Reference numeral 21 denotes a terminal for switching between the test mode and the actual machine mode.

Next, the operation will be described. In the case of the actual mode, an analog signal (regardless of the form of the signal) is input from the terminal 8 as shown in the waveform of FIG. 13, and is amplified by the amplifier circuit 1 at a preset rate. Send to 2. It should be noted that the phase of the amplified signal is inverted because it is an inverting amplifier. The transmitted signal is compared with the voltage generated by the reference voltage circuit 5 in the comparator circuit 2, and if the signal is smaller, the same level as the power supply voltage (hereinafter referred to as “H” level) is output. ,
If it is larger, it outputs the same level as the ground voltage (hereinafter referred to as “L” level).

The signal output from the comparator circuit 2 is first input to the buffer 3 and then to the logic circuit 4 in order to ensure the driving capability, and after being subjected to signal processing, is output from the terminal 9 ( See the waveform shown in FIG. 13).

In the test mode, the selector 7 is controlled by the terminal 21 so that a logic signal can be directly input from the terminal 20. Terminal 12 in power save mode
The bias current of the amplifier circuit 1 and the reference voltage generating circuit 5 is cut to suppress the power consumption when there is no signal.

The operation will be described with reference to FIGS. FIG. 11 shows an example of the amplifier circuit 1 and FIG. 12 shows an example of the reference voltage generating circuit 5. The common point is that the bias current is controlled. When a voltage of the power supply voltage level is input to the gate of the N-channel MOS: Q9, the P-channel MOS: Q3
Transistor size, R1 resistance, N-channel M
OS: A bias current I3 determined by Q9 flows. The P-channel MOSs Q1 and Q2 form a current mirror circuit with the P-channel MOS Q3, and the bias currents I1 and I2 corresponding to the transistor sizes are formed.
2 flows and the circuit becomes operable.

When a ground level voltage is input to the gate of N-channel MOS: Q9,
9 is turned off, and the bias current I3 stops flowing. Therefore, the currents I1 and I2 generated by the current mirror circuit do not flow similarly, and the mode becomes a mode in which the circuit does not operate. In the case of the above block configuration, the mode switching terminal 21
In fact, there is no room to provide an extra signal input terminal 20 for logic circuit test.

[0014]

An object of the present invention is to provide a semiconductor integrated circuit device and a test method thereof capable of accurately executing a digital circuit test using a control terminal for performing a power saving operation of an analog circuit. It is assumed that.

[0015]

According to a first aspect of the present invention, in a semiconductor integrated circuit device, there is provided a digital / analog mixed integrated circuit in which a digital circuit and an analog circuit for supplying a signal to the digital circuit are mixed. A control terminal for performing a save operation; and a switch for switching a test signal to a digital circuit when the analog circuit is performing a power save operation by the control terminal. This is a test.

In a semiconductor integrated circuit device according to a second aspect of the present invention, in a digital / analog hybrid integrated circuit in which a digital circuit and an analog circuit having a comparison circuit and supplying a signal to the digital circuit are mixed, an input signal is amplified. An amplification circuit to be applied to the comparison circuit, a buffer for receiving an output of the output of the comparison circuit, and a control terminal for controlling a bias current of the analog circuit to perform a power save operation. When the power saving operation is performed by the control terminal, the buffer is configured to have a high impedance,
A connection signal of an external resistor connected to the comparison circuit is switched to input a test signal from the test signal terminal to the digital circuit.

According to a third aspect of the present invention, there is provided a test method for a semiconductor integrated circuit device, wherein the power saving operation of the analog circuit in the digital / analog mixed integrated circuit is performed by an input from a control terminal. When the analog circuit is performing a power saving operation by the control terminal when performing the test, a test signal can be input to the digital circuit.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 If a power save function for reducing power consumption is provided during standby, the standby state is used for a logic test. That is, both the standby state and the test mode are used. FIG. 1 shows a schematic flowchart up to the logic test.

In FIG. 1, in step S1, the analog circuit in the digital / analog mixed integrated circuit is set to the power save state, and the test mode is set. Step S
In step 2, a logic test of the digital circuit in the digital / analog mixed integrated circuit is performed. Step S3
Then, it is verified whether or not the logic test of the digital circuit has been performed under all the conditions, and if it is satisfied, the operation is terminated.

FIG. 2 shows an example of a circuit proposed so that a logic test can be performed based on the flowchart shown in FIG. In FIG. 2, reference numeral 1 denotes an amplifier circuit for amplifying an input signal, and 2 denotes a waveform generated by the amplifier circuit 1.
A comparison circuit (comparator) 3 for converting into a rectangular wave represented by “L” or “H” receives the output of the comparator 2 and is a buffer circuit for securing a current supply capability to the next stage and an output terminal. . These amplifier circuit 1, comparison circuit 2 and buffer 3 are configured as analog circuits. Reference numeral 4 denotes a digital circuit as a logic circuit that receives an output of the buffer circuit 3 and performs signal processing.

Reference numeral 5 denotes a reference voltage generating circuit,
The reference voltage is supplied to the comparator 2 and the comparator 2. Reference numeral 6 denotes an oscillation circuit which generates and supplies a reference clock for operating the logic circuit 4. Numeral 7 is a mode switching means for switching the logic circuit 4 between a real mode and a test mode by selecting a selector circuit for selecting whether to input a signal for actual operation or a signal for logic test. Reference numerals 8 to 14 represent I / O terminals of the semiconductor integrated circuit. Reference numeral 8 denotes an analog signal input terminal, 9 denotes a logic output terminal, and 10 and 11 denote switching terminals for supplying a logic mode switching signal. In an actual operation, a DC level voltage of "L" or "H" is input. Is done. This may be considered as a terminal for performing an operation of switching the count number of the counter, an operation of switching the polarity of the output signal, and the like.

Reference numeral 12 denotes a control terminal for switching between a power save mode and an operation mode of the analog circuit. When a ground level voltage is input to the control terminal 12, the bias current of the analog circuit is cut off, and a power save operation is performed.

The circuits newly added in the first embodiment are a D-type flip-flop 13 and an AND circuit 14. Further, a control terminal 12 for controlling a bias current is connected to a control terminal of the selector circuit 7. For this reason, when the bias current is turned off and the analog circuit enters the power saving state, the selector circuit 7 selects the B side, so that a logic circuit test signal can be input from the terminal 10.

As described above, the selector circuit 7 selects whether to input a signal in actual operation to the logic circuit 4 or to input a signal for a logic test.
When the analog circuit is performing the power saving operation by the control terminal 12, a switching means for switching so that a test signal can be input to the digital circuit. And
The D-type flip-flop 13 and the AND circuit 14 apply the “H” level or “L” level voltage signal applied to the digital circuit as the logic circuit 4 according to the signal state of the control terminal 12 during the test mode period to the test mode. Test voltage signal applying means for maintaining a hold state during the period is configured.

FIG. 3 shows a time chart up to the execution of the logic test in the circuit example of FIG. It is assumed that the state of this logic circuit can take four states for convenience of explanation. This is based on the fact that four combinations are possible with two terminals 10 and 11.

First, in a period 1, a state is set during a logic test in the actual machine mode. "H" from terminal 10
Are input to the D-latch circuit 13,
Triggered by the rising edge of the pulse output from the D circuit 14, the signal is output from the Q terminal of the D latch circuit 13. This output signal is held during period 2. An “L” DC level is input from the terminal 11, and is kept as it is during the period 2. These terminals 10 and 11
After setting, the bias control terminal 12 is set to “L”.
Then, the logic test 1 is executed in the period 2.

Next, in the period 3, the mode is returned to the actual machine mode, and the state is set during the logic test in the period 4. The DC level of “H” is input from the terminal 10 and the D latch circuit 13
Is triggered by the rising edge of the pulse output from the AND circuit 14 and is output from the Q terminal of the D latch circuit 13. This output signal is held during period 4. The DC level of “L” is input from the terminal 11 and is kept as it is during the period 4. This terminal 1
After setting by 0 and 11, the bias control terminal 12
Is set to “L”, and the logic test 2 is executed in the period 4. The same operation is performed up to the logic test 4 in the period 8.

As shown in FIG. 4, for example, after the IC is mounted on a system, the power of the IC may be saved in actual operation. In such a case, the test mode is naturally set. In this case, the output signal does not appear at the terminal 9 if the terminal 10 is set to the non-signal state. If there is no terminal between the analog and the logic, a logic test signal can be input from the DC input terminal, and the logic circuit can be tested.

The flowchart shown in FIG. 5 shows the operation in the first embodiment in steps S1 to S6.

According to the first embodiment of the present invention, when the analog circuit is performing the power saving operation by the control terminal 12, the switching means comprising the selector circuit 7 for switching the digital circuit so that the test signal can be inputted. Is provided to test the digital circuit, so that the test of the digital circuit can be executed accurately using the control terminal 12 for performing the power saving operation of the analog circuit.

According to the embodiment, when the analog circuit is performing the power saving operation by the control terminal 12, the switching means including the selector circuit 7 for switching the digital circuit so that the test signal can be input is provided. And the D-type flip-flop 13 and the AND circuit 1
In the test mode period, the "H" level or "L" level voltage signal applied to the digital circuit as the logic circuit 4 according to the signal state of the control terminal 12 is maintained in the hold state during the test mode period. Since the test of the digital circuit is performed by providing the test voltage signal applying means, the test of the digital circuit can be performed more accurately by using the control terminal 12 for performing the power saving operation of the analog circuit. Can be.

Embodiment 2 FIG. As shown in FIG. 6, the external resistors R1 and R2 are provided so that the comparison circuit 2 has hysteresis.
Consider the case with. In this case, the comparison circuit 2 operates according to the hysteresis determined by the external resistors R1 and R2 as described below. VHYS = VTHH-VTHL = Vcc · R2 / (R2 + R
1) Here, VTHH is the input threshold voltage when the output level changes to "H", and VTHL is the input threshold voltage when the output level changes from "H" to "L".

A logic circuit test in such a circuit configuration is performed by making the output of the buffer 3 a three-state type as shown in FIG. 7 and inputting a logic test signal from an external resistor mounting terminal 17. The bias current control terminal 12 is connected to the control terminal of the three-state buffer 3. Therefore, when the bias current is turned off and the analog circuit enters the power saving state, the buffer 3 becomes high impedance, and a signal for a logic circuit test can be input from the terminal 17. That is, the buffer 3 is configured to have a high impedance when the analog circuit performs the power saving operation by the control terminal 12.

FIG. 8 is a flow chart of the circuit example of FIG. 7 up to execution of the logic test, and FIG.
Shown in Since there are four combinations of the two states of the terminals 10 and 11, there are four possible states of the logic circuit, as in the time chart of FIG. However, since this circuit does not need to set the logic circuit in the actual device mode, the operation becomes simpler than the time chart of FIG. Therefore, the four modes are collectively described in period 2.

In the period 2 in FIG. 9, the bias current setting terminal 12 is set to "L" to enter the test mode. In the test mode, the output of the three-state buffer 3 enters a high impedance state. At this time, if the external changeover switch 18 is also connected to the outside of the integrated circuit at the terminal 12, when the terminal 12 becomes "L" level, it switches to the B side. In this state, a logic test signal is input from the terminal 19, and when the test is completed, the terminal 12 is set to the "H" level to return to the actual device mode.

As in the circuit of FIG. 2, the analog circuit is saved in power during the actual operation to enter the test mode, and the terminal 17 is disconnected from the three-state buffer. However, the terminal 17 is disconnected via the external resistors R1 and R2. Reference voltage generation circuit 5
Connect with. That is, when the terminal 17 enters the power save mode, the terminal 17 is settled at the power supply voltage and does not float.

When there is any terminal between analog and logic, such as a terminal for attaching an external resistor for hysteresis, the terminal can be used as a logic test input terminal in combination with a three-state buffer, thereby facilitating the logic test. become able to.

The flowchart shown in FIG. 8 shows the operation in the second embodiment in steps S1 to S4.

According to the second embodiment of the present invention, when the analog circuit is performing the power saving operation by the control terminal 12, the buffer 3 to the digital circuit is configured to have high impedance, and the comparison circuit 2 Since the connection terminals 17 of the external resistors R1 and R2 to be connected are switched to input a test signal to the digital circuit from the test signal terminal 19, a control terminal for performing a power saving operation of the analog circuit. The test of the digital circuit can be executed accurately by using the test circuit 12.

[0040]

According to the first aspect of the present invention, when the analog circuit is performing the power saving operation by the control terminal, the switching means for switching so that the test signal can be inputted by the control from the control terminal is provided. Since the test of the circuit is performed, the test of the digital circuit can be accurately performed by using the control terminal for performing the power saving operation of the analog circuit.

According to the second aspect of the present invention, when the analog circuit is performing the power saving operation by the control terminal, the buffer for the digital circuit is configured to have a high impedance, and the external circuit connected to the comparison circuit is provided. Since the connection terminal of the resistor was switched and the test signal was input to the digital circuit from the test signal terminal,
The test of the digital circuit can be executed accurately using the control terminal for performing the power saving operation of the analog circuit.

According to the third invention, the test of the digital circuit in the digital-analog mixed integrated circuit is switched so that a test signal can be input to the digital circuit when the analog circuit is performing the power saving operation by the control terminal. Therefore, it is possible to provide a test method of a semiconductor integrated circuit device that can accurately execute a test of a digital circuit using a control terminal for performing a power save operation of an analog circuit.

[Brief description of the drawings]

FIG. 1 is a schematic flowchart showing an operation according to a first embodiment of the present invention.

FIG. 2 is a connection diagram showing a circuit configuration according to the first embodiment of the present invention.

FIG. 3 is a waveform chart showing a time chart according to the first embodiment of the present invention.

FIG. 4 is a waveform chart showing another time chart according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing an operation in the first embodiment according to the present invention.

FIG. 6 is a connection diagram showing a circuit configuration used in a second embodiment of the present invention.

FIG. 7 is a connection diagram showing a circuit configuration according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing an operation according to the second embodiment of the present invention.

FIG. 9 is a waveform chart showing a time chart according to the second embodiment of the present invention.

FIG. 10 is a connection diagram showing a circuit configuration according to a conventional technique.

FIG. 11 is a connection diagram illustrating a circuit configuration of an amplifier circuit.

FIG. 12 is a connection diagram illustrating a circuit configuration of a reference voltage generation circuit.

FIG. 13 is a diagram showing input / output waveforms in a digital / analog hybrid integrated circuit.

[Explanation of symbols]

1 amplifying circuit, 2 comparing circuit (comparator), 3 buffer circuit, 4 logic circuit, 5 reference voltage generating circuit, 6 oscillation circuit, 7 selector circuit, 8 analog signal input terminal, 9 logic output terminal, 10 and 11 logic modes A switching terminal 12 is a switching terminal for switching between a standby mode and an operation mode of the analog circuit, a 13D flip-flop, a 14 AND circuit, an 18 external switching switch, and a 19 signal terminal for testing.

Claims (3)

[Claims] 1. A digital / analog hybrid integrated circuit in which a digital circuit and an analog circuit for supplying a signal to the digital circuit are provided. The integrated circuit includes a control terminal for performing a power saving operation of the analog circuit. A semiconductor integrated circuit device, comprising: switching means for switching so that a test signal can be input to a digital circuit when a power saving operation is being performed by the control terminal, so as to test the digital circuit. 2. A digital-analog hybrid integrated circuit in which a digital circuit and an analog circuit having a comparing circuit and supplying a signal to the digital circuit are mixed. An amplifier circuit for amplifying an input signal and applying the amplified signal to the comparing circuit. A buffer receiving an output of the output of the comparison circuit, and a control terminal for controlling a bias current of the analog circuit to perform a power save operation, wherein the analog circuit performs a power save operation by the control terminal. When you are
A semiconductor integrated circuit, wherein the buffer is configured to have a high impedance, and a connection terminal of an external resistor connected to the comparison circuit is switched to input a test signal from a test signal terminal. Circuit device. 3. A digital analog integrated circuit in which a power saving operation of an analog circuit is performed by an input from a control terminal. In performing a digital circuit test in the digital analog mixed integrated circuit, the analog circuit uses the control terminal. A test signal can be input to a digital circuit when a power saving operation is performed by the method.