JP2000200214A - Memory system and assigning method for memory banks - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make adjustable changing demands of access agents by allocating 1st parts of memory banks to a 1st memory map of a 1st process agent and 2nd parts to a 2nd memory map of a 2nd process agent. SOLUTION: The 1st memory bank is assigned to the memory map of the 1st agent preferably in order as shown in Fig.A. Consequently, if the memory system is so initially sectioned into seven memory banks that the 1st agent can access and seven memory banks that the 2nd agent can access, the starting seven memory banks are assigned in the increasing order to the memory map of the 1st agent. Memory banks for order agents are assigned in the decreasing order (top to bottom) to the memory map of the 2nd agent from the bottom to the top.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the sharing of memory by a plurality of processing agents, and more particularly, to the efficient and flexible partitioning of a single-port shared memory among a plurality of processing agents.

[0002]

BACKGROUND OF THE INVENTION As the speed of today's processors has never been faster, memory designs have been attempted to meet such speed requirements. With the increasing integration of multiple specific task-oriented processors in a single system, efficient use of high-speed memory has become a design challenge.

For example, SDRAM technology has been developed for a wide range of applications to achieve high memory speeds,
The gap between the access time of asynchronous memories such as AM and SRAM and the need for high speed processors has been narrowed. Synchronous memory (eg, SDRAM technology)
Combine industry advances in fast DRAM with high-speed interfaces.

Functionally, SDRAMs are similar to conventional DRAMs. That is, it is dynamic and requires refreshing. However, the architecture of SDRAM is superior to standard DRAM. For example, SD
RAM uses internal pipelines to improve throughput, and uses on-chip interleaving between separate memory banks to eliminate output data gaps.

The idea of using SDRAMs synchronously (as opposed to using the DRAMs asynchronously) has arisen due to the increasing demand for data transfer in high-end processors. SDRAM circuit designs are based on state machine operation, rather than being level / pulse width driven as in conventional asynchronous memory devices. Also, synchronous memory access techniques improve the margin for system noise. This is because the input is not level driven. Instead, the input is latched by the system clock. Since all timings are based on the same synchronous clock, the specification machine is improved. Also, because SDRAM access is programmable, bus utilization can be improved. This is because the processor can be synchronized with the SDRAM output.

The core of the SDRAM device is a standard DRAM with important synchronization control logic. By synchronizing all address, data, and control signals with one clock signal, SDRAM technology can improve performance, simplify design, and provide faster data transmission.

[0007] Synchronous memory requires a clock signal from the accessing agent and allows the accessing agent to fully synchronize. If multiple agents are allowed to access the shared synchronous memory, each agent must provide its own clock signal to its synchronous memory in a conventional manner. However, clock signals from different agents are not synchronous in the prior art. That is, it is not an interface with the other. Thus, as the synchronous memory shifts from using one clock signal to another, a delay wait state must be added before the new agent's clock signal is used to access the synchronous memory.

Some synchronous memory devices have the ability to provide burst I / O. This is particularly suitable for optimizing the emphasis of cache memory at system frequencies. Advanced features such as programmable burst mode and burst length improve memory system performance and flexibility in traditional synchronous memory,
Eliminates the need to insert wait states (eg, dormant clock cycles) between individual accesses in a burst.

[0009] Traditional SDRAM devices have a separate fixed memory section, which can be accessed here or in an interleaved fashion. For example, two independent banks in an SDRAM device allow the device to have two different rows active at the same time. This means that one bank can read and write to the other bank during precharge. The setup for pre-charging and active-eighting rows can be hidden by interleaving bank accesses.

Conventionally, each task-oriented processing agent has a dedicated memory bank system as shown in FIG. In FIG. 6, two separate processing agent systems 600a and 600b have processing agents 602 and 604, respectively, and dedicated memory bank systems 508a and 508b. Each processing agent 602, 604 includes a microprocessor, a microcontroller, a digital signal processor (DS).
A suitable processor such as P) can be used.

In an application where one processing agent requires a large amount of information from another processing agent, the second processing agent may cooperate with the first processing agent to co-process information with an asynchronous memory. In order to reduce the need for information transmission between bank systems, a conventional asynchronous memory sharing technique using an arbitrator has been developed as shown in FIG.

In FIG. 7, a single-port type common memory bank system 508 has two processing agents 5.
02,504. A multiplexer (MUX) 510 selects the selected processing agent 50.
The 2,504 address, data, and control bus (ADC) are passed to a single-port common memory bank system 508 under the control of an arbiter, or arbitrator 512.

Unless arbitrated so that only one agent can access the single-port common memory bank system 508 at any time, separate agents 502 and 50 are provided.
Access to memory by 4 will crash.
Therefore, the selection logic (arbitrator 512) conventionally provided for controlling the multiplexer 510. The multiplexer 510 provides appropriate ADC signals to the single-port common memory bank system 508. The processing agents 502, 504 are typically assigned a hierarchy (biala key) in the arbitrator 512 for prioritized access to the single port common memory bank system 508,
Single port common memory bank system 508
The arbitrator 512 blocks access by other agents until the access to is terminated.

Another conventional technique for sharing a single-port common non-asynchronous memory uses a memory management address translator 706 as shown in FIG.

In FIG. 8, two processing agents 7
02 and 704 are accessing the single-port common memory bank system 508 under the control of the memory management address translator 706 and the MUX 708. The address translation function includes a processing agent 702,
It functions to invisibly index memory accesses by one of the 704s into a predetermined amount of memory (eg, 7k as shown in FIG. 8).

Therefore, for example, the first processing agent 7
02 is indexed by memory management address translator 706 to physical address 0 in single-port common memory bank system 508, and memory access by second processing agent 704 to address 0 is memory management Address translator 706
Depending on the offset physical address (for example, 7) in the single-port type common memory bank system 508.
K).

In the past, address translation was fixed in a shared memory system and did not provide flexibility, even when the memory needs of the processing agent changed, especially when the agent was running.

[0018]

Thus, there is a need for a memory system that coordinates the changing demands of multiple access agents.

[0019]

SUMMARY OF THE INVENTION A memory system in accordance with the principles of the present invention comprises a plurality of contiguous (collectively adjacent) memory banks having a lowest addressable (addressable) end and a highest addressable end.
s) Consists of a memory bank. A switch is configured to switch each of a plurality of adjacent memory banks,
Accessed from one of the first processing agent and the second agent. The control circuit allocates a first sub of the plurality of adjacent memory banks in ascending order from a lowest addressable end to a first memory map of the first processing agent, and allocates a second sub of the plurality of adjacent memory banks from a highest addressable end. Allocate to the second memory map of the second processing agent in descending order.

In accordance with the principles of the present invention, a method of allocating a plurality of memory banks for sharing among a plurality of processing agents is provided, wherein the lower address of the first processing agent is associated with the last one of the plurality of memory banks. Providing access to the plurality of memory banks to the first processing agent such that a higher address of the first processing agent is associated with the last one of the plurality of memory banks. The second processing agent is configured such that the lower address of the second processing agent is associated with the last one of the plurality of memory banks and the higher address of the second processing agent is associated with the first one of the plurality of memory banks. Provided access to the memory banks.

According to another principle of the present invention, a method for assigning a plurality of shared memory banks to two agents comprises:
Allocating a plurality of shared memory banks to the memory map of the first agent in ascending order. The plurality of shared memory banks are allocated to the memory map of the second agent in descending order.

According to yet another principle, a method for assigning a plurality of shared memory banks to two agents comprises assigning a plurality of shared memory banks to each of the two processing agents in an opposing manner.

[0023]

1 and 2 show a single-port memory system having a plurality of memory blocks that can be accessed by two separate agent or processing agent groups. The present invention relates to allocating a plurality of shared memory blocks between two agents.

In FIG. 1, a common memory system 3
10 shows a configuration of a shared memory partitioned so as to allocate a predetermined number of memory banks 10 to each of an access agent or an agent group. FIG. 1 shows the synchronous memory 310,
The present invention can also use asynchronous shared memories (traditional memories such as DRAM, SRAM).

In FIG. 1, it is shown in connection with two groups of access agents. That is, a first group of shared memory accessing agents 340 including the processing agents 302 to 306, and a second group of shared memory accessing agents 342 including the processing agents 312 to 316. Although the agent groups 340, 342 are intended to have the same number of agents, the present invention can be used with accessing agent groups having any number of agents as well.

The memory block 310 is divided into partitions 310a and 310b. Although shown in this embodiment as two partitions 310a, 310b, the present invention can be used with any number of partitions. Preferably, the number of partitions is equal to the number of agent groups.

Separate agent groups 340, 34
2 accesses the corresponding partitioned portion of the shared memory 310. Partitions 310a, 310b may be of any size and may occupy from zero to the entire size of memory block 310, as set in configuration register 360.

According to the present invention, memory block 310
The allocation of memory banks in is flexible and allows any size memory bank in the memory block 310 to be assigned to any of the agent groups 340, 342. Due to such a configuration, the processing agents 302 to 306, 312 to 3
The user can change the memory configuration before running 16 or by executing certain instructions in the code to change the value in the configuration register 360 on-the-fly.

The configuration register 360 contains the agent 30
2, 304, 306, 312, 314, 316. In this embodiment, the value written to configuration register 360 corresponds to the length of first partition 310a, and the remaining memory banks are assigned to the second partition.

Of course, multiple words or registers can be implemented in configuration register 360 and shared memory block 310 can have more than two configurable partitions.

The memory block 310 is preferably (but not necessarily) partitioned into adjacent partitions. For example, if the configuration register 360 is 1 4
With bit registers, the partition between any of up to 16 memory banks can be properly represented.

For example, it is assumed that there are 14 memory banks in the memory block 310 for convenience of explanation.
Agents 302, 304, 306, 312, 31
Either of 4, 316 becomes 360 and the value is “9” (0101H)
, This means that the arbitrator 312 assigns the first nine individual memory banks to the first agent 340 and the remaining five individual memory banks to the second agent group 342. 310 to be interpreted.

Next, the 4 bits of the configuration register 360 are decoded by the arbitrator 312 and the first MU
An appropriate control signal is given to X 308 to select or not select a requested or winning agent in the first agent group 340, and to select a requested or winning agent in the second agent group 342 for the second MUX 308. Or make no choice. Because the memory block 310 is partitioned, both agent groups 340, 342 can access their corresponding assigned partitions 310a, 310b without collision.

The memory bank arbitrator can also have holes in the memory space as desired. For example, the first agent is a memory bank 71,
2, 4, 6, 8 so that the second agent can be assigned memory banks 14-9, 7, 5, 3.

In a multiple agent system, one shared memory block is often provided for use by all agents in the system. A fixed amount of memory for each agent in the system becomes inefficient for a number of reasons (e.g., the application program at each agent changes frequently for any user).

For example, one of two available DSPs in an IC consisting of a memory access system.
If only one user implements the code, only that user will be given a minimum if there is a memory request by the second DSP. In this case, it may be preferable to allocate or partition all available shared memory to the first DSP and not allocate memory to the second DSP.

FIG. 2 shows a memory system 41 comprising a plurality of individual memory banks 1-14 that can be assigned to be accessed by either the first agent bus 496 or the second agent bus 497.
0 is shown. The memory banks 1 to 14 are either synchronous memories (eg, SDRAM) or asynchronous memories (eg, D
RAM). Also, while shown with respect to 14 individual memory banks in the embodiment of FIGS. 2-5B, the present invention can be similarly used in a shared memory system having any number of individual memory banks.

The memory banks 1 to 14 of the common memory system are flexibly allocated to be accessed by two agent buses according to the invention. This allocation is done in the opposite direction from last to first and from first to last memory bank.

The individual memory banks 1-14 are each configurablely accessible by any agent by using the appropriate multiplexers 401-414. MUXs 401-414 are individually controlled by selection logic 412b, which effectively implements flexible partitions in memory system 410 based on information set in configuration registers 460b.

This flexible partition can be moved during operation of the memory system, but is preferably done after it has been confirmed by all affected agents. Thus, if one agent needs more memory, the memory accessible by that agent can be increased and the memory accessible by other agents decreases.

The present invention not only partitions a plurality of memory banks between two agents, but also allocates memory banks in reverse order. FIGS. 3A-5B show the individual memory banks 1-14 as Agent 1 (FIGS. 3A, 4A, 5A).
FIG. 3A shows an embodiment in which a memory map is assigned to Agent 2 and Agent 2 (FIGS. 3B, 4B, and 5B).

In accordance with the principles of the present invention, the first memory banks are preferably allocated to the first agent's memory map, as shown in FIG. 3A. Therefore,
If the memory system 410 is initially partitioned to have seven memory banks accessible to the first agent and seven memory banks accessible to the second agent, the first seven memory banks are shown in FIG. 3A. Assigned to the memory map of the first agent in ascending order. In contrast, as shown in FIG. 3B,
Memory banks for other agents are allocated in descending order (highest to lowest) to the second agent's memory map from lowest to highest.

FIGS. 4A and 4B show that five memory banks are the first.
Nine memory banks assigned to agents are second
An example of the assignment of individual memory banks 1-14 as assigned to agents is shown. The lowest memory bank is assigned to the first agent in ascending order starting with the lowest memory bank (eg, memory bank # 1), and the highest memory bank is assigned in ascending order starting with the highest memory bank (eg, memory bank # 14). Assigned to second agent.

Similarly, FIGS. 5A and 5B show that the first agent has 9 lowest memory banks (in order, memory banks # 1 to # 1).
# 9) shows an example of a mapping of memory banks 1-14 allocated initially to use the five highest memory banks (in order memory banks # 14- # 10) with the second agent using the highest five memory banks. is there.

The present invention obtains memory banks addressed in different ways from two agents. Nevertheless, by simply changing the location of the partitions between the memory banks, the data in the memory bang stored by the first agent can be accessed by other agents as well.

The invention has many uses. For example, 2
In a Kate DSP system, the first DSP runs a modem application program that requires seven or more memory banks, and the second DSP runs a medium quality audio session that requires a balance of the other seven memory banks. Suppose you have In this case, the configuration register is set to “7” (0111H), for example, and the first seven memory banks 1 are sequentially arranged from the lowest to the highest.
7 is instructed to the first DSP, and the second DSP is instructed to allocate the remaining seven memory banks 14 to 8 in order from the highest to the lowest. Then, at a later point in time, the user may receive a second
A high quality audio session can be operated by the DSP.

Either the first or second DSP can adjust the settings in the configuration register 460 to more memory banks appropriate for the second DSP. This comes at the expense of the size of the memory partition of the first DSP. For example, in this case, the value “2” (00
10H) is written to the configuration register 460 and the first D
Allocate 2 memory banks 1 and 2 to SP,
The second memory bank 14-3 is configured into a second partition of a memory block for use by the second DSP. Conversely, at any time, the user may want to run a high baud rate modem program on the first DSP that requires a large amount of memory. In this case, the configuration register 460 can be written, for example, to assign the first eleven memory banks 1-11 to the first DSP and leave only the remaining three memory banks 14-12 for use of the second DSP. .

Thus, in accordance with the present invention, two processing agents access a shared memory subsystem in adjacent memory spaces without having to adjust to facilitate memory access without changing the manner in which the memory space is addressed. be able to.

As described above, any processing agent can use part or all of the memory system without changing the memory space received by another processing agent.

More generally, in a shared memory bank system having M memory banks, a first processing agent owns memory banks 1-N and a second processing agent owns memory banks N + 1-M.
From the point of view of the first processing agent, address 0 is the first
It is arranged in the memory bank 1 and the address increases as the number of memory banks increases. For the second processing agent, address 0 is located in the highest memory bank M,
As the number of memory banks decreases, the addresses increase. This is the case for adjacent memory requirements. Of course, the allocation of the memory banks does not have to be on an adjacent condition.

Thus, in accordance with the principles of the present invention, data can be simply exchanged between two processing agents, or data can be exchanged separately between coordinated processing agents. For example, data can be written to a memory bank by a first processing agent, which can then simply be switched to the domain of the second processing agent by appropriately switching the multiplexer. This multiplexer controls the input to the memory bank and allows the second processing agent full access to the data.

[Brief description of the drawings]

FIG. 1 is a diagram of a common memory that is structurally partitioned such that a predetermined number of memory banks are assigned to each access in agent.

FIG. 2 is a diagram of an embodiment of the partitionable memory system shown in FIG.

FIG. 3 is a memory allocation diagram illustrating a first example of a plurality of memory banks allocated for two agents to access in reverse order according to the present invention.

FIG. 4 is a memory allocation diagram similar to FIG.

FIG. 5 is a memory allocation diagram similar to FIG. 3;

FIG. 6 illustrates a conventional two-agent system having separate asynchronous memory systems.

FIG. 7 illustrates a prior art two-agent system using an arbitrator to access an asynchronous shared memory.

FIG. 8 illustrates a prior art agent system using a memory management address translator to offset memory access from one of the agents.

[Explanation of symbols]

0 address 302-306, 312-316, 502, 504, 6
02, 604, 702, 704 Processing agents 308, 318, 401-414, 510 Multiplexers (MUX) 310 Memory blocks 310a, 310b Partitions 340, 342 Agent groups 360, 460, 460b Configuration registers 1-14 Memory banks 410 Memory systems 412b Selection logic 496, 497 Agent bus 508 Single port type common memory bank system 508a, 508b Dedicated memory bank system 512 Arbitrator 600a, 600b Processing agent system 706 Memory management address translator

 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Richard Joseph Neissier, Peach Tree Lane, Bethlehem, Pennsylvania, United States, 18015 1937

Claims (27)

[Claims] (A) a plurality of memory banks having a lowest addressable end and a highest addressable end as a whole; and (B) a first portion of the plurality of memory banks in an ascending order from the lowest addressable end. A control module allocating to a memory map and allocating a second portion of the plurality of memory banks to a second memory map of a second processing agent in descending order from the highest addressable end. 2. The memory system according to claim 1, wherein the plurality of memory banks are adjacent. And (C) further comprising a switch configured to switch each of the plurality of memory banks to be accessed from one of the first processing agent and the second processing agent. The memory system according to claim 1. 4. The memory of claim 1, wherein the control module (B) has a configuration register that defines a first portion of the plurality of memory banks and a second portion of the plurality of memory banks. system. 5. The memory system according to claim 1, wherein the plurality of memory banks are assigned to only one of the first processing agent and the second processing agent at any time. 6. The memory system according to claim 1, wherein said plurality of memory banks are synchronous memory banks. 7. The memory system according to claim 1, wherein said plurality of memory banks are asynchronous memory banks. 8. A method for allocating a plurality of memory banks for sharing among a plurality of processing agents, comprising: (A) a low address of a first processing agent and a last address of the plurality of memory banks; Causing the first processing agent to access the plurality of memory banks such that a high address of the first processing agent is associated with the last one of the plurality of memory banks; and (B) a low address of the second processing agent. Is associated with the last one of the plurality of memory banks and the second processing agent is associated with the second one of the plurality of memory banks such that a high address of the second processing agent is associated with the last one of the plurality of memory banks. Accessing. 9. The method of claim 8, wherein the first one of the plurality of processing agents is associated with an address 0 in a memory map of the first processing agent. 10. The method of claim 8, wherein said first one of said plurality of processing agents is associated with an address 0 in a memory map of a second processing agent. 11. The method of claim 9, wherein said first one of said plurality of processing agents is associated with an address 0 in a memory map of a second processing agent. 12. The method of claim 9, wherein said plurality of memory banks are synchronous memories. 13. The method of claim 9, wherein said plurality of memory banks are asynchronous memories. 14. The method of claim 9, wherein each of the plurality of memory banks cannot be accessed simultaneously by both the first processing agent and the second processing agent. 15. A method of allocating a plurality of shared memory banks to two agents, comprising: (A) allocating a plurality of shared memory banks to a memory map of a first agent in ascending order; Assigning the shared memory bank to the second agent's memory map in descending order. 16. The method of claim 15, wherein said plurality of shared memory banks comprises synchronous memory banks. 17. A method of allocating a plurality of shared memory banks to two agents, comprising: (A) allocating a plurality of shared memory banks in reverse order to each of the two processing agents. . 18. Apparatus for allocating a plurality of memory banks for sharing among a plurality of processing agents, wherein: (A) a low address of a first processing agent is associated with a last one of the plurality of memory banks. Means for allowing the first processing agent to access the plurality of memory banks such that the high address of the first processing agent is associated with the last one of the plurality of memory banks; Means associated with the last one of the plurality of memory banks and having the second processing agent access the plurality of memory banks such that a high address of the second processing agent is associated with the first one of the plurality of memory banks; An apparatus comprising: 19. The apparatus of claim 18, wherein the first one of the plurality of processing agents is associated with an address 0 in a memory map of the first processing agent. 20. The apparatus of claim 18, wherein said first one of said plurality of processing agents is associated with an address 0 in a memory map of a second processing agent. 21. The apparatus of claim 20, wherein said first one of said plurality of processing agents is associated with an address 0 in a memory map of a second processing agent. 22. The apparatus according to claim 18, wherein said memory bank is a synchronous memory. 23. An apparatus for allocating a plurality of shared memory banks to two agents, comprising: (A) means for allocating a plurality of shared memory banks to a memory map of a first agent in ascending order; Means for allocating the shared memory banks to the memory map of the second agent in descending order. 24. The apparatus of claim 23, wherein said plurality of shared memory banks comprises synchronous memory banks. 25. An apparatus for allocating a plurality of shared memory banks to two agents, comprising: (A) means for allocating a plurality of shared memory banks in reverse order to each of the two processing agents. . 26. The apparatus of claim 25, wherein said plurality of shared memory banks comprises a synchronous memory. 27. (A) a first processing agent, (B) a second processing agent, (C) a shared synchronous memory accessible by the first and second processing agents, and (D) ascending order from the lowest addressable end. Assigning a first portion of the plurality of memory banks to a first memory map of a first processing agent;
A control module for allocating the plurality of shared synchronous memories to the memory map in descending order from the highest addressable end.