JP2000200210A - Memory managing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory managing device, which is suitable for a data processing method for a dynamically managed memory and easily detects and avoids a memory leak, for a packet exchanger, a router device or the like. SOLUTION: The memory managing device comprises a data memory 3 composed of a RAM or the like, a link list memory 5, and an address control part 4 arranged and connected to between both the memories 3 and 5. The address control part 4 has a free area management part 41, a use area management part 42, and an address/link list control part 43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory management device for detecting / avoiding a memory leak in a memory (storage device) such as a computer.

[0002]

2. Description of the Related Art Conventionally, a memory management device for detecting / avoiding a memory leak has been widely used in a computer for detecting unnecessary allocation of memory.

A conventional example of such a memory management device or method is as follows.
For example, it is disclosed in “Method and Apparatus for Detecting Memory Leak” in JP-A-9-244948. In such a conventional example, in addition to the file name and line number, the corresponding memory allocation should be deallocated before the appearance of the event in the memory allocation table that tracks the allocation and release of the memory. A memory leak is detected by storing an expiration event indicating that the information has expired, and allocation release information including a dependent pointer indicating the current allocation of the memory.

[0004]

However, there is a problem that the conventional memory management device and method are complicated and large-scale. This is because, in a conventional system for detecting a memory leak, the memory of a computer is dynamically allocated by an operating system (OS) to a program, that is, a plurality of processes used for a specific function. This is because the purpose is to detect a case where the assignment is not canceled when the assignment is completed.

[0005] In other words, the time interval between the memory allocation of the computer and its release depends on the processing time of each process. The processing time of each process is not unequivocally determined because, for example, there are processes that are processed in an extremely short time and processes that are required while the computer is operating, depending on the processing contents. For that purpose, the memory area allocated to the valid process,
Determining the memory area allocated to the invalid process,
In other words, for the purpose of detecting a memory leak, a means for managing file information corresponding to a process, information on a currently allocated block of a memory, and allocation release information is required.

An object of the present invention is to provide a simple memory management device adapted to data processing in a packet switching device or a router device.

It is another object of the present invention to provide a memory management device which prevents / avoids a reduction in data processing capacity due to an increase in an unusable memory area due to unnecessary allocation of memory.

[0008]

To solve the above-mentioned problems, a memory management device according to the present invention has the following characteristic configuration.

(1) A data memory for storing input data based on a write request signal and reading it as output data based on a read request signal, a link list of each packet of the input data, and a link list of the free area of the data memory A memory management device comprising: a link list memory for storing an address; and an address control unit connected between the data memory and the link list memory for generating an address to the data memory.

(2) The address control section has a free area management section for outputting write address information, a use area management section, and an address / link list control section connected to the free area and use area management section. (1) The memory management device.

(3) The memory management according to (2), wherein the free area management unit has a head address management unit that holds a free area head address of the data memory and a tail address management unit that holds the free area tail address. apparatus.

(4) The memory management device according to (2) or (3), wherein the used area management unit has an unreleased address bit processing unit configured by a counter that counts a set fixed time and a logic circuit.

(5) The address / link list control unit includes a page number management unit including a down counter and an initial value setting circuit, an address generation link list memory address control unit, and a link list memory data processing unit. ), (3) or (4).

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a memory management device according to the present invention will be described below in detail with reference to the accompanying drawings.

First, an overall system configuration of a packet switching device including a memory management device according to the present invention will be described with reference to FIG. This system comprises an input data processing unit 2, a memory management device 1, an output request control unit 6, a route search processing unit 7, a switch control unit 8, and an output data processing unit 9 connected to a plurality of communication lines. The output of the data processing unit 9 is sent to a communication line. Here, the memory management device 1 includes a data memory 3, an address control unit 4, and a link list (chain information) memory 5.

In the system shown in FIG. 1, the input data processing unit 2 is a unit (page) unique to the apparatus for each packet in order to independently and quickly switch packets from a plurality of communication lines. , And an attribute for determining a processing method of each packet is generated. Output request control unit 6
Controls the output request for switching based on the attribute of each packet generated by the input data processing unit 2.

The route search processing unit 7 includes an output request control unit 6
In response to the output request, the output destination is determined, the switch is controlled, and information for reading the packet divided into the page of the output request source from the data memory is generated. Memory management device 1
Has a data memory 3 for storing the divided pages as described above and reading them out when necessary, and appropriately controlling them as described later.

The switch control unit 8 switches the page read from the data memory 3 to the destination determined by the route search processing unit 7. The output data processing unit 9 reassembles the packet data divided into pages switched by the switch control unit 8 so as to conform to the format of the output communication line and outputs the reassembled packet data.

The memory management device 1 will be further described. The data memory 3 of the memory management device 1 stores the data from the input data processing unit 2 at the address generated by the address control unit 4 and generates the data from the address control unit 4 in response to a read request from the route search processing unit 7. The address data is output to the switch control unit 8.

The address control unit 4 includes the input data processing unit 2
A write address and a read address to the data memory 3 are generated from a write request from the CPU and a read request from the route search processing unit. Then, a link list memory 5 that stores a link list of each packet and a link list of a free area of the data memory 3 is managed for a page link in a packet unit. For some reason, the data memory 3
If the read request from the route search processing unit 7 for reading the data written in the data memory is incorrect and the page to be read from the data memory 3 is not read and has an unnecessary area,
It has a memory leak avoidance function to release this. The details will be described later.

Next, with reference to FIG. 2, a detailed configuration of the memory management device 1 of FIG. 1, particularly, the address control unit 4 therein will be described. The address control unit 4 includes a free area management unit 4
1. It comprises a use area management unit 42 and an address / link list control unit 43. The address / link list control unit 43 receives the write request and the read request, is interconnected with the free area management unit 41 and the use area management unit 42, and is also connected with the data memory 3 and the link list memory 5. . The free area management unit 41 outputs write address information.

Here, the free area management unit 41 includes storage means for storing the start address information and the end address information of the free area in the data memory 3 in the free area link list of the link list memory 5. In order to search the write address from the link list memory 5, the head address information of the free area is output to the address / link list control unit 43. Further, the head address information of the empty area is also output to the output request control unit 6.

The address / link list control unit 43 reads the address of the received free area starting from the free area of the link list memory 5 from the link list memory as a write address to the data memory 3 and outputs the read address to the data memory. At this time, a means for reading a new free area start address from the link list memory and updating the free area start address information of the free area management unit 41 and a first page address information of the read packet included in the read request, As a read address,
Means for passing the data to the data memory 3 and, if there is a subsequent page, reading the corresponding link list in the link list memory 5 and outputting it to the data memory 3; and when all the pages of the packet are read, the link list of the packet is read. Is added to the end address information of the free area management unit, so that the area is set as a free area again.

The use area management section 42 stores a counter for counting a set fixed time and a link list memory 5 so as to identify an address of the link list memory which has not been allocated to the free area at least once in the fixed time. There are means for managing the unreleased address display bits for writing, and means for reading the contents of the link list memory 5 at regular time intervals and recognizing the unreleased address display bits to determine the address as a memory leak area. .

FIG. 3 is a detailed block diagram of the address control unit 4 of FIG. In FIG. 3, a free area management unit 41 holds a free area start address of a data memory, and a start address management unit 11 that holds a free area end address. The register to be configured. The used area management unit 42 includes a counter 21 that counts a set fixed time by an internal clock, and an unaddressed address bit processing unit 22 configured by a logic circuit.

The address / link list control unit 43 includes a page number management unit 31 including a down counter and a logic circuit for setting an initial value, and a link list memory including a counter and a logic circuit for generating an address. It is composed of an address control unit 32 and a link list memory data processing unit 33 composed of a logic circuit and the like.

The operation of the preferred embodiment of the memory management device according to the present invention will be described below. First, the operation of the system shown in FIG. 1 will be described. The data memory 3 shown in FIGS.
Is a RAM (random access memory), and the link list memory 5 is a dual port memory (DPM).

In the system shown in FIG. 1, a plurality of communication lines are provided, and a plurality of packets are input from each of the plurality of communication lines. Therefore, first, each packet is divided by the input data processing unit 2 into a data length (page) unique to the apparatus, and is multiplexed for each packet in order to be passed to the next stage.

Next, attribute data including the packet length and the destination of each packet is created and output to the output request control unit 6. At the same time, during a route search process for determining a destination and a processing time for switching, the data is sent to a data memory 3 for storing the data in a standby state,
In order to obtain the write address, data including the number of pages of the packet is transmitted as a write request to the address control unit 4, and the page of each packet is stored in the write address specified by the address control unit 4 of the data memory 3. You. At this time, in the link list memory 5, link list information indicating at which address in the data memory the page for each packet is stored.

Subsequently, as information for switching the packet to the required correct destination, the attribute information of the packet passed to the output request control unit and the write address of the first page of the packet in the data memory are searched for a route. Transfer to processing unit 7. The route search processing unit 7 passes the switch control information to the switch control unit 8 based on the set route information, and reads out the data (packet) to be switched so as to read the first page of the packet written in the data memory. The address is passed to the address control unit 4 as a read request.

The address controller 4 outputs a read address to the data memory 3 based on the received address and the link list of the corresponding packet written in the link list memory 5. The page read from the corresponding address in the data memory 3 is switched by the switch control unit 8 in accordance with the switching information together with the attribute from the route search processing unit for each packet, and the output data processing unit 9 of the predetermined destination is determined. Sent to Output data processing unit 9
Then, the received page is reassembled in packets based on the attribute information, and is transmitted in a data format suitable for a communication line.

In this series of operations, the read request processed and generated by the route search processing unit 7 is not correctly passed to the address control unit 4 for some reason, and the data to be read from the data memory 3 is deleted. The fact that the information is not read out and remains in the link list memory 5 and an area that cannot be allocated to an address to which data is newly written occurs afterwards is defined as a memory leak.

Here, in order to facilitate understanding, a specific example will be described. For example, when a packet 1 and a packet 2 are input from two communication lines, first, the input data processing unit 2 divides the data into a data length (page) unique to the device. Here, it is assumed that the packet length of the packet 1 is 28 bytes and the packet length of the packet 2 is 20 bytes. And assuming that one page length is 10 bytes, packet 1 is divided into three pages,
The remaining two bytes of the last one page contain dummy data. Packet 2 is divided into two pages, which are exactly divisible by the page length, so that no dummy data is inserted.

Then, attribute data including the packet length and destination of each packet is created, and the created attribute data is output to the output request control unit 6.
Output to At the same time, in order to write the packet divided into pages into the data memory 3, as a write request to the address control unit 4, if the packet is 1, the page number information 3 is transmitted, and the pages of the packet 1 are sequentially transmitted to the data memory. I do.

Next, the operation of the memory management device according to the present invention will be described with reference to FIGS. Address control unit 4
Then, three pages, which are the number of pages to be written, received by the page number management unit 31 of the address / link list control unit 43, are set to the initial value of the down counter.

Link list memory address control unit 32
Looks at the set value of 3, and prepares an address for writing three empty pages into the data memory.
, The head address of the free area is received, the contents of the link list memory at that address are referenced, and at the same time, the value of the down counter of the page number management unit 31 is decremented by one. The free area start address is output to the address of the data memory as the write address of the first page.
The content referred to here is output to the write address of the data memory as the address of the second page, and the content of the link list memory at that address is referred to as the write address of the third page. At this time, the value of the down counter is reduced by one again. The address of the third page is output to the write address of the data memory, and the contents of the link list at that address are referred to.

Here, when the address / link list control unit recognizes that the value of the down counter, which is decremented by one again, has become 0, the referenced value is set as the new start address of the free area as the start address. The data is written to the register of the management unit 11. Similarly, 0, which is a reserved value for indicating that the page written at this address is the last page of the packet, is written in the link list of the link list memory. Now packet 1
Are sequentially written. At this time, the data of the address of the link list read as the write address to the data memory includes an unreleased address display for identifying an area of the data memory that has not been allocated to a free area during a certain period of time. 1 is written to the bit. This bit is used so that once it is allocated to an empty area for a certain fixed time, even if that area is allocated to an address for writing a page to the data memory again, it is not written to 1 42
Is controlled by the unreleased address bit processing unit. Also, this fixed time is determined by the counter 2 of the used area management unit 42.
The set value is determined from the packet length to be processed by the device, the route search processing unit, and the switching capability, and the maximum time during which the page is normally stored in the data memory is defined as the minimum value. One cycle is a value obtained by taking several cycles for protection. The first page address initially held by the first address management unit 11 is:
It is output as write address information of the first page.
Similarly, packet 2 is processed.

FIG. 4 is an address map of the link list memory and the data memory in the embodiment according to the present invention. FIG. 4A shows an address map of the link list before the page-divided packet is written to the data memory.
All the areas are free areas, the head address of the free area is 2, the end address of the free area is 9, and the link list of the free area is 2-3-3-5-8-8-4-7 in order.
−9. FIG. 4B shows an address map of the data memory after the packet 1 and the packet 2 are written into the data memory. The three pages of the packet 1 and the two pages of the packet 2 are stored in the link list memory. Indicates that the data is sequentially written from the head of the free area indicated in the address map of FIG.

FIG. 5 is an address map of the link list after the packets 1 and 2 have been written to the data memory. Here, the link list of the packet 1 is in the order of the address 2-3-5, and the content of the address 5 contains 0 indicating the last page. Similarly, the link list of the packet 2 is 6-8, and the link list of the empty area is 1-4-7-9.

In order to switch the packet to the required correct destination, the attribute information of the packet passed to the output request control unit and the write address of the first page of the packet in the data memory are sent to the route search processing unit 7. hand over.
The route search processing unit 7 passes the switch control information to the switch control unit 8 based on the set route information, and reads out the data (packet) to be switched so as to read the first page of the packet written in the data memory. If the packet is a packet 1, the address 2 is passed to the address control unit 4 as a read request.

Referring to FIGS. 2 and 3, the address control unit 32 of the address / link list control unit 43 that has received the read request sets the address as the top address and stores the link information of the packet stored in the link list. After that, the content is output as a read address to the data memory 3 until 0 indicating the last page is recognized. The read address of the data memory output in the case of the packet 1 is 2-3-5, and three pages of the packet 1 are output from the data memory. At this time, in the read address, the read start address is written as data at the end of the free area of the link list memory indicated by the register of the end address management unit 12 of the free area management unit 41, and the address of the third page is set as the new address. By updating as a free area end address, it is reassigned to a free area. At this time, 0 is written in the unreleased address bits of the link list memory reallocated to the free area.

The page output from the data memory is switched by the switch control unit 8 in accordance with the switching information together with the attribute from the route search processing unit for each packet, and is sent to the output data processing unit 9 having a predetermined destination. You. In the output data processing unit 9, the received page is
The packet is reassembled on the basis of the attribute information, and transmitted in a data format suitable for the communication line.

Next, in addition to the packets 1 and 2, when a new packet is not processed, and a packet 2 and a read request are not received after a certain period of time after which the packets 1 and 2 should have been read. The operation will be described.

FIG. 6 is an address map of the link list memory in a state where only the packet 1 is read from the address map of the link list memory in a state where the packets 1 and 2 of FIG. 5 are written. Here, it is assumed that the read information of the packet 2 does not come and the addresses 6 and 8 are invalid areas. The address control unit 32 and the data processing unit 33 of the address / link list control unit use a value set in the counter 21 of the use area management unit 42 from one port of the link list memory configured by DPM. The unreleased address display bit of the address is being scanned.

Here, the time required to scan all the addresses once is a fixed time set in the counter 21. When scanning is performed after a predetermined time from the previous scanning, addresses 6 and 8 in which 1 is written in the unreleased address display bit are regarded as memory leak areas. The address of this area is written in the content indicated by the end address of the free area, and is updated as a new end address. Also,
By writing 0 to the memory leak address, the memory leak area is reallocated as a free area. In this case, the address map of the link list memory 5 is the same as that of FIG.

The configuration and operation of the preferred embodiment of the memory management device according to the present invention have been described above in detail. However, the present invention should not be limited to only such an embodiment, and it can be easily understood by those skilled in the art that various modifications can be made without departing from the gist of the present invention.

[0047]

As can be understood from the above description, according to the memory management device of the present invention, a dynamically used memory is divided into two pieces of chain information (a link list) of a used area and a free area. ). The invalid area is assigned to one bit of data in the link list memory for storing the link list. Unopened address bits are detected by scanning at fixed time intervals determined from the processing capacity of the device. For this reason, a memory leak can be detected / avoided only by adding a configuration for confirming one bit of data in the link list memory, a counter for counting a fixed time, and an unreleased address bit of the link list memory. Therefore, there is a practically remarkable effect that the intended memory leak can be detected / avoided with a simple configuration.

That is, according to the memory management device of the present invention,
In the case of a dynamically allocated memory, writing / reading is always repeated in all areas over a long period of time, and the data processing time peculiar to the device is counted. The area has been detected. Therefore, there is an effect that special plural pieces of information and control hardware are not required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bucket communication system using a memory management device according to the present invention.

FIG. 2 is a block diagram of a preferred embodiment of the memory management device shown in FIG. 1;

FIG. 3 is a detailed block diagram of an address control unit of the memory management device shown in FIG.

4 is a diagram showing an example of an address map (A) of a link list memory and an address map (B) of a data memory of the memory management device shown in FIG. 2;

5 is a diagram showing an address map of a link list memory after packets 1 and 2 have been written to a data memory of the memory management device shown in FIG. 2;

6 is a diagram showing an example of an address map of a link list memory in a state where packets 1 and 2 shown in FIG. 5 are written.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory management device 3 Data memory 4 Address control unit 5 Link list memory 11 Start address management unit 12 End address management unit 21 Counter 22 Unreleased address bit processing unit 31 Page number management unit 32 Link list memory address control unit 33 Link list memory Data processing unit 41 Free area management unit 42 Used area management unit 43 Address / link list control unit

Claims (5)

[Claims] 1. A data memory for storing input data based on a write request signal and reading it out as output data based on a read request signal, a link list of each packet of the input data, and a link list of the free area of the data memory. A memory management device, comprising: a link list memory for storing; and an address control unit connected between the data memory and the link list memory for generating an address to the data memory. 2. The method according to claim 1, wherein the address control unit includes a free area management unit for outputting write address information, a use area management unit, and an address / link list control unit connected to the free area and use area management unit. The memory management device according to claim 1, wherein: 3. The free area management section according to claim 2, further comprising: a start address management section for holding a free area start address of the data memory; and a tail address management section for holding the free area end address. 3. The memory management device according to claim 1. 4. The memory according to claim 2, wherein the used area management unit includes an unaddressed address bit processing unit including a counter for counting a set predetermined time and a logic circuit. Management device. 5. The address / link list control unit includes a page number management unit including a down counter and an initial value setting circuit, an address generation link list memory address control unit, and a link list memory data processing unit. The memory management device according to claim 2, 3 or 4, wherein: