JP2000194577A - Fault detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault detecting circuit which can easily specify a fault place. SOLUTION: Registers 12 and 22 for test data storage are provided at the exit of a peripheral device controller 2 and the entrance of a peripheral device 1, respectively, and data written to a storage circuit 11 are compared with data stored in those registers 12 and 22 to specify a fault location on a data transmission line. Thus, the fault location can be specified without replacing the peripheral device controller 2, the peripheral device 1, and a cable 3, then the trouble to prepare and replace a substitute peripheral device controller, a substitute peripheral device, and a substitute cable can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a failure detection circuit for detecting a failure in a data transfer path.

[0002]

2. Description of the Related Art Conventionally, a data parity check unit is often provided to detect a failure in a data transfer path. If a parity error occurs due to a mismatch between the data stored in the memory and the parity bit or the occurrence of noise on the data line, the control unit is interrupted accordingly and the diagnostic routine is executed. It is designed to diagnose failures.

[0003]

For this reason, when a data error which has not been detected by a data parity error conventionally occurs, it is difficult to identify the location where the failure has occurred. The problem is that a great deal of time is spent on the work, such as exchanging the device and peripheral devices and cables. Therefore, the present invention has been made in view of such circumstances,
It is an object of the present invention to provide a failure detection circuit that can easily specify a failure location.

[0004]

In order to achieve the above object, according to the first aspect of the present invention, test data storage means provided on a data transfer path for temporarily storing test data; A failure location specifying means for performing write / read of test data and identifying a failure location according to coincidence / mismatch between the written test data and the read test data.

According to the second aspect of the present invention, test data storage means is provided at each of the data transfer destination and the data transfer source and temporarily stores test data written via the data transfer path, and the data transfer destination and the data transfer The test data is written / read to / from each of the original test data storage means, and the test data written to the test data storage means at the data transfer destination and the test data storage means at the data transfer source are compared with the test data read therefrom. Correspondingly, there is provided a failure point specifying means for specifying whether the failure point is a data transfer destination, a data transfer source, or a data transfer path.

According to the present invention, when a data error occurs, the fault location specifying means writes / writes test data to the test data storage means provided on the data transfer path.
Since the readout is performed and the failure location is specified in accordance with the match / mismatch between the written test data and the read test data, the failure location can be easily specified.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. (1) Summary of the Invention A failure detection circuit according to the present invention is provided with a test data storage register on a data transfer path.
By writing / reading test data to / from this register, a failure location is specified.

(2) Configuration FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. A peripheral device 1 and a peripheral device controller 2 and a cable 3 for connecting the peripheral device 1 and the peripheral device controller 2 are shown.
And a keyboard 4 for inputting commands and test data in the test mode, and a display 5 for displaying the read test data. The peripheral device 1 selects the storage circuit 11 and a register b12 for storing test data at the time of writing in the test mode, and the test data read from the storage circuit 11 and the test data storage register b12 at the time of reading in the test mode. And a peripheral device side test mode control circuit 14 in which a test mode command from the keyboard 4 is set.

The peripheral device side test mode control circuit 14
Test data storage register b by test mode setting
12 and the data select timing of the selector 13 are controlled. The peripheral device controller 2 selects the normal write data and the write data in the test mode and outputs the selected data, the register a22 for storing the test data, the test data read from the peripheral device 1 and the test data storage. A selector 23 for selecting and outputting data of the register a22 for
It comprises a controller-side test mode control circuit 24 in which a test mode command from the keyboard 4 is set. The controller-side test mode control circuit 24 sets the test data storage register a22 according to the test mode setting.
, And the timing of selecting data to the selectors 21 and 23.

(3) Operation In the above configuration, when the operator executes a test data write command from the keyboard 4 and inputs test data, the test data is generated by the data select generated by the controller side test mode control circuit 24 by the test mode command. The data is selected by the selector 21 based on the timing, is stored in the test data storage register a22 by the write timing generated by the controller-side test mode control circuit 24, and is transferred to the peripheral device 1 via the cable 3 at the same time.

The test data transferred to the peripheral device 1 is stored in the test data storage register b12 at the write timing generated by the peripheral device side test mode control circuit 14 according to the test mode command, and at the same time, the storage circuit 11 is written. Next, when the operator executes a data read instruction of the storage circuit 11, a read instruction of the test data storage register b12, and a read instruction of the test data storage register a22 from the keyboard 4, the storage circuit 11 and the test data storage register b12 output the instruction. Is read by the selector 13 according to the data select timing generated by the peripheral device side test mode control circuit 14 according to the test mode instruction.
And is transferred to the peripheral device controller 2.

The read data from the peripheral device 1 and the test data storage register a22 is supplied to the selector 23 by the data select timing generated by the controller-side test mode control circuit 24 according to the test mode instruction.
Is selected and transferred to the display 5. Thus, the operator identifies the location of the failure in the data transfer path by checking the data displayed on the display 5.

For example, when the test data input from the keyboard 4 and the content of the data read from the test data storage register a22 do not match, it is specified that there is a fault in the peripheral device controller 2, and the input using the keyboard 4 is performed. Test data and test data storage register a
If the contents of the data read from the test data storage register 22 match and the contents of the data read from the test data storage register b12 do not match, it is specified that the cable 3 has a failure. Also, the test data input from the keyboard 4 and the contents of the data read from the test data storage register a22 and the test data storage register b12 match, and only the contents of the data read from the storage circuit 11 do not match. In this case, it is specified that the storage circuit 11 has a failure.

As described above, according to the present invention, the test data storage registers 12 and 22 are stored in the peripheral device controller 2.
, And at the entrance of the peripheral device 1, and by reading out the data written in the storage circuit 11 and the data stored in these registers 12 and 22, it is possible to specify the failure point on the data transfer path. . In addition, since it is possible to specify a failure point without replacing the peripheral device controller 2, the peripheral device 1, and the cable 3, the trouble of preparing and replacing the replacement peripheral device controller, the peripheral device, and the cable can be eliminated. You can also.

[0015]

According to the present invention, when a data error occurs, the fault location specifying means writes / reads test data to / from the test data storage means provided on the data transfer path, and writes the written test data. The failure location is specified in accordance with the match / mismatch between the data and the read test data. Therefore, the failure location can be easily specified, and the work such as cable replacement which has been conventionally required can be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Peripheral device 2 Peripheral device controller 3 Cable 4 Keyboard 5 Display 11 Storage circuit 12, 22 Test data storage register (Test data storage means) 13, 23 Selector 14, 24 Test mode control circuit (Fault location specifying means)

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[Procedure amendment]

[Submission date] November 16, 1999 (1999.11.
16)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

1. A data transfer destination of the inlet and the data transfer
Respectively provided in the connection data transfer source outlet <br/> via Okusaki a cable, and the test data storage means for temporarily storing test data to be written through the data transfer path, said data transfer destination and the writes / reads the test data for each test data storage means and said data transfer destination storage circuit of the data transfer source, before
Depending on the serial data transfer destination and the data transfer source for each test data storage means and a result of mutual comparison between the test data read therefrom and the test data written in said data transfer destination storage circuit, fault location is the de <br/> over data transfer destination, the data transfer source and the failure detecting circuit, characterized by comprising a failure place specifying means for specifying which one of said cable.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Deleted

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

Means for Solving the Problems To achieve the above object,
Therefore, in the present invention, the data transfer destination entrance and the data
Out destination and is connected via a cable data transfer source
Respectively provided in the mouth, and the test data storage means for temporarily storing test data to be written through the data transfer path, said data transfer destination and the respective test data in the data transfer source storage device and the data transfer destination storage circuit < br /> performs write / read of the test data to, written to the data transfer destination and the respective test data transfer source <br/> Todeta storage means as well as the data transfer destination storage circuit <br/> According to the result of the mutual comparison between the test data and the test data read therefrom,
Said data transfer destination, the data transfer source and the Cave
And a failure location specifying means for specifying which of the two is a fault.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

According to the present invention, when a data error occurs, the fault location specifying means is connected to the data transfer device via a cable.
Each test data storage means and data transfer destination of the serial respectively provided at the inlet and the data transfer source outlet of Okusaki
Perform the test data write / read with respect 憶回path and test data and the test data read therefrom written to each test data storage means and the storage circuit
According to the result of the mutual comparison, the failure location is
Since a data transfer source or a cable is specified, a failure location can be easily specified.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015]

According to the present invention, when a data error occurs, the data of the failure point specifying means connected by a cable is used.
Each test data storage means and data transfer destination respectively kicked set <br/> the data transfer destination of the inlet and the data transfer source outlet
The test data is written / read to / from the storage circuit of each of the above, and the test data written to each of the test data storage means and the storage circuit is compared with the test data read therefrom. Location is data transfer
Since the destination is the data transfer source or the cable , the failure location can be easily specified, and the operation such as cable replacement which has been conventionally required can be omitted.

Claims (2)

[Claims] 1. Test data storage means provided on a data transfer path for temporarily storing test data, writing / reading test data to / from the test data storage means, writing the test data and reading the read test data A failure location specifying means for specifying a failure location according to a match / mismatch with the fault detection circuit. 2. Test data storage means provided at a data transfer destination and a data transfer source, respectively, for temporarily storing test data written via a data transfer path, and test data storage means at the data transfer destination and the data transfer source Test data is written / read from / to the test data storage means at the data transfer destination and the data transfer source, and the test data read from the test data is compared with the test data. A fault detection circuit comprising: a fault location specifying means for specifying which of a transfer destination, a data transfer source and a data transfer path.