JP2000194306A - Method and circuit to drive liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the picture quality and the reliability of a liquid crystal display panel having a counter signal line structure. SOLUTION: Scanning lines of a liquid crystal display panel having a counter signal line structure are provided with the voltage levels indicated in (a). If the voltage levels are higher than a threshold value, the system is turned on. If the levels are lower than the value, the system is turned off. While the system is turned off, voltage waveforms related to the signal line voltage shown in (b) are applied to the scanning line voltage, the alternating components between the scanning lines and the signal lines are canceled to improve the picture quality and the reliability. The signal voltage applied during a low level interval, in which the scanning line driving voltage is turned off, is formed by adding the average value voltage waveforms of the driving voltages of all signal lines that cross the lines in which scanning line driving voltages are turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display panel in which an active three-terminal element is formed on one substrate facing a liquid crystal layer. In particular, a signal line made of a transparent conductor is formed on an opposite substrate. Further, the present invention relates to a driving method and a driving circuit for a liquid crystal display panel having a structure for applying an electric field to a liquid crystal layer between the pixel electrode and the pixel electrode.

[0002]

2. Description of the Related Art In recent years, liquid crystal display panels have been widely used as display devices such as word processors, personal computers, and television receivers. 2. Description of the Related Art A liquid crystal display panel is formed by forming a large number of thin films such as a metal and a semiconductor on a light-transmitting substrate such as a glass and patterning them into a desired shape by photolithography or the like.
One electrode substrate is obtained. The liquid crystal display panel has a structure in which the electrode substrates obtained in this manner are bonded together so that their electrode forming surfaces face each other and at a predetermined interval, and a liquid crystal is sealed between the electrode substrates. .

FIG. 8 shows the structure of a thin film transistor (hereinafter sometimes abbreviated as “TFT”) liquid crystal display panel which has been conventionally and generally used. The scanning line 1, the signal line 2, the TFT 3, and the pixel electrode 4 are formed in a matrix on one glass substrate. A common electrode 5 common to all pixels indicated by virtual lines is formed on a glass substrate opposed to the liquid crystal layer. Further, a reference line may be formed on the glass substrate on which the TFT 3 is formed via an auxiliary capacitor CS (not shown). TFT3 is active 3
It has a gate electrode 3g, a drain electrode 3d and a source electrode 3s as terminal elements.

A driving method for obtaining a high-quality image on a liquid crystal display panel having such a structure is described in, for example, the Journal of the Institute of Information and Image Technology Vol. 51, No. 10 (19
97), pp. 1768 to 1776, “TFT-L Using Digital Driver Having Tone Interpolation Function”.
CD drive system ". This document describes a driving method of a liquid crystal display panel called a floating gate driving method.

FIG. 9 shows a general driving waveform as a floating gate driving method described in the above-mentioned document. 9A is a scanning line driving voltage waveform, FIG. 9B is an average value of all signal line driving voltages on the y-th row selected when the scanning line driving voltage is on, and FIG. The reference line drive voltage waveform is shown. 9 (a), 9 (b), and 9 (c), with reference to the reference line voltage in FIG. 9 (c),
It can be represented as shown in FIGS. 10 (a), (b) and (c). FIG. 11 shows a case of a general active matrix driving method. 11A shows a scanning line voltage, FIG. 11B shows a specific gradation voltage, and FIG. 11C shows a reference line driving voltage waveform. The point that the floating gate driving method as shown in FIGS. 9 and 10 is more advantageous than the driving waveform of a general and simple driving method as shown in FIG.
This will be described below.

FIG. 12 shows a cross-sectional structure and a parasitic capacitance to be noted in driving of one liquid crystal display cell of a conventional liquid crystal display panel which performs active matrix driving. A liquid crystal layer 12 is sealed between the two glass substrates 10 and 11. On one glass substrate 10, an intrinsic semiconductor layer 14 is formed via an insulating film 13 in accordance with the arrangement of the TFTs 3 shown in FIG. The pixel electrode 1 is formed on the intrinsic semiconductor layer 14.
An n + semiconductor layer 16 for forming layers 5 and the like is formed. A gate electrode 17 is formed on the glass substrate 10 in a portion corresponding to the position of the TFT 3 in FIG. The intrinsic semiconductor layer 14 is formed above the gate electrode 17 with the insulating film 13 interposed therebetween.
The n + semiconductor layer 16 is separated from above. The portion of the n + semiconductor layer 16 connected to the pixel electrode 15 forms a drain electrode 18. The n + semiconductor layer 16 facing the drain electrode 18 forms a source electrode 19. Intrinsic semiconductor layer 1 between drain electrode 18 and source electrode 19
4 is thinner, and a channel portion 20 is formed. The upper portion of the channel portion 20 is generally protected by a protective film 21. A common electrode 22 having a solid electrode structure on one surface is provided on the glass substrate 11 facing the glass substrate 10.
Are formed. Here, the liquid crystal capacitance between the common electrode 22 on the channel portion 20 and the common electrode 22 is CM, the capacitance of the protective film 21 is CK, and the capacitance of the intrinsic semiconductor layer 14 and the insulating film 13 is Cgi. Further, the capacitance between the gate electrode 17 and the drain electrode 18 or the source electrode 19 is Cg, and the liquid crystal capacitance between the pixel electrode 15 and the common electrode 22 is CL.

FIG. 13 shows an equivalent circuit relating to display performance in a liquid crystal cell as shown in FIG. 12 in consideration of parasitic capacitance. FIG. 13A shows the state of the pixel (x, y) at the time of the (y + 1) -th scan in the off period. FIG. 13B shows the state of the pixel (x, y) at the time of the (y + 2) -th scan in the off period. FIG. 14 shows an equivalent circuit of a portion related to the reliability as a TFT. FIG. 14A shows that y +
The state of the pixel (x, y) at the time of the first scan is shown. FIG.
(B) is a pixel (x,
The state of y) is shown. In FIG. 13, the voltage Vp shown in FIG.
From the voltage Vp ′ shown in FIG.
When p′−Vp) becomes a value that is not negligible as compared with the voltage applied to the liquid crystal cell, flickering and deterioration in display quality occur. In the equivalent circuit shown in FIG.
The voltage Vt ′ shown in FIG. 14B and the voltage Vt shown in FIG.
When the voltage fluctuation amount (Vt′−Vt), which is the difference from t, becomes large, when driving the liquid crystal display cell for a long period of time, the display quality deteriorates due to a shift in TFT characteristics and the like.

In order to avoid such deterioration in display quality, a liquid crystal display panel is generally driven with a drive waveform as shown in FIG. 9 and FIG. That is, FIG.
In the equivalent circuit diagram shown in FIG. 14 and FIG. 14, when the gate voltage for driving the scanning line is in the off state, there is no AC component of the off voltage VGL of the gate voltage for driving the scanning line viewed from the common electrode driving voltage Vcom. Need to be driven. FIG. 10 shows a voltage waveform when the driving state as shown in FIG. 9 is reviewed with reference to the common electrode driving voltage Vcom.
It is necessary to drive the waveform shown in (b) so as not to have an AC component during the off period of the scanning line driving gate voltage shown in (a). The relationship between each voltage value and charge value shown in FIGS. 13 and 14 is as follows: Vcom (y + 2) −Vcom (y + 1) = VGL (y + 2)
−VGL (y + 1), and QG = QG ′, QL = QL ′, QS = QS ′, QM = QM ′, QK = QK ′, and Qgi = Qgi ′ hold, so that Vp′−Vp = Vt′−Vt = 0. Is realized. When this condition is satisfied, no charge transfer between the capacitors occurs, so that a highly reliable liquid crystal display panel can be realized.

FIG. 15 shows a specific example of such a floating gate driving method. In a liquid crystal display panel 23 configured by arranging liquid crystal display cells as shown in FIGS. 8 and 12 in a matrix, a scanning line 1 is driven by a gate driver 24 and a signal line 2 is connected to a data driver 2.
5 driven. 8 is driven by an output from the common voltage amplifier 26. The gate driver 24 is supplied with gate voltages VGH and VGL for driving a scanning line from the DC-DC converter 27. The DC-DC converter 27 converts a power supply voltage supplied from the outside, and further supplies a reference voltage Vref to the grayscale voltage source 28. Hereinafter, a DC-DC converter is an example representing a DC voltage source, and a method for producing the DC voltage source is not specified. The gray scale voltage source 28 generates eight types of voltages V0 to V7 corresponding to a 3-bit gray scale and supplies the voltages V0 to V7 to the data driver 25. In the floating gate driving method, the voltages V0 to V7 of each gradation are derived separately into two types, V0A to V7A and V0B to V7B, and are alternately switched by the voltage selector 29 to supply the gradation voltages V0 to V7 to the data driver 25. Given. A control signal for switching the gradation voltage to one of two types by the voltage selector 29 is provided from the controller 30. The controller 30 supplies display data supplied from the outside to the data driver 25, and the data driver 25 selects one of the gradation voltages V0 to V7 in accordance with the supplied data and selects one of the signal lines of the liquid crystal display panel 23. Drive. To perform the floating gate driving method, the output Vco of the common voltage amplifier 26 is used.
m is added to the off voltage VGL of the gate voltage for driving the scanning line by a capacitor or the like.

FIG. 16 shows an internal configuration for driving one signal line by the data driver 25 of FIG. Data to be displayed is taken into a sampling memory 31 which also displays Msmp at a timing determined by the sampling pulse Tsmp. The data taken into the sampling memory 31 is transferred to a holding memory 32 also indicated as MSC according to the output pulse LP. The data stored in the holding memory 32 is decoded by a decoder 33 indicated as DEC. The decoder 33 includes a demultiplexer 34 and ASW0 to ASW0.
Analog switches 40 to 47 indicated as SW7 are included. 3-bit data D0 input to the decoder 33
D2 is the eight outputs S0 to S7 of the demultiplexer 34.
Is turned on. One of the analog switches 40 to 47 connected to the output in the on state is turned on, and one of the eight types of gradation voltages V0 to V7 is turned on.
One of them is selected as the voltage for driving the signal line 2 as the output OUT.

For example, when the data value is 0, AS
The analog switch 40 displayed as W0 is turned on,
V0 which is one of the gradation voltages for driving the signal line provided from the voltage selector 29 external to the data driver 25
Is selected and output. The internal configuration as shown in FIG. 16 is provided in one-to-one correspondence with the signal lines of the liquid crystal display panel 23, and constitutes the data driver 25 as a whole.

FIG. 17 shows a partial electrode arrangement in a liquid crystal display panel having a counter signal line structure in which a signal line is provided on a substrate facing a substrate on which a TFT is formed. In the liquid crystal display panel 50, portions corresponding to the portions described in FIGS. 8 to 16 are denoted by the same reference numerals, and redundant description will be omitted. Prior art regarding the liquid crystal display panel having such a structure is as follows.
For example, it is disclosed in JP-A-61-215590.
In the liquid crystal display panel 50, the counter signal line 52 is formed on the substrate facing the substrate on which the TFT 3 is formed,
The source electrode of the TFT 3 is connected to the reference line 51.
The reference line 51 is formed in parallel with the scanning line 1 connected to the gate electrode of the TFT 3. The opposing signal line 52 on the opposing substrate is generated in a direction crossing the scanning line 1 and the reference line 51.

FIG. 18 shows the liquid crystal display panel 5 shown in FIG.
0 shows an electrical equivalent circuit. The drain electrode 3 d of the TFT 3 is connected to the pixel electrode 4. Opposing signal lines 52 are formed on the substrate opposing the pixel electrodes 4. By applying an electric field to the liquid crystal layer between the opposing signal line 52 and the pixel electrode 4, display can be performed for each pixel. In JP-A-61-215590, all of the reference lines 51 are grounded, or all of the reference lines are commonly connected.

The liquid crystal display panel 50 having the opposing signal line structure as shown in FIG. 17 is driven by using the driving voltage as shown in FIG. 11A shows a scanning line driving voltage waveform, FIG. 11B shows a signal line driving voltage waveform,
(C) shows a reference line drive voltage waveform. When the scanning line driving voltage waveform is at a high level, the TFT 3 is turned on. The pixel electrode 4 is charged according to the voltage of the relative difference between the signal line drive voltage and the reference line drive voltage. Further, in order to apply a large AC voltage to the liquid crystal display cell, the signal line drive voltage may be inverted with respect to the reference line drive voltage. In the paper described in the above-mentioned journal of the Institute of Information and Image Technology, the concept of reducing the amplitude of the signal line drive voltage by setting the reference line drive voltage to a rectangular wave is also presented. The AC drive of the reference line is also described in detail in the document, and the description thereof is omitted here.

[0015]

In a liquid crystal display panel having a structure in which the common electrode 5 is uniformly formed on the opposite substrate as shown in FIGS. 8 and 12, the scanning line drive voltage in the off state and the common electrode drive The cause of the decrease in reliability due to the AC component generated between the voltage and the voltage has been analyzed, and a practical driving method has already been established. However,
The liquid crystal display panel 50 having the opposing signal line structure as shown in FIGS. 17 and 18 is at the stage where a prototype is being produced at the laboratory level so far, and has not yet been commercialized. Not reached. The reason for this is that a factory plant for mass-producing liquid crystal display panels is premised on manufacturing a liquid crystal display panel having a structure in which uniform common electrodes are formed on a counter substrate as shown in FIGS. And the fact that such a conventional liquid crystal display panel and its driving system have already been mass-produced for many years, and the degree of perfection as a practical system is extremely high.

As to the driving system of the liquid crystal display panel having the opposed signal line structure, no optimization has been performed so far on the premise of commercialization, and only a basic driving method has been proposed. Until now, the subject of research was not the drive system, but rather the liquid crystal display panel itself,
This is because the problem of the display quality, that is, the phenomenon such as flicker or image sticking in the long-term reliability test has not been analyzed or studied as a comprehensive problem with the drive system.

As for the conventional liquid crystal panel, the fact that the reliability is lowered due to the AC component generated between the scanning line drive voltage in the off state and the common electrode drive voltage has been described above with respect to the floating gate drive. It has been found that adopting the law solves the problem. For a liquid crystal display panel having an opposed signal line structure, an alternating current component generated between a scanning line driving voltage and a signal line driving voltage causes a reduction in reliability. However, this problem cannot be solved at all. Further, in the opposing signal line structure, since the signal line electrodes on the opposing substrate side are driven with different voltages, a problem that must be solved in order to ensure the reliability of the liquid crystal display panel having the opposing signal line structure. Is very difficult.

An object of the present invention is to solve the above-mentioned problems by optimizing a driving method of a liquid crystal display panel having an opposed signal line structure and performing flickering or image sticking even after performing a long-term reliability test. It is an object of the present invention to provide a driving method and a driving circuit for a liquid crystal display panel which does not have high reliability.

[0019]

According to the present invention, a liquid crystal layer is provided between two substrates, and an active three-terminal element, a scanning line, a reference line, and a pixel electrode are arranged on one substrate. The gate electrode of the terminal element is connected to a scanning line, the drain electrode is connected to a pixel electrode, the source electrode is connected to a reference line, and a signal line made of a transparent conductor is formed on another opposite substrate. A liquid crystal display panel having a structure in which an electric field is applied to a liquid crystal layer between the pixel electrode and the pixel electrode, wherein an AC waveform is applied to both a voltage for driving a reference line and a voltage for driving a signal line. When the voltage is applied, the average value voltage waveform of the drive voltages of all the signal lines whose scanning line drive voltage intersects the line in the on state is added to all the scan lines in which the scan line electrodes are in the off state. The driving method of the liquid crystal display panel .

According to the present invention, a liquid crystal layer is provided between two substrates, an active three-terminal element, a scanning line, a reference line, and a pixel electrode are arranged on one substrate, and another opposing substrate is provided. Since a signal line made of a transparent conductor is formed on the top and has a structure to apply an electric field to the liquid crystal layer between the pixel electrode,
A liquid crystal display panel having an opposing signal line structure is configured. Active 3
The gate electrode of the terminal element is connected to a scanning line, the drain electrode is connected to a pixel electrode, and the source electrode is connected to a reference line. When driving the scanning lines of the liquid crystal display panel having such a counter line structure, the average value voltage waveform of the driving voltages of all the signal lines that intersect with the line in which the scanning line voltage is on is set to the off-state. Since it is added to all scanning lines in the state,
An AC component generated between the scanning line driving voltage and the signal line driving voltage in the off state is reduced, and a decrease in reliability can be prevented.

In the present invention, when applying the AC waveform to both the reference line driving voltage and the signal line driving voltage, the scanning line driving voltage is turned on for all the scanning lines whose scanning line driving voltage is off. Instead of all the signal lines intersecting with the line in the state, an average voltage waveform of the driving voltages of some signal lines in which the scanning line driving voltage intersects with the line in the on state is added.

According to the present invention, the average value voltage waveform of the drive voltages of some signal lines crossing the lines whose scan line drive voltage is on is applied to all the scan lines whose scan line drive voltage is off. Since the addition is performed, the off-state voltage of the scanning line driving voltage as viewed from the reference line driving voltage suppresses an AC component, and reliability can be improved. Since it is only necessary to use the drive voltages of some of the signal lines in order to obtain the average voltage waveform, the operation can be performed with a quicker and simpler configuration than in the case where the average value of the drive voltages of all the signal lines is obtained.

In the present invention, when applying the AC waveform to both the reference line drive voltage and the signal line drive voltage, the scan line drive voltage is turned on for all the scan lines whose scan line drive voltage is off. A driving voltage waveform of a signal line for outputting a specific gradation is applied instead of all the signal lines intersecting the state line.

According to the present invention, since the driving voltage waveform of the signal line for outputting a specific gradation is applied to all the scanning lines in which the scanning line driving voltage is in the off state, the scanning line driving voltage is in the off state. Sometimes, the AC component between the scanning line and the signal line can be reduced, and the reliability can be improved.

In the present invention, when applying the AC waveform to both the reference line drive voltage and the signal line drive voltage, the scan line drive voltage is turned on for all the scan lines whose scan line drive voltage is off. In place of the average voltage waveform of the drive voltages of all the signal lines intersecting the state line, a signal line drive voltage waveform capable of outputting a stepwise voltage close to the average voltage is added.

According to the present invention, a stepwise output voltage close to the average voltage of all the signal lines crossing the line where the scanning line driving voltage is on is applied to all the scanning lines whose scanning line driving voltage is off. Is added, the AC component can be reduced. In addition, since it is not necessary to calculate the average value of the added voltages, the reliability can be improved with a simple configuration.

In the present invention, when applying the AC waveform to both the reference line drive voltage and the signal line drive voltage, the scan line drive voltage is turned on for all the scan lines whose scan line drive voltage is off. Instead of the average voltage waveform of the drive voltage of all the signal lines that intersect with the line in the state, the voltage that is the closest to the average value of the signal line drive voltage in which the scanning line drive voltage intersects the line in the on state is output. It is characterized in that possible signal line drive voltage waveforms are added.

According to the present invention, the voltage closest to the average value of a part of the signal line driving voltages is added to all the scanning lines whose scanning line driving voltages are in the OFF state. Thus, reliability can be improved.

Further, according to the present invention, a liquid crystal layer is provided between two substrates, an active three-terminal device, a scanning line, a reference line, and a pixel electrode are arranged on one substrate, and a gate electrode of the active three-terminal device is provided. Is connected to a scanning line, a drain electrode is connected to a pixel electrode, and a source electrode is connected to a reference line. A signal line made of a transparent conductor is formed on another opposing substrate, and the pixel electrode is connected to the pixel electrode. Circuit for driving a liquid crystal display panel having a structure for applying an electric field to a liquid crystal layer between the two, and applying an AC waveform to both a voltage for driving a reference line and a voltage for driving a signal line. A liquid crystal display panel comprising: a control circuit having a function of calculating an average value of signal line drive voltages; and a selector for selecting an analog voltage according to output data of the control circuit. A driving circuit Le.

According to the present invention, the control circuit has a function for calculating the average value of the signal line drive voltage incorporated in the control circuit, and the selector selects the analog voltage according to the output data of the control circuit. As an analog voltage applied to all the scanning lines in the state, the average value of the signal line driving voltage is added to all the scanning lines in which the scanning line driving voltage is in the off state, and the signal line driving voltage and the scanning line driving voltage in the off state are added. The AC component of the difference can be reduced to improve the reliability.

Further, in the present invention, the control circuit has a memory required for performing an operation for obtaining an average value of the signal line drive voltage, and has a data driver having a function of outputting an analog voltage selected by the selector. It is characterized by the following.

According to the present invention, the control circuit includes:
A memory necessary for performing an operation for calculating an average value of the signal line drive voltage is provided, and an analog voltage selected by the selector is output by the data driver and added to the scan line drive voltage. Occasionally, the AC component of the difference from the signal line drive voltage can be reduced to improve reliability.

[0033]

FIG. 1 shows a schematic electrical configuration of a liquid crystal display device 60 including a driving circuit according to an embodiment of the present invention. A liquid crystal display panel 63 in which liquid crystal display cells are formed in a matrix at the intersections of the scanning lines 61 and the signal lines 62 is formed such that the signal lines 62 are formed in a substrate shape opposite to the substrate on which the scanning lines 61 are formed. , And a counter signal line structure as shown in FIGS. The scanning line 61 is driven by a gate driver 64, and the signal line 62 is driven by a data driver 65. LCD panel 63
, A common voltage amplifier 66 is further provided. Various voltages are supplied to the gate driver 64 and the common voltage amplifier 66 from the DC-DC converter 67. The gate driver 64 is supplied with a high-level scanning gate voltage VGH that is turned on and a low-level scanning gate voltage VGL that is turned off. The common voltage amplifier 66 is supplied with a high-level common voltage VampH, a low-level common voltage VampL, and a reference voltage Vref.

The reference voltage Vref is also supplied to the gray scale voltage source 68. The grayscale voltage source 68 corresponds to, for example, eight levels of grayscale represented by 3 bits based on the reference voltage Vref, and is a signal necessary for floating gate driving.
It generates six types of voltages V0A to V7A and V0B to V7B. The grayscale driving voltage is supplied to the voltage selector 69, and is supplied to the voltage selector 69 in accordance with the floating gate driving timing.
The types of gradation voltages V0 to V7 are selected and supplied to the data driver 65. The selection of the voltage by the voltage selector 69 is performed based on a control signal from the controller 70. The controller 70 also provides the data driver 65 with a data signal as a 3-bit digital value.

In the data driver 65 of this embodiment,
A function to calculate the average value of data is also provided, and the average value is Vs
Output as average. The output of the common voltage amplifier 66 drives the reference line 71 of the liquid crystal display panel 63. The average voltage Vs average is supplied to an average voltage amplifier 72 and is supplied to a gate driver 6 via an adder 73 such as a capacitor.
4 is added to the low-level scanning voltage VGL given from the DC-DC converter 67.

The DC-DC converter 67 operates based on DC power supplied from the outside, and generates various voltages. Not only DC-DC converters, but also voltage regulator circuits, voltage divider circuits combining resistors, etc.
Similarly, various voltages can be generated. Controller 70
Is supplied with display data from outside. Although it is assumed that the display data is given as a 3-bit digital value, the number of bits is not limited to 3 bits, but can be a larger number of bits. In that case, the number of gray scale voltages to be switched by the gray scale voltage source 68, the voltage selector 69 and the data driver 65 may be increased.

Each output voltage generated by the DC-DC converter 67 can be stabilized by inserting a regulator circuit or the like. The control signal generated from the controller 70 and given to the gate driver 64 includes a vertical start pulse and a vertical shift clock.
With these control signals, a high-level driving gate voltage V
GH and a low-level driving gate voltage VGL are selected and applied to the liquid crystal display panel 63 from the gate driver 64 via the scanning line 61. The common voltage amplifier 66 connects the reference line 71 to the high-level VcomH and the low-level VcH.
AC drive with omL. The gradation voltages V0A to V7A generated by the gradation voltage source 68 are high-level reference line voltages V.
comH. The signal line driving voltages corresponding to the low-level VcomL are V0B to V7B. The voltage of “A” and the voltage of “B” are temporally switched by a control signal from the controller 70, and are supplied from the voltage selector 69 to the data driver 65 as gradation voltages V0 to V7.
The operation of the data driver 65 to output the input gradation voltages V0 to V7 to the signal line 62 of the liquid crystal display panel 63 is the same as that of FIG.

FIG. 2 shows a data driver 65 for each signal line 6.
2 shows an internal configuration for driving the control unit 2. The decoder 75 of FIG.
Then, based on the 3-bit data by the decoder 76, the AS
Eight analog switches 8 denoted as W0 to ASW7
One of 0 to 87 is selected and output as an output data signal OUT, and a specific gradation voltage, for example, V4 is output as an average value signal voltage Vs average. It is desirable that the specific gradation voltage is close to the average value of the voltages for driving all the signal lines 62.

FIG. 3 shows a target driving waveform in the liquid crystal display panel 63 having the opposed signal structure of FIG. FIG. 3A shows a driving voltage waveform for the scanning line 61, and FIG. 3B shows all the signal lines 6 in the y-th row selected when the scanning line driving voltage is on.
FIG. 3C shows the driving waveform of the reference line 71, respectively. As shown in FIG. 3A, even in the OFF section where the scanning voltage is lower than the threshold value indicated by the broken line, FIG.
By adding a signal equivalent to the average waveform as shown in (b), the difference between the scanning line voltage and the signal line voltage can be calculated.
It can be seen that the AC component can be suppressed in the OFF section. In this embodiment, since an intermediate gradation voltage is applied,
Reduction of the AC component is possible.

FIG. 4 shows the cross-sectional structure of the liquid crystal display panel 63 having the opposed signal line structure shown in FIG. 1 and the parasitic capacitance of each portion of interest. The liquid crystal display panel 63 includes two glass substrates 10
The liquid crystal layer 102 is sealed between the layers 0 and 101. On one glass substrate 100, an insulating film 103, an intrinsic semiconductor layer 104, and a pixel electrode 105 are sequentially formed. The pixel electrode 105 is formed by the n + semiconductor layer 106. The liquid crystal display panel 63 is shown in FIGS.
The electrode structure shown in FIG.
A gate electrode 107 connecting portions where the FT 3 is formed is formed on the glass substrate 100 before the formation of the insulating film 103. Therefore, in the portion where the gate electrode 107 is formed, the insulating film 103, the intrinsic semiconductor layer 104, and the n + semiconductor layer 106 are formed in a shape that is raised toward the glass substrate 101, which faces the other portion. FIG.
In FIG. 18, a drain electrode 108 and a source electrode 109 are formed on a portion where a TFT 3 is formed with a channel portion 110 interposed therebetween.
Is configured. The periphery of such a channel portion 110 is
It is covered with a protective film 111. A signal line 62 is formed on the glass substrate 101 facing the glass substrate 100 via the liquid crystal layer 102. The parasitic capacitances CM, CK, Cgi, Cg, CL of the liquid crystal display panel 63 of this embodiment are basically the same as the parasitic capacitances described with reference to FIG.

FIG. 5 shows an equivalent circuit of a portion related to display performance. FIG. 5A shows the state of the pixel (x, y) at the time of the (y + 1) -th scan in the off period. FIG. 5B shows y +
The state of the pixel (x, y) at the time of the second scan is shown. FIG.
In comparison with the above, both ends of the series circuit of CL and Cg
Since the low-level gate voltage VGL (y + 1) obtained by adding the first signal voltage Vs (y + 1) and its average value is applied, the AC component is canceled. In contrast, FIG.
In the conventional configuration as shown in FIG. 3, CL is the common voltage (Vc
om (y + 1)) and the TFT is turned off, so that the AC component does not cancel out and the display performance may be reduced.

FIG. 6 shows an equivalent circuit of a portion related to the reliability of the TFT. FIG. 6A shows the state of (x, y) at the time of the (y + 1) -th scan in the off period, and FIG. 6B shows the state of the pixel (x, y) at the time of the y + 2-th scan. Parasitic capacitance C
A signal line voltage Vs is applied to one end of M, CK, and Cgi connected in series, and a low-level gate voltage V
GL is applied. Since the average value of the drive voltage of the signal line and the like are applied to the low-level gate voltage VGL side, the AC component can be canceled and the reliability can be improved.

FIG. 7 shows a schematic electrical configuration of a liquid crystal display device 120 according to another embodiment of the present invention. In the present embodiment, portions corresponding to the embodiment of FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. In the present embodiment, the average value Vs average of the signal line voltage is generated by the voltage selector 121. The data driver 122 only drives each signal line 62, similarly to the conventional data driver 25. Average voltage Vs a generated from voltage selector 121
verage is calculated by digital operation processing in the controller 123 for all signal line drive voltages, and is selected in the voltage selector 121 according to a control signal and a selection signal given from the controller 123 to the voltage selector 121;
Or formed. In the controller 123, a memory and a processor for performing calculations are provided.

In the embodiment shown in FIG. 7, the average value of all the signal line driving voltages is calculated as the average voltage Vsaverage, but the average value of some voltages, or the average value of all or some Can be used in place of the average voltage waveform of all the signal lines. Further, the controllers 70 and 123
The data drivers 65, 122 and the like can also be integrally formed as a semiconductor integrated circuit (IC).

In the present invention, as shown in FIG. 3A, during a period in which the scanning line driving voltage is off, a voltage having some relationship with the change voltage of the signal line is added, and the scanning line driving voltage is turned off. In this case, the AC component in the period is suppressed, and the image quality and the reliability can be improved.

[0046]

As described above, according to the present invention, in the liquid crystal display panel having the opposing signal line structure, all the scanning lines in which the scanning line driving voltage is off are connected to the lines in which the scanning line driving voltage is on. Since the average waveforms of the drive voltages of all intersecting signal lines are added, the AC component between the scanning line in the OFF state and the signal line can be reduced, and a decrease in reliability due to the AC component can be avoided. it can.

According to the present invention, the average value of the drive voltages of some signal lines that intersect with the line in which the scanning line drive voltage is on is added to the drive voltage of the scan lines. The reliability can be easily improved as compared with the addition.

Further, according to the present invention, the driving voltage of the signal line for outputting the specific gradation is added to all the scanning lines in the state where the scanning line driving voltage is off, so that the average value waveform can be easily obtained. The reliability can be improved with a simple configuration.

Further, according to the present invention, the scanning line driving voltage is gradually changed to the average value of the driving voltages of all the signal lines intersecting the lines in the on state for all the scanning lines in the off state. Since the voltages are added, the AC component when the scanning line driving voltage between the scanning line and the signal line is off is reduced, and reliability and display quality can be improved.

Further, according to the present invention, the voltage closest to the average value of a part of the signal line driving voltages that intersects with the line whose scanning line driving voltage is on is applied to all the scanning lines whose scanning line driving voltage is off. Is added, reliability and image quality can be improved with a simple configuration.

Further, according to the present invention, the control circuit has a built-in function for calculating the average value of the signal line driving voltage, so that the average value waveform can be easily generated and the liquid crystal display panel having the opposed signal line structure can be used. In addition, it is possible to suppress problems such as flickering and burning that occur in the reliability test, and to perform driving with high display quality.

Further, according to the present invention, the data driver
The average value is calculated and the analog voltage is selected according to the calculation result, so that the liquid crystal display panel having the opposed signal line structure can be driven with high reliability and high display quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of a liquid crystal display device 60 including a drive circuit according to an embodiment of the present invention.

FIG. 2 shows a decoder 7 included in the data driver 65 of FIG.
FIG. 5 is a block diagram showing an internal configuration of the fifth embodiment.

FIG. 3 is a waveform diagram showing drive signals for the liquid crystal display panel 63 having the opposed signal line structure in the embodiment of FIG.

FIG. 4 is a simplified sectional view showing a sectional structure and a parasitic capacitance of the liquid crystal display panel 63 of FIG.

FIG. 5 is an equivalent circuit diagram relating to image quality in an off period based on the parasitic capacitance in FIG. 4;

FIG. 6 is an equivalent circuit diagram relating to the reliability of an off period based on the parasitic capacitance of FIG. 4;

FIG. 7 is a liquid crystal display device 120 according to another embodiment of the present invention.
FIG. 3 is a block diagram showing a schematic electrical configuration of FIG.

FIG. 8 is an electric circuit diagram showing a relationship between a TFT substrate and a counter electrode in a conventional TFT active matrix type liquid crystal display panel.

9 is a waveform diagram showing a driving voltage when performing floating gate driving on the liquid crystal display panel shown in FIG.

10 is a waveform diagram showing a voltage for driving the liquid crystal display panel of FIG. 8 based on the reference line voltage shown in FIG. 9C.

FIG. 11 is a waveform diagram showing a driving voltage when floating gate driving is not performed on a conventional liquid crystal display panel.

12 is a simplified sectional view showing a sectional structure and a parasitic capacitance of the liquid crystal display panel shown in FIG.

13 is an equivalent circuit diagram of an off period related to image quality in consideration of the parasitic capacitance in FIG.

FIG. 14 is an equivalent circuit diagram related to the reliability of an off period in consideration of the parasitic capacitance of FIG. 12;

FIG. 15 is a block diagram showing an electrical configuration for driving a liquid crystal display panel as shown in FIG. 8 by floating gate driving.

FIG. 16 is a block diagram showing an electrical configuration of a unit circuit constituting the data driver of FIG.

FIG. 17 is a partial perspective view showing an electrode structure of a liquid crystal display panel having a counter signal line structure.

18 is an electric circuit diagram showing an electrode arrangement in the liquid crystal display panel having the opposed signal line structure shown in FIG.

[Explanation of symbols]

 60, 120 Liquid crystal display device 61 Scan line 62 Signal line 63 Liquid crystal display panel 64 Gate driver 65, 122 Data driver 66 Common voltage amplifier 67 DC-DC converter 68 Gradation voltage source 69, 121 Voltage selector 70, 123 Controller 71 Reference line 72 average voltage amplifier 73 adder 75 decoder 76 decoder 80-87 analog switch 100, 101 glass substrate 102 liquid crystal layer 107 gate electrode 108 drain electrode 109 source electrode 110 channel part

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keiichi Tanaka 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside (72) Inventor Akishi Fujiwara 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka In-house F term (reference) 2H093 NA16 NA36 NA43 NA53 NB25 NC03 NC05 NC34 ND10 ND12 ND35 ND47 5C006 AA11 AC11 AC24 AF44 AF59 BB15 BC12 BF24 FA33 5C080 AA10 BB05 DD03 DD29 EE29 FF11 GG12 JJ02 JJ03 JJ03 JJ04 JJ04 JJ04 JJ04

Claims (7)

[Claims] A liquid crystal layer is provided between two substrates, an active three-terminal element, a scanning line, a reference line, and a pixel electrode are arranged on one substrate, and a gate electrode of the active three-terminal element is a scanning line. The drain electrode is connected to the pixel electrode, the source electrode is connected to the reference line, and a signal line made of a transparent conductor is formed on another opposing substrate, and A method for AC driving a liquid crystal display panel having a structure for applying an electric field to a liquid crystal layer, wherein a scanning line electrode is applied when an AC waveform is applied to both a voltage for driving a reference line and a voltage for driving a signal line. A method of driving a liquid crystal display panel, wherein an average voltage waveform of driving voltages of all signal lines whose scanning line driving voltage intersects with lines in an on state is added to all scanning lines in an off state. 2. When applying an AC waveform to both the reference line drive voltage and the signal line drive voltage, all of the scan lines whose scan line drive voltages are in the off state are connected to the scan line drive voltage in the on state. 2. The method according to claim 1, wherein, instead of all the signal lines intersecting the lines, an average value voltage waveform of the driving voltages of some signal lines intersecting the lines in which the scanning line driving voltage is on is added. Driving method of liquid crystal display panel. 3. When applying an AC waveform to both the reference line drive voltage and the signal line drive voltage, all of the scan lines whose scan line drive voltages are in an off state are connected to the scan line drive voltage in an on state. 2. The liquid crystal display panel driving method according to claim 1, wherein a driving voltage waveform of a signal line for outputting a specific gradation is applied instead of all the signal lines crossing the line. 4. When applying an AC waveform to both the reference line driving voltage and the signal line driving voltage, all of the scanning lines whose scanning line driving voltage is in an off state are connected to the scanning line driving voltage in an on state. 2. The signal line driving voltage waveform capable of outputting a stepwise voltage close to the average voltage instead of the average voltage waveform of the driving voltages of all the signal lines crossing the line. Driving method of liquid crystal display panel. 5. When applying an AC waveform to both the reference line driving voltage and the signal line driving voltage, all of the scanning lines whose scanning line driving voltage is in an off state are connected to the scanning line driving voltage in an on state. Instead of the average voltage waveform of the drive voltages of all the signal lines crossing the line, a voltage closest to the average value of some signal line drive voltages crossing the line where the scanning line drive voltage is on can be output. 2. The method according to claim 1, further comprising adding a signal line drive voltage waveform. 6. A liquid crystal layer is provided between two substrates, an active three-terminal element, a scanning line, a reference line, and a pixel electrode are arranged on one substrate, and a gate electrode of the active three-terminal element is a scanning line. The drain electrode is connected to the pixel electrode, the source electrode is connected to the reference line, and a signal line made of a transparent conductor is formed on another opposing substrate, and A circuit for driving a liquid crystal display panel having a structure for applying an electric field to a liquid crystal layer, comprising: an AC application circuit for applying an AC waveform to both a voltage for driving a reference line and a voltage for driving a signal line; A drive circuit for a liquid crystal display panel, comprising: a control circuit having a function of performing an operation for calculating an average value of a line drive voltage; and a selector for selecting an analog voltage according to output data of the control circuit. 7. The control circuit includes a memory required to perform an operation for calculating an average value of a signal line driving voltage, and a data driver including a function of outputting an analog voltage selected by the selector. 7. A driving circuit for a liquid crystal display panel according to claim 6, wherein: