JP2000193715A - Test board for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate a testing treatment in a test and to make a test of high reliability regarding a test board, for a semiconductor device, in which a plurality of sockets used to mount the semiconductor device on a printed-circuit board are arranged and installed. SOLUTION: In this test board for a semiconductor device, a plurality of IC sockets 11 which are formed in such a way that every pedestal 15 used to mount the semiconductor device 1 is provided and that contact pins 13 which are electrically connected to leads 2 installed at the semiconductor device 1 are provided are arranged and installed on a printed-circuit board 12. The test board is constituted in such a way that every pedestal 15 is displaced when the semiconductor device 1 is mounted. In addition, the test board is constituted in such a way that the displacement of every pedestal 15 is detected by POGO pins 15, and that the mounting state of the semiconductor device 1 can be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test board for a semiconductor device, and more particularly to a test board for a semiconductor device having a plurality of sockets for mounting a semiconductor device on a printed circuit board. 2. Description of the Related Art In recent years, testing of semiconductor devices (mainly, memory type burn-in / stress tests) has been progressing to test burn-in. This burn-in test is performed using a semiconductor device test board (hereinafter, simply referred to as a test board) in which a plurality of IC sockets are arranged on a printed circuit board.

[0004] Specifically, a semiconductor device is mounted on a plurality of IC sockets provided on a test board, and the test board is mounted on a test device (burn-in test device) to perform a burn-in test. Before a test board is mounted on a test apparatus and a burn-in test is started, a simple function test for recognizing a mounting state of a semiconductor device in an IC socket is performed. In this function test, a recognition process of “mounted” or “unmounted” of the semiconductor device in the IC socket is performed.
The configuration is such that the test results are obtained to the end only for the semiconductor device recognized as “mounted”.

[0003]

2. Description of the Related Art In a conventional function test, a signal is supplied to a contact pin of each IC socket provided on a test board, and a mounting state of a semiconductor device and an initial operation test (for example, , A simple contact check).

That is, a high / low level signal (H / L signal) is written to an input terminal of a semiconductor device, and after setting to a read mode, a high / low level output signal (H / L signal) is output from a predetermined output terminal. ) Is output, it is determined that the semiconductor device is securely mounted on the IC socket and that the semiconductor device is operating normally. When an H signal is supplied to an input terminal and a low-level output signal (L signal) is output from a predetermined output terminal, the semiconductor device is not mounted on the IC socket and the semiconductor device is defective. Was determined.

In order to mount a semiconductor device on an IC socket, an insertion / extraction device (hereinafter, referred to as an I / R device) is used. When the semiconductor device is mounted on the IC socket by the I / R device, Although rare, the semiconductor device may be mounted at an angle. In such a case,
Even if the H signal is supplied to the IC socket,
The output signal is a low-level signal (L signal) because it is not properly mounted on the socket.

For this reason, in the function test, L
When the signal is output, the following various modes occur in the recognition result of the mounting state and the pass / fail state of the semiconductor device. Although the semiconductor device is properly mounted in the IC socket, the semiconductor device itself is broken (defective).
When the L signal is output, the mounting state of the semiconductor device in the IC socket is defective. When the L signal is output, the semiconductor device is not actually mounted on the IC socket (not mounted). When a signal is output, the following three cases can be considered. In any of the cases (1) to (4), conventionally, it is treated as "unmounted (no semiconductor device)", and no test result is obtained.

When the function test and the subsequent burn-in test are completed, the semiconductor device is removed from the test board by the above-mentioned I / R device and stored in a carrier or the like. At this time, the mounting recognition result of the semiconductor device is also transmitted to the medium such as a floppy disk or the I / R device on-line. The / R device does not perform the semiconductor device removal processing. Therefore, in the above cases, the semiconductor device is left unplugged from the IC socket. Therefore, conventionally, the recognition result obtained by the function test and the I / R
A comparison is made with mounting information indicating the mounting state of the semiconductor device by the device, and if they match, it has been determined that the mounting process has been properly performed.

[0008]

However, a comparison process between the recognition result (hereinafter referred to as recognition data) obtained in the above function test and the mounting information (hereinafter referred to as mounting map data) from the I / R device. Can download the mounting map data from the I / R device side to the test device side in advance, and recognize the mounting state of the semiconductor device (the presence or absence of the semiconductor device) only by comparing and comparing the mounting map data with the recognition data.

At this time, if the test device and the I / R device are not online, the test data cannot be directly compared on the test device side, so the test board is pulled out from the test device once. A comparison check between the mounting map data issued by a printer or the like and the actual mounting state of the test board has been performed visually. As another method, the recognition data and the mounting map data are stored on a floppy disk, and are stored in another server for comparison and verification.

[0010] However, all of these methods are troublesome, resulting in a decrease in test efficiency. In addition, in the case of a visual comparison check, a human error may occur, and the reliability of the recognition process is reduced. on the other hand,
Even if the test device and the I / R device can be brought online, there is no problem if the semiconductor device is recognized as a non-defective product and the mounting position is also recognized as an appropriate position. If it is determined that the semiconductor device is defective due to defective contact characteristics, the semiconductor device is moved to another empty socket where no defect has occurred (the first time, the unmounted socket). In such a case, it is necessary to change the registration of the mounting map data obtained from the online information. This registration change process can only be performed manually, and thus there is the danger of registration errors during data registration (change) work.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a test board for a semiconductor device capable of performing a test with high reliability while facilitating a test process at the time of a test. .

[0012]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means. The invention according to claim 1, wherein a substrate, a plurality of pedestals mounted on the substrate, a pedestal on which the semiconductor device is mounted, and a contact member electrically connected to an external connection terminal provided on the semiconductor device. A semiconductor device test board provided with a socket comprising: a mounting state recognition device for recognizing a mounting state of the semiconductor device.

According to a second aspect of the present invention, in the semiconductor device test board according to the first aspect, the pedestal configured to displace the mounting state recognition device by mounting the semiconductor device; A switch element is provided below the pedestal and outputs a signal in accordance with the displacement of the pedestal.

According to a third aspect of the present invention, in the test board for a semiconductor device according to the second aspect, the switch element includes at least two or more conductive pogo pins. According to a fourth aspect of the present invention, in the semiconductor device test board according to the third aspect, a conductive region and an insulating region are formed in the conductive pogo pin, and the conductive pogo pin is partially connected to the pedestal. Forming a connection region, with the displacement of the pedestal accompanying the mounting of the semiconductor device, the connection region is electrically connected to the conductive region in a state where the semiconductor device is properly mounted, and the semiconductor device is further pushed in The connection region is located in the insulating region in a state of being separated.

According to a fifth aspect of the present invention, in the test board for a semiconductor device according to any one of the first to third aspects, the pedestal is divided into a plurality of pedestals, and the pedestal is divided for each of the divided pedestals. A mounting state recognition device is provided. According to a sixth aspect of the present invention, in the test board for a semiconductor device according to the fifth aspect, the test board receiving stand provided in a mounting apparatus for mounting the printed board or the semiconductor device in the socket, A connection pattern for forming a closed loop circuit by connecting the mounting state recognition devices respectively disposed in a plurality of sockets in a closed loop is provided, and the mounting state of the semiconductor device is determined based on a signal output from an end of the closed loop circuit. Is recognized.

According to a seventh aspect of the present invention, in the test board for a semiconductor device according to the fifth aspect, the mounting state recognition device provided in each of the plurality of sockets provided on the printed circuit board. In addition, a common power supply line for collectively supplying power is provided, and individual signal lines for individually extracting signals from the individual mounting state recognition devices are provided.

According to a eighth aspect of the present invention, in the test board for a semiconductor device according to any one of the first to seventh aspects, based on a signal output from the mounting state recognition device on the printed circuit board. And a mounting state recognizing circuit for recognizing a mounting state of the semiconductor device.

Each of the above means operates as follows.
According to the first aspect of the present invention, the mounting state recognition device that recognizes the mounting state of the semiconductor device is provided on the base.
For each semiconductor device to be mounted, “unmounted (no semiconductor)”, “defective product (fault of semiconductor device, etc.)”, and “unstable mounting state (for example, tilted mounting)” are distinguished. Automatic recognition becomes possible. As a result, even when the semiconductor device is mounted at an angle with respect to the socket, it is determined that the semiconductor device is mounted.

Therefore, the semiconductor device is no longer recognized as "unmounted" even though it is mounted, and a visual test and data storage processing on a floppy disk which have been required conventionally can be eliminated. Simplification of recognition process,
Efficiency and reliability can be improved. Also,
A signal for performing an operation test can be supplied only to a normally mounted semiconductor device, and the accuracy of the operation test of the semiconductor device can be improved.

According to the second aspect of the present invention, the mounting state recognition device is constituted by the pedestal configured to be displaced by mounting the semiconductor device and the switch element for outputting a signal in accordance with the displacement of the pedestal. Thus, the mounting state of the semiconductor device can be reliably recognized with a simple configuration. According to the third aspect of the present invention, since the switch element is constituted by at least two or more conductive pogo pins, the mounting state of the semiconductor device can be changed to “high level” or “low level” of the two or more conductive pogo pins. Recognition can be performed from the state, and recognition processing can be facilitated.

According to the fourth aspect of the present invention, with the displacement of the pedestal accompanying the mounting of the semiconductor device, the connection region is electrically connected to the conductive region of the conductive pogo pin when the semiconductor device is properly mounted. The configuration in which the connection region of the conductive pogo pin is located in the insulating region while the semiconductor device is further pushed in allows an electrical connection between the connection region of the pedestal and the conductive region of the conductive pogo pin to be mounted. Can be recognized. When the semiconductor device is completely mounted, the connection region of the conductive pogo pin is located in the insulating region of the pedestal. Therefore, after the recognition process is completed, the wiring connected to the conductive pogo pin is in a free state (for the recognition process). Is a free state that is not used). For this reason, after the recognition processing, this wiring can be used as a signal line wiring, so that the use efficiency of the wiring can be improved and the number of wirings can be reduced.

According to the fifth aspect of the present invention, the pedestal is divided into a plurality of parts, and the mounting state recognizing device is provided for each of the divided pedestals. Recognition can be performed more accurately, and recognition accuracy can be improved. Further, according to the invention of claim 6, a connection pattern for forming a closed loop circuit by connecting the mounting state recognition devices respectively arranged in the plurality of sockets in a closed loop is provided, and an output from an end of the closed loop circuit is provided. Is configured to recognize the mounting state of the semiconductor device on the basis of the received signal, the mounting state of the semiconductor device provided in each of the plurality of sockets can be detected with a small number of wires, and the wiring can be easily formed. And the test efficiency can be improved.

In the case where a connection pattern is provided on a test board pedestal provided on a mounting apparatus for mounting a semiconductor device on a socket, the semiconductor device may be mounted on a test board mounted on the test board pedestal. In other words, it is possible to recognize the mounting state of the semiconductor device before mounting the test board on the test apparatus. Therefore, it is not necessary for the test device that performs the test such as the pan-in to perform the process of recognizing the mounting state of the semiconductor device, and the efficiency of the test can be improved.

According to the seventh aspect of the present invention, a common power supply line for collectively supplying power to a mounting state recognition device provided on each of a plurality of sockets provided on a printed circuit board is provided. By providing the individual signal wiring for individually extracting a signal from each mounting state recognition device, it is possible to immediately identify a socket determined to be “unstable in the mounting state”.

According to the eighth aspect of the present invention, a mounting state recognizing circuit for recognizing a mounting state of a semiconductor device based on a signal output from a mounting state recognizing device is provided on a printed circuit board. In other words, by providing the mounting state recognition circuit on the test board side, it is possible to simplify the device configuration on the test device side to which the test board is connected and reduce the recognition processing.

[0026]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an enlarged main part of a test board 10A according to a first embodiment of the present invention. The test board 10A is roughly the IC socket 1
1 and a printed circuit board 12. Although only one IC socket 11 is shown in FIG. 1, a plurality of IC sockets 11 (for example,
2).

The IC socket 11 mounts the semiconductor device 1, and roughly includes a contact pin 13 electrically connected to the lead 2 of the semiconductor device 1,
Mounting state recognition device 14 (hereinafter, referred to as the mounting state)
(Hereinafter simply referred to as a recognition device). The same number of the contact pins 13 as the leads 2 are provided, and are configured to have a spring property by being curved to generate a contact pressure.

The recognition device 14 includes a pedestal 15 and a conductive pogo pin 16 (hereinafter, pogo pin). The pedestal 15 is configured to contact the bottom surface of the semiconductor device 1 to be mounted. In the present embodiment, the pedestal 15 is configured to be able to move up and down in the figure as the semiconductor device 1 is mounted. Pogo pin 16 is pedestal 1
A plurality (two in the example shown in FIG. 1) is provided below the pedestal 5, and the pedestal 15 moves down with the mounting of the semiconductor device 1, and conducts when the semiconductor device 1 is mounted to a predetermined mounting position. It has a configuration.

FIG. 2 shows a specific example of the recognition apparatus (first embodiment).
Is shown. In the recognition device 14 </ b> A shown in FIG. 4, a pair of pads 20 is formed on the printed board 12. Of the pair of pads 20, the pad 20 located on the left side in the figure is an input-side pad, to which a reference voltage (high (H) signal) is applied. Further, a pad 20 located on the right side in the drawing is an output side pad, and is connected to a test device (not shown).

A conductive plate 19 is provided on the lower surface of the pedestal 15A.
Are configured to extend downward. Pogo pin 1
6, a bar-shaped conductive region 17 is formed at a position facing the pad 20 and an insulating region 18 is formed between the conductive region 17 and the conductive plate 19. Also,
The conductive regions 17 respectively formed on the pair of pogo pins 16 are electrically connected by a conductive plate 19.

In the recognition device 14A having the above configuration,
When the semiconductor device 1 is normally mounted, the pedestal 15A moves down while maintaining the horizontal state, and thus the conductive regions 17 formed on the pair of pogo pins 16 as shown in FIG.
Are connected to a pair of pads 20 formed on the printed circuit board 12, respectively, so that the pair of pads 20 is conducted. As a result, the output side pad 20 located on the right side in FIG.
Becomes high level.

On the other hand, when the semiconductor device 1 is mounted on the IC socket 11 in an inclined state, the pedestal 15A is also in an inclined state. In this state, the pair of pogo pins 16 are not connected to the pair of pads 20, and the output side pad 20 located on the right side in the drawing maintains the low level. Therefore, by detecting the output state of the wiring connected to the output side pad 20, it can be recognized that the semiconductor device 1 has been properly mounted.

FIGS. 3 to 7 show various embodiments of the pogo pin used in the recognition device. The pogo pin 21A shown in FIGS. 4 to 5 is roughly composed of a head portion 23A, a shaft 24, a spring 25, a spacer 26, an E-ring 27, and the like. The head portion 23A is made of, for example, a conductive metal having a body portion having a cylindrical shape and a tip portion having a spherical shape. A shaft 24 made of an insulating material is press-fitted into the center of the head 23A. A spring 25, a spacer 26, and an E-ring 27 are inserted through the shaft 24 from above.

The spacer 26 and the E-ring 27 are formed of an insulating material. An insulator 28 is provided at a position of the head portion 23A where the spring 25 abuts so that a pad 29 described later and the head portion 23A do not conduct through the spring 25. The pogo pin 21A is connected to the IC socket 11
, The head portion 23A is vertically slidably inserted into the insertion hole 22 formed in the IC socket 11, and the shaft 24 is inserted into the insertion hole formed in the printed circuit board 12. . In this mounted state, the spring 25 and the spacer 26 are located above the printed circuit board 12, and the E-ring 27 is located below the printed circuit board 12. Further, the printed circuit board 12
Is formed with a pad 29, which is configured to face the lower end of the head portion 23A.

FIG. 3A shows the pogo pins 21A before the semiconductor device 1 is mounted. As shown in the figure,
Before the semiconductor device 1 is mounted, the head portion 23 </ b> A slightly protrudes from the upper surface of the IC socket 11 by the elastic force of the spring 25. On the other hand, the semiconductor device 1
Is mounted, the bottom surface of the semiconductor device 1 (or
The head 23A moves down against the elastic force of the spring 25 (by the pedestal), and the lower end of the head 23A is electrically connected to the pad 29 formed on the printed circuit board 12 as shown in FIG. Connecting. Therefore, for example, the pad 2 on the left side in the figure
Setting the H level to 9 makes it possible to recognize whether or not the semiconductor device 1 is mounted from the output of the pad 29 on the right side in the figure.

In the example shown in FIGS. 3 and 4, the pad 29 is formed on both sides of the printed circuit board 12, but it is sufficient that the pad 29 is formed at least on the surface facing the head portion 23A. In this embodiment, the head unit 23
A has a configuration in which the body portion is cylindrical and the tip portion is spherical, but the shape of the head portion 23A is not limited to this, and a rectangular head portion 23B as shown in FIG. The head portion 23C may have a cross-shaped cross section.

On the other hand, the pogo pin 21B shown in FIG. 7 has a configuration in which a spherical portion 33 is fixed to the upper portion of the shaft 24 and a substantially spherical contact portion 34 made of a conductive material is provided in the lower portion. The spherical portion 33 is vertically movably mounted in the upper large-diameter groove 30 formed in the socket 11, and the contact portion 34 is mounted on the lower large-diameter groove 31 formed in the socket 11.
It is mounted to be able to move up and down. Further, the shaft 24 is inserted through an insertion hole formed in the small diameter portion 32, and a spring 25 for urging the spherical portion 33 upward is provided between the small diameter portion 32 and the spherical portion 33. ing. On the other hand, a pair of pads 29 is formed on the printed circuit board 12 at a position facing the contact portion 34.

FIG. 7A shows the pogo pins 21B before the semiconductor device 1 is mounted. As shown in the figure,
In a state before the semiconductor device 1 is mounted, the sphere portion 33 is configured to slightly protrude from the upper surface of the IC socket 11 by the elastic force of the spring 25. On the other hand, when the semiconductor device 1 is mounted, the spherical portion 33 moves down against the elastic force of the spring 25 by the bottom surface (or by the pedestal) of the semiconductor device 1, as shown in FIG. The contact portion 34 is electrically connected to the pad 29 formed on the printed circuit board 12. Therefore, for example, by setting the pad 29 on the left side in the drawing to H level, it is possible to recognize whether or not the semiconductor device 1 is mounted from the output of the pad 29 on the right side in the drawing.

FIG. 8 shows a second embodiment of the recognition device. In FIG. 8, components corresponding to those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted. The recognition device 14B shown in FIG. 3 has a configuration in which the pogo pins 21 are formed upright on pads of the printed circuit board 12. Further, a groove 35 is formed in the pedestal 15B, penetrating the conductive plate 19 (connection region) and reaching the pedestal 15B itself (the pedestal 15B is formed of an insulating material).

FIG. 8A shows a state before the semiconductor device 1 is mounted in the recognition device 14B having the above configuration. In this state, the pogo pin 21C is
B and the conductive plate 19. The pogo pin 21C is at the H level on the left side in the figure. When the semiconductor device 1 is mounted from the state shown in FIG. 8A, the pedestal 15B moves downward. FIG. 8B shows a state where the semiconductor device 1 is mounted at a predetermined mounting position (hereinafter, referred to as a mounting state). Here, the predetermined mounting position is
All leads 2 provided on the semiconductor device 1 are IC
This refers to a state in which the socket 11 is connected to the contact pins 13 (see FIG. 1).

In this mounted state, the conductive region 17 of the pogo pin 21C is configured to be electrically connected to the conductive plate 19. Accordingly, in the mounted state, the pair of pogo pins 21C are conducted through the conductive plate 19, and the signal of the pad located on the right side in the drawing becomes H level. Therefore, from the output of the wiring connected to the pad located on the right side in the figure,
It can be recognized that the semiconductor device 1 has been mounted.

In the present embodiment, the groove 35 is
B is formed. Therefore, the semiconductor device 1 can be moved further downward than the mounting state shown in FIG. FIG. 8C shows a state where the semiconductor device 1 is further moved down from the mounted state (hereinafter, referred to as a completely mounted state). Even in this state, all the leads 2 provided on the semiconductor device 1 maintain the state of being connected to the contact pins 13 of the IC socket 11.

In the completely mounted state, the conductive region 17 of the pogo pin 21 passes through the conductive plate 19 and is located in the pedestal 15B. Since the pedestal 15B is formed of an insulating material as described above, the pair of pogo pins 21C are in a non-conductive state again in a completely mounted state. As described above, in the recognition device 14B according to the present embodiment, the semiconductor device 1
Is mounted to the mounting state, the conductive plate 19 is electrically connected to the conductive region 17 of the pogo pin 21C, thereby changing the mounting state of the semiconductor device 1 from the output state of the output side pad (the right side pad in the figure). Can be recognized. That is, when the output of the pad on the right side in the figure changes from the L level to the H level, it can be detected that the semiconductor device 1 has been mounted.

When the semiconductor device 1 is further pushed in from the mounted state, the conductive plate 19 faces the insulating region 18 of the pogo pin 21C, and the conductive region 17 is located in the pedestal 15B. In this state, the pair of pogo pins 21C are in a non-conductive state. That is, after the recognition process of the mounting state of the semiconductor device 1 is completed, the wiring connected to each pogo pin 21C is in a free state (free state). For this reason, after the recognition processing, this wiring can be used as a signal line wiring, so that the use efficiency of the wiring can be improved and the number of wirings can be reduced.

Next, the operation using the above-described recognition apparatus will be described. 9 and 10 show a recognition processing circuit that recognizes the mounting state of the semiconductor device 1. FIG. 9 is a schematic diagram showing the overall configuration of the recognition processing circuit, and FIG. 10 is an enlarged view showing two circuits (two sockets) in FIG. 9 for convenience of explanation. In the examples shown in FIGS. 9 and 10,
The pedestal 15 is divided into two, so that three pogo pins 16A-1
An example in which recognition processing is performed using 6C is shown.

The recognition processing circuit according to the present embodiment has one I
This is a very simple circuit configuration in which one AND circuit 37 and one OR circuit 38 are provided for the C socket 11. In this embodiment, the AND circuit 37 and the OR circuit 38 are arranged on the printed circuit board 12.
As described above, since the recognition processing circuit has a very simple configuration, even if the AND circuit 37 and the OR circuit 38 are provided in each of the plurality of IC sockets 11 provided on the printed circuit board 12, the test board The cost of 10A does not rise abnormally.

As described above, in this embodiment, the pedestal 15 is divided into two and three pogo pins 16A to 16C are used, but one of the pogo pins 16A is connected to the reference voltage via the voltage wiring. Connected to the source. The remaining pogo pins 16B and 16C are disposed so as to face the pedestal 15 divided into two parts. The pogo pins 16B, 16
C is connected in parallel to an AND circuit 37 and an OR circuit 38, the AND circuit 37 is connected to the test device 36 by a first signal wire 40, and the OR circuit 38 is connected to the test device 36 by a second signal wire 41. It is connected to the.

Next, a specific method of recognizing the mounting state of the semiconductor device 1 using the recognition processing circuit having the above configuration will be described. First, the semiconductor device 1 is mounted on each IC socket 11 of the test board 10A using the above-described I / R device. Next, the test board 10A on which the semiconductor device 1 is mounted is mounted on the test device 36 (see FIG. 19).

Subsequently, a reference voltage is applied to each of the pogo pins 16A from the reference voltage source provided in the test device 36 via the voltage wiring 39 to generate an H level. As described with reference to FIGS. 2 and 8, the signal output from the recognition device in this state differs depending on the mounting state of the semiconductor device 1. In the case of this embodiment, the pogo pins 16B, 16B
The output from C differs depending on the mounting state of the semiconductor device 1.

When the semiconductor device 1 is mounted on the IC socket 11, "unmounted (no semiconductor)", "normally mounted (semiconductor device is properly mounted)", "unstable mounting state (for example, tilting) 3) is conceivable. These aspects can be recognized from the output from the pogo pins 16B and 16C. That is, when the semiconductor device 1 is “not mounted” on the IC socket 11, the two pedestals are not moved down, and the pogo pin 16 is not mounted.
Neither B nor 16C is electrically connected to the pogo pin 16A which is set to the H level. Therefore, when the outputs from the pogo pins 16B and 16C are both at the L level, it can be determined that the semiconductor device 1 is not mounted on the IC socket 11.

When the semiconductor device 1 is "normally mounted" on the IC socket 11, the two pedestals are both moved down, so that the pogo pins 16B and 16C are electrically connected to the pogo pin 16A both at H level. Connect to Therefore, when the outputs from the pogo pins 16B and 16C are both at the H level, it can be determined that the semiconductor device 1 is "normally mounted" on the IC socket 11.

Further, the semiconductor device 1 is mounted on the IC socket 11 “unstable mounting state (for example, mounting is inclined)”.
In the case of (1), since the semiconductor device 1 is inclined, one seat moves down and the other pedestal does not move down. Therefore, one of the pogo pins 16B and 16C is at the H level and the other is at the L level. Therefore, pogo pins 16
When the outputs from B and 16C are different, I
The mounting state for the C socket 11 is “unstable mounting state”.
Can be determined.

The above-described mounting state recognition processing is performed in the test device 36 to which the test board 10A is connected, and the obtained mounting state recognition data is stored in a storage register in the test device 36. Then, based on the mounting state recognition data, the test device 36 supplies a semiconductor control signal only to the semiconductor device 1 that has been “normally mounted” and performs the main test. As a result, the semiconductor device 1 that has been mounted but is “unstable in mounting state” is not subjected to the test, and thus the semiconductor device 1 that has been “normally mounted” due to the semiconductor device 1 in “unstable mounting state”. It is possible to prevent adverse effects on the test results.

Further, in the above configuration, each of the circuits 3 for performing the recognition process of the mounting state of the semiconductor device 1 on the printed board 12
With the provision of 7 and 38, it is possible to simplify the device configuration on the test device 36 side to which the test board 10A is connected and to reduce the recognition processing. In the present embodiment, the above-described determination processing is performed in the test device 36 to which the test board 10A is connected.
By connecting the test board 10A to an I / R device, the I / R device can be configured to perform the above-described determination processing (generally, an I / R for a semiconductor device).
The R device has an arithmetic function).

FIGS. 11 to 13 show display examples of mounting state recognition data obtained by performing the mounting state recognition processing of the semiconductor device 1 described above. Note that, in the examples shown in FIGS. 11 to 13, a test board on which twelve semiconductor devices 1 can be simultaneously mounted is shown as an example. Numerals (1 to 12) shown in each drawing are position numbers of mounting positions where the semiconductor device 1 is mounted.

FIG. 11A shows all mounting positions 1 to 12
Shows a state in which the semiconductor device 1 is “unmounted”. In the present embodiment, "."
Is used. FIG. 11B shows a state in which the semiconductor device 1 is in “normal mounting” (Full mounting) in all mounting positions 1 to 12. In the present embodiment, “M” is used to indicate “implement”.

FIG. 12 shows a display example of mounting state recognition data by a conventional mounting state recognition process for convenience of explanation. The example illustrated in FIG. 12A illustrates a case where “unmounted” is present at the mounting positions 4, 8, and 12. Also,
FIG. 12B shows a case where there is “unmounted” at the mounting positions 4, 8, and 12, and there is “unstable mounting state” at the mounting position 3. In the conventional mounting state recognition process, “unmounted” in which the semiconductor device 1 is not mounted in the first place and “unstable mounting state” in which the semiconductor device 1 is mounted but its mounting state is inclined are distinguished. I couldn't do that. For this reason, conventionally, as shown in FIG. 12B, the display “•” of “not mounted” is attached to the mounting position 3 in spite of the fact that the mounting state is actually “unstable”.

FIG. 12C shows a case where a burn-in test (BI) is performed after the completion of the mounting state recognition processing and a failure (Fail) occurs in the semiconductor device 1 at the mounting position 7. As shown in the figure, when "Fail" occurs in the semiconductor device 1, "f" indicating "Fail" is added to the mounting position 7 of the semiconductor device. On the other hand, FIG. 13 shows a display example of mounting state recognition data by the mounting state recognition processing according to the present embodiment. FIG.
The example shown in (A) shows a case where “unmounted” is present at the mounting positions 4, 8, and 12, as in the conventional FIG. 12A described above.

FIG. 13B shows mounting positions 4, 8, and
12 shows a case where there is “unmounted” and a mounting position 3 has “unstable mounting state”. In the present embodiment, the recognition devices 14A and 14B that recognize the mounting state of the semiconductor device 1 are provided, so that the IC socket 11
Can be recognized independently of the mounting state of the semiconductor device 1. Therefore, in the present embodiment, the display “x” indicating that the mounting state is “unstable” is attached to the mounting position 3. As a result, according to the present embodiment, “unmounted” and “unstable mounting state”, which could not be determined in the past, can be clearly determined.

Therefore, the semiconductor device 1 is no longer recognized as “not mounted” even though the semiconductor device 1 is mounted, and the visual test and the data storing process to the floppy disk which are conventionally required can be eliminated. In addition, the recognition processing can be facilitated, the efficiency can be improved, and the reliability can be improved. Also, only for the semiconductor device 1 that is normally mounted,
A signal for performing an operation test can be supplied, and the accuracy of the operation test of the semiconductor device 1 can be improved.

Further, at the time of mounting processing (at the time of mounting processing using an I / R device), the semiconductor device 1 which is determined to be “unstable in mounting state”
Then, by thoroughly removing the semiconductor device in the “unstable mounting state” from the test board, all the semiconductor devices 1 remaining on the test board become “normally mounted”. Therefore, mounting from the first time (good product:
Since the test results are obtained to the end only for the semiconductor device that has been recognized as "Pass", the I / R device will not be left unchecked.

FIG. 13 (C) is the same as FIG.
As in (C), a case is shown in which a burn-in test (BI) is performed after the completion of the mounting state recognition processing, and a failure (Fail) occurs in the semiconductor device 1 at the mounting position 7. FIG.
FIG. 9 is an enlarged view showing a main part of a test board 10B according to a second embodiment of the present invention. In FIG.
2 shows an enlarged view of the IC socket 42 disposed on the upper side 2.

FIG. 15 is an enlarged view of the recognition device 14C provided in the IC socket 42. The recognition device 14C according to the present embodiment divides a pedestal on which the semiconductor device 1 is mounted into a plurality of (in this embodiment, nine) pedestals, and mounts the mounting state recognition device on each of the divided pedestals 43-1 to 43-9. The pogo pins 44A-1 to 44A-9 and 44B-1 to 44B-9 functioning as a unit are provided. A conductive plate 19 is provided on the bottom of each of the pedestals 43-1 to 43-9.

Further, between the adjacent pedestals 43-1 and 43-2, the pogo pins 44B-1 and 44A-2 are connected and connected.
45, and between the next adjacent pedestals 43-2 and 43-3, a pogo pin 44B-2 and a pogo pin 44A-3 are connected by a connection wiring 45, and this connection is made to all the pedestals 43-1 to 43-3. -9
It is done in. Therefore, when the semiconductor device 1 is properly mounted (“normal mounting”), the pedestals 43-1 to 43-9
The conductive plate 19 of all the pogo pins 44A-1 to 44A-9, 4
A closed loop circuit is formed to make contact and conduct with 4B-1 to 44B-9. Therefore, in the case of "normal mounting", when the voltage wiring 46 is set to the H level, the output wiring 47 is also set to the H level, whereby "normal mounting" can be detected.

On the other hand, when the semiconductor device 1 is not properly mounted (in the case of “unstable mounting state”), one of the plurality of divided pedestals 43-1 to 43-9 does not move down. Becomes That is, as shown in FIG. 16A, in the case of “normal mounting”, all the pedestals 43-1 to 43-9 (in the figure,
Only the pedestals 43-1 to 43-3 are pressed by the semiconductor device 1 and all the pogo pins 44A-1 to 44A-9 and 44B-1 to
44B-9, but in the case of "unstable mounting state", as shown in FIG. 16B, one of the pedestals (the pedestals 43-1 and 43-2 in FIG. 16) is securely connected. Pogo pins 44A-1 and 44B-1, and Pogo pins 44A-2 and 44B
-2 is not connected.

In this case, the above-mentioned closed loop circuit is not formed, and therefore, even if the voltage wiring 46 is set to the H level, the output wiring 47 is also set to the L level. Therefore, it is possible to detect “unstable mounting state”. Further, by dividing the pedestal into a plurality as described above, the semiconductor device 1
Can be detected for any inclination of the semiconductor device 1, so that the mounting state of the semiconductor device 1 can be more accurately recognized, and the recognition accuracy can be improved.

FIG. 17 shows the structure of the twelve ICs configured as described above.
A test board 10B having a configuration in which sockets 42-1 to 42-12 are arranged on a printed circuit board 12 is connected to an adapter-type test board receiving stand (test board 10) provided in an I / R device.
B, which is located on the back side and does not appear in the figure). In this embodiment, each IC socket 42-1 to
42-12 for the conductive pogo pins 44C-1 to 44C-12 respectively
(Shown in black in the figure. In the figure, the reference numeral is assigned only to the steer conductive pogo pin 44C-1). In addition, the adapter-type test board support
A connection pattern 48 for connecting the C sockets is formed.

Specifically, the IC sockets 42-1 and 42-2
The connection pattern 48 connects the pogo pin 44B-9 provided on the IC socket 42-1 and the conductive pogo pin 44C-2 provided on the IC socket 42-2. Also, the next adjacent IC sockets 42-2 and 42-3
Between them, the pogo pins 44B-9 provided on the IC socket 42-2 and the conductive pogo pins 44C-3 provided on the IC socket 42-3 are connected by the connection pattern 48. This connection is made for all IC sockets 42-1 to 42
-12.

Therefore, all the IC sockets 42-1 to 42-2
-12, the semiconductor device 1 is properly mounted (“normal mounting”), the individual IC sockets 42-1 to 4-4
2-12, the conductive pogo pins 44C-1 to 44C-4
4C-12 and the pogo pins 44B-9 are electrically connected, and in all the IC sockets 42-1 to 42-12, all the IC sockets 42-1 to 42-12 are connected via the connection pattern 48.
Electrically conduct to form a closed loop circuit. Therefore,
In the case of "normal mounting", the conductive pin 4 of the IC socket 42-1 located at one end of the closed loop circuit is connected.
When 4C-1 is set to the H level, the pogo pin 44B-9 of the IC socket 42-12 located at the other end of the closed loop circuit also becomes the H level, whereby "normal mounting" can be detected.

As described above, according to the configuration of the present embodiment, the mounting state of the semiconductor device 1 disposed in each of the plurality of IC sockets 42-1 to 42-12 can be detected with a small number of wirings. Wiring formation can be facilitated and the test efficiency can be improved. In the configuration of the present embodiment, since the connection pattern 48 is provided on the adapter-type test board pedestal provided on the I / R device on which the test board 10B is mounted, the connection pattern 48 is provided when the semiconductor device 1 is mounted on the test board 10B. That is, before mounting the test board 10B on the test device 36, the mounting state of the semiconductor device 1 can be recognized (in this case, the I / R device includes a circuit for performing the mounting state recognition process). Need to be). Therefore, it is not necessary for the test device that performs the test such as the pan-in to perform the process of recognizing the mounting state of the semiconductor device, and the efficiency of the test can be improved.

FIG. 18 shows a test board 10C according to a third embodiment of the present invention. The test board 10C according to the present embodiment collectively supplies power to a mounting state recognition device (not shown) provided in each of the plurality of sockets 42-1 to 42-12 provided on the printed circuit board 12. A common power supply wiring 49 is provided, and individual sockets 42-1 to
42-12 An individual signal wiring 50 for individually extracting a signal from the (mounting state recognition device) is provided.

As described above, the individual sockets 42-1 to 42-2
By pulling out the individual signal wiring 50 from -12, the mounting state can be recognized for each of the sockets 42-1 to 42-12. Therefore, it is possible to immediately identify a socket determined to be “unstable in the mounting state”, and it is not necessary to perform a process of confirming an individual mounting state, thereby improving test efficiency.

[0073]

According to the present invention as described above, the following various effects can be realized. According to the first aspect of the present invention, it is no longer recognized as "unmounted" despite the fact that the semiconductor device is mounted, eliminating the need for a visual test and data storage processing to a floppy disk, which were conventionally required. Can make the recognition process easier, more efficient,
In addition, reliability can be improved. Further, a signal for performing an operation test can be supplied only to a normally mounted semiconductor device, and the accuracy of the operation test of the semiconductor device can be improved.

According to the second aspect of the present invention, the mounting state of the semiconductor device can be reliably recognized with a simple configuration. Further, according to the third aspect of the present invention, the mounting state of the semiconductor device is set to “ON” by two or more conductive pogo pins,
Recognition can be performed from the "off" state, and recognition processing can be facilitated.

According to the fourth aspect of the present invention, after the recognition processing is completed, the wiring connected to the conductive pogo pins is in a free state (a free state not used for the recognition processing). This wiring can be used later as a signal line wiring, which can improve the use efficiency of the wiring and reduce the number of wirings. Further, according to the invention described in claim 5, it becomes possible to more accurately recognize the mounting state of the semiconductor device at the time of mounting, and it is possible to improve the recognition accuracy.

According to the sixth aspect of the present invention, the mounting state of the semiconductor device provided in each of the plurality of sockets can be detected with a small number of wires, thereby facilitating the wiring formation and improving the test efficiency. Can be improved. In addition, if a connection pattern is provided on a test board holder provided on a mounting device that mounts a semiconductor device on a socket, it is possible to recognize the mounting state of the semiconductor device before mounting the test board on the test device. This makes it unnecessary to perform a process of recognizing the mounting state of the semiconductor device on the test device side that performs a test such as a pan-in test, thereby making it possible to increase the efficiency of the test.

Further, according to the invention described in claim 7, a socket determined to be “unstable in mounting state” can be immediately specified. According to the eighth aspect of the present invention, since the mounting state recognizing circuit is provided on the test board side, it is possible to simplify the device configuration on the test device side to which the test board is connected and to reduce the recognition processing. .

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram of a test board according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the configuration and operation of a first embodiment of a recognition device provided on a test board;

FIG. 3 is a view for explaining an example of a pogo pin provided in the recognition device (part 1).

FIG. 4 is a diagram for explaining a pogo pin provided in the recognition device (a cross-sectional view in FIG. 3).

FIG. 5 is a diagram for explaining pogo pins provided in the recognition device (the configuration diagram of FIG. 3).

FIG. 6 is a view showing a modified example of a head portion constituting a pogo pin.

FIG. 7 is a view for explaining another example of the pogo pin provided in the recognition device (part 2).

FIG. 8 is a diagram for explaining the configuration and operation of a second embodiment of the recognition device provided on the test board.

FIG. 9 is a diagram showing a state where a test board is connected to a test apparatus.

FIG. 10 is a diagram illustrating a circuit configuration of a recognition device.

FIG. 11 is a diagram for explaining a conventional mounting state recognition processing method.

FIG. 12 is a diagram for explaining a conventional mounting state recognition processing method.

FIG. 13 is a diagram for explaining a specific mounting state recognition processing method using the recognition device according to the present embodiment.

FIG. 14 is a main part configuration diagram of a test board according to a second embodiment of the present invention.

FIG. 15 is a diagram illustrating a configuration of a third embodiment of the recognition device provided on the test board.

16 is a diagram for explaining the operation of the recognition device shown in FIG.

FIG. 17 is a plan view of a test board according to a second embodiment of the present invention.

FIG. 18 is a plan view of a test board according to a third embodiment of the present invention.

FIG. 19 is a diagram illustrating a state where the test board is mounted on a test device.

[Explanation of symbols]

Reference Signs List 1 semiconductor device 2 lead 10A to 10C test board 11, 42, 42-1 to 42-12 IC socket 12 printed board 13 contact pin 14, 14A to 14C recognition device 15A, 15B, 43-1 to 43-9 pedestal 16, 16A-16C, 44A-1-44A-9, 44B-1
To 44B-9 Pogo pin 17 Conductive area 18 Insulating area 19 Conductive plate 20 Pad 23A to 23C Head part 33 Spherical part 34 Contact part 35 Groove part 36 Test device 37 AND circuit 38 OR circuit 39, 46 Voltage wiring 40 First signal wiring 41 Second signal wiring 44C-1 to 44C-12 Steady conductive pogo pin 45 Connection wiring 47 Signal wiring 48 Connection pattern 49 Common voltage wiring 50 Individual signal wiring 51 Voltage terminal 52-1 to 52-4 Individual signal terminal

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Katsumi Kumazawa 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Toshiaki Tominaga 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. (72) Inventor Tomokazu Kitaoka 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 1 Within Fujitsu Co., Ltd. 1-chome No. 1 Fujitsu Limited F-term (reference) 2G003 AA07 AE01 AG01 AG10 AG10 AG13

Claims (8)

[Claims] 1. A semiconductor device comprising: a substrate; a plurality of pedestals provided on the substrate, on which a semiconductor device is mounted; and contact members electrically connected to external connection terminals provided on the semiconductor device. A test board for a semiconductor device, comprising: a socket having a mounting state recognition device for recognizing a mounting state of the semiconductor device. 2. The test board for a semiconductor device according to claim 1, wherein the mounting state recognition device is disposed under the pedestal and configured to be displaced by mounting the semiconductor device, A test board for a semiconductor device, comprising: a switch element that outputs a signal according to displacement of a pedestal. 3. The test board for a semiconductor device according to claim 2, wherein said switch element comprises at least two or more conductive pogo pins. 4. The test board for a semiconductor device according to claim 3, wherein a conductive region and an insulating region are formed in the conductive pogo pin, and a connection region partially connected to the conductive pogo pin is formed in the pedestal. With the displacement of the pedestal accompanying the mounting of the semiconductor device, the connection region is electrically connected to the conductive region when the semiconductor device is properly mounted, and the connection is performed when the semiconductor device is further pushed in. A test board for a semiconductor device, wherein a region is located in the insulating region. 5. The test board for a semiconductor device according to claim 1, wherein the pedestal is divided into a plurality of parts, and the mounting state recognition device is provided for each of the divided pedestals. Characteristic test board for semiconductor devices. 6. The test board for a semiconductor device according to claim 5, wherein the plurality of sockets are respectively provided on a test board holder provided on the printed board or a mounting device for mounting the semiconductor device on the socket. A connection pattern for forming a closed loop circuit by connecting the mounted mounting state recognition devices provided in a closed loop is provided, and the mounting state of the semiconductor device is recognized based on a signal output from an end of the closed loop circuit. A test board for a semiconductor device, comprising: 7. The test board for a semiconductor device according to claim 5, wherein a common power supply collectively supplies power to the mounting state recognition devices provided in the plurality of sockets provided on the printed circuit board. A test board for a semiconductor device, comprising: a wiring; and an individual signal wiring for individually extracting a signal from each of the mounting state recognition devices. 8. The test board for a semiconductor device according to claim 1, wherein the mounting state of the semiconductor device is recognized on the printed circuit board based on a signal output from the mounting state recognition device. A test board for a semiconductor device, comprising a mounting state recognition circuit for performing processing.