JP2000188394A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent diffusion of impurity from a gate to a channel and to reduce gate leakage current. SOLUTION: A semiconductor device having a MISFET is provided with sidewalls 6 on both sides of a gate electrode 3. The main surface of the semiconductor substrate 1 between the sidewalls is made into a groove form lower than the main surface of the semiconductor substrate in a source region and a drain region 5. In the manufacture method, a dummy gate electrode and a sidewall are formed in a gate electrode forming region on the main face of the semiconductor substrate, and impurity is implanted on the gate electrode or the sidewall by self-matching, so as to anneal it. The source region and the drain region are formed, and an insulating film 7 covering the dummy gate electrode, the source region and the drain region are flattened and the dummy gate electrode exposed by the flattening processing is selectively removed. As a result, the gate insulating film 4 and the gate electrode 3 are formed on the exposed main surface of the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to miniaturization of a device structure.

[0002]

2. Description of the Related Art Since a semiconductor device has advantages such as high speed, low cost, small size and light weight, it is required to increase the degree of integration by miniaturization. Also, the semiconductor device
Higher integration, lighter weight, and smaller size are achieved by the reduction of the device structure accompanying the advancement of microfabrication technology, and at the same time, higher speed and lower power are brought about by the reduction of the wiring length or the reduction of the operating current due to the reduction of the device structure. And other characteristics have been improved.

In such miniaturization, the scale of the device itself has been reduced, and the dimensions in the horizontal and vertical directions have been reduced. With respect to such scaling, in the MIS device, various device parameters (channel length, channel width, junction depth, lateral diffusion distance, gate oxide film thickness) accompanying the reduction are changed based on a certain factor, and the A scaling theory for predicting an improvement in performance by increasing the degree of integration and high integration has been considered, and the performance improvement by miniaturization up to now substantially conforms to this scaling theory. Therefore, reduction of the device structure is considered to be effective for improving performance in the future.

[0004] However, the improvement of the characteristics accompanying the shrinking of the device structure has been gradually gradual.
This tendency is due to the short channel MIS (Metal Insulato
r Semiconductor) FET (Field Effect Transistor)
Is remarkable.

FIG. 1 shows a schematic flow of a conventional MISFET forming process. First, a gate insulating film is formed on the main surface of the semiconductor substrate subjected to element isolation, a gate electrode is formed by patterning polycrystalline silicon or the like, and an end of the gate electrode is repaired and oxidized. The low concentration regions of the source region and the drain region are implanted by self-alignment to form sidewalls on the gate electrode, and the sidewalls are implanted with the impurities by self-alignment to form high concentration regions of the source and drain regions. Then, annealing for activating impurities and removing defects in the implanted source region and drain region is performed, an insulating film covering the gate electrode and the source region and the drain region is deposited, planarization is performed, and an opening is formed in the insulating film. A contact for forming the provided connection electrode is formed. In addition, a structure in which the junction depth is reduced by using an elevated source region, a drain region, or the like in connection with the formation of a contact silicide has been proposed.

In the development of a complementary (CMOS) semiconductor integrated circuit device in the future, in order to advance the miniaturization and performance improvement of the MISFET such as high integration, low power consumption, and high speed (high driving current), Dual gate, SAC (Self-Ali
Assuming a self-aligned S / D contact structure by gned contact hole, formation of an ultra-thin gate insulating film, prevention of boron leakage from a p-type gate electrode, ultra-shallow low-resistance source region,
A drain region forming process is required.

As a gate insulating film of a general device, an oxide film by thermal oxidation, a nitrided oxide film, or a reoxynitride oxide film is used. These are pure SiO ₂ films which do not contain nitrogen intentionally or NH ₃ , N ₂ O, NO
This is a silicon oxide film to which nitrogen is added at a concentration of less than 10% by heat treatment in a gas or the like.

In a special device such as an MNOS nonvolatile memory, for example, a laminated film of a Si ₃ N ₄ film and a SiO ₂ film is used as a gate insulating film to form an electron trap at a nitride film or an interface between a nitride film and an oxide film. The memory function is realized by charging and discharging electric charges. The same type of laminated film is also used as an interlayer film between a floating gate and a control gate of a flash memory. An ONO film further laminated with an oxide film may be used for the same purpose.

[0009]

However, if the gate insulating film is to be made thinner than about 3 nm in terms of SiO ₂ , the conventional process has the following problems. As a first problem, when polycrystalline silicon is used for the gate electrode, it is necessary to reduce the resistance, so that the impurity concentration is set to be high. In addition, a dual gate technology using an n-type gate electrode and a p-type gate electrode in a semiconductor device having a complementary (CMOS) configuration is known. In order to obtain a high impurity concentration of the mold, B is used as an impurity.

[0010] In forming the source and drain regions, a shallow junction is generally formed by impurity implantation and annealing. Since the source and drain regions are formed after the formation of the gate electrode, the source and drain regions are formed. The heat load at the time is also added to the gate structure.

When a thermal oxide film is used as the gate insulating film, impurities in the p-type gate electrode, particularly B, easily pass through the gate insulating film mainly due to the heat load when the source region and the drain region are formed. As a result, it becomes difficult to deteriorate the reliability and stability of the gate insulating film and to control the threshold value of the threshold value.

In order to solve this problem, the use of a nitrided oxide film or a reoxynitride film has a certain effect as compared with a simple oxide film. Techniques for using a film containing nitrogen as a gate insulating film are described in, for example, JP-A-9-313393, JP-A-7-254704, and JP-A-8-31.
No. 958, Japanese Patent Application Laid-Open No. 5-145069, and the like.

However, these methods do not fundamentally solve the problem, so that further scaling will be insufficient. This is because the dopant in polycrystalline silicon must be added at a high concentration in order to minimize gate depletion, and the transmission phenomenon is nonlinearly amplified as the gate insulating film becomes thinner. The current nitrogen oxide film or reoxynitride film has a nitrogen concentration of about 10%,
This is because it becomes insufficient to prevent transmission. This problem can be solved by using a pure metal gate material having an appropriate work function and not deteriorating the reliability of the oxide film. However, the stability of transistor characteristics and the problem in manufacturing have not been solved yet.

In addition, conventionally, a nitride film is used as a gate sidewall and a gate cap in order to form a contact between a source region and a drain region in a self-aligned manner by the SAC technique. The hydrogen in the nitride film is released by the heat treatment for forming the source region and the drain region, so that there is a problem that the diffusion of B in the oxide film to the substrate side is greatly increased.

As a second problem, when the physical thickness of the thermal oxide film, the nitrided oxide film, or the reoxynitrided oxide film is thinner than about 3 nm, a tunneling current flows directly, making it difficult to reduce power consumption. . In order to deal with the first and second problems, it is advantageous to use a laminated film including a nitride film having a high impurity permeation suppression effect and a large dielectric constant. Become. That is, as can be easily understood from application to a nonvolatile memory, the nitride film stacked structure has many charge traps, and has poor reliability and stability as a general-purpose gate insulating film. The leak current also increases as compared with the oxide film. Although a metal oxide film having a higher dielectric constant than a nitride film or a laminated film thereof is suitable for solving the second problem, the same problem as the third problem still arises.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a technique capable of preventing diffusion of an impurity from a gate to a channel. Another object of the present invention is to provide a technique capable of reducing a gate leak current. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. In a semiconductor device having a MISFET composed of a drain region and a source region formed on a main surface of a semiconductor substrate and a gate electrode formed on a main surface of the semiconductor substrate via a gate insulating film, sidewalls are formed on both side surfaces of the gate electrode. The main surface of the semiconductor substrate between the side walls is formed as a groove lower than the main surfaces of the semiconductor substrate in the source region and the drain region.

In the manufacturing method, a dummy gate electrode is formed in a gate electrode forming region on a main surface of a semiconductor substrate, side walls are formed on both side surfaces of the dummy gate electrode, and self-alignment with the gate electrode or the side wall is performed. The source region and the drain region are formed by injecting impurities in the step (b), the implanted source region and the drain region are annealed, and the dummy gate electrode and the insulating film covering the source region and the drain region are planarized. A gate insulating film and a gate electrode are formed on the semiconductor substrate main surface exposed by selectively removing the dummy gate electrode exposed by the oxidation treatment.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0020]

FIG. 2 shows a MISFET as a main part of a dual-gate complementary semiconductor device according to the present embodiment.
FIG. In the figure, reference numeral 1 denotes a semiconductor substrate made of single crystal silicon or the like, 2 denotes an SGI type element isolation insulating film which divides the main surface of the semiconductor substrate 1 into each element formation region, and 3
Is a gate electrode formed on the main surface 1 of the semiconductor substrate with the gate insulating film 4 interposed therebetween, and 5 is a drain region and a source region formed on the main surface of the semiconductor substrate and composed of a low concentration region 5a and a high concentration region 5b. . The semiconductor substrate 1 includes a single wafer, a case where an epitaxial layer is formed on the surface, a case where a well is formed on the surface, and the like.

Side walls 6 made of silicon nitride are provided on both side surfaces of the gate electrode 3, and the main surface of the semiconductor substrate 1 between the side walls 6 is the main surface of the semiconductor substrate 1 on which the source region and the drain region 5 are formed. It has a shallow groove shape lower than the surface.
For this reason, the source region and the drain region 5 can have an effective shallow junction. The gate electrode 3 has a high impurity concentration of B
And a metal film 3b formed by laminating W on WN.

The gate insulating film 4 has a structure in which an oxide film of about 1 nm is laminated with an oxynitride film of about 3 nm containing nitrogen at a high concentration of 50% or more. Further, as such a gate insulating film 4, when the composition is SiNxOy, a single-layer film that satisfies (x ≧ y: x = 50% to 95%);
This single-layer film may be a stacked film in which a single-layer film of x ≦ y is stacked.

The gate electrode 3, the source region, and the drain region 5 are covered with an interlayer insulating film 7. The interlayer insulating film 7 covers the source region, the drain region 5, and the side wall 6, and is flat on the upper surface of the gate electrode 3. Of the first insulating film 7a, the flattened gate electrode 3 and the first insulating film 7a
And a second insulating film 7b covering the second insulating film 7b.

The connection wiring 8 is connected to predetermined regions of the gate electrode 3 and the source region and the drain region 5 through an opening provided in the interlayer insulating film 7.

FIG. 3 is a schematic flow chart showing the process of forming the MISFET shown in FIG. 2, and FIGS.
FIG. 6 is a vertical sectional view of a main part showing a MISFET for each step in order to explain the manufacturing method. Using FIG. 4 to FIG.
A method for manufacturing the above-described semiconductor device will be described for each manufacturing process.

First, a pad insulating film 10 serving as a protective film at the time of ion implantation is formed on the entire surface of the main surface of the semiconductor substrate 1 separated into each element forming region by an SGI type element separating film 2 by thermal oxidation. (Step a), a non-doped polycrystalline silicon layer deposited on the entire surface by thermal CVD is patterned by dry etching using a resist mask formed by photolithography, and a dummy gate electrode 9 is formed in the gate electrode formation region by the gate electrode 3.
(Step b), and B is formed on the main surface of the semiconductor substrate 1 by self-alignment with the dummy gate electrode 10.
F ₂ ions are implanted to form low concentration regions 5a of the drain region 5 and the source region 5 (step c).
This state is shown in FIG.

Next, a silicon nitride film is formed on the entire surface by a thermal decompression CVD method, and then a sidewall 6 of the dummy gate electrode 9 is formed by anisotropic etching such as RIE (step d). Semiconductor substrate 1 by self-alignment
BF ₂ ions are implanted into the main surface to form a drain region 5.
Then, a high concentration region 5b of the source region 5 is formed (step e). After the ion implantation into the drain region 5 and the source region 5, annealing for recovering implantation defects and electrically activating the implanted atoms is performed in a hydrogen atmosphere containing a small amount (10% or less) of moisture (hereinafter referred to as a WH atmosphere). ) (Step f). This state is shown in FIG.

Next, a silicon oxide film to be the first insulating film 7a is formed on the entire surface by a CVD method (step g). This state is shown in FIG. Next, the first insulating film 7a is formed by CMP.
(Step h) until the upper surface of the dummy gate electrode 9 is exposed. This state is shown in FIG. next,
The exposed dummy gate electrode 9 is selectively removed (step i). Subsequently, the pad insulating film 10 located under the dummy gate electrode 9 is selectively removed. A shallow groove is formed on one main surface by self-alignment (step j). This state is shown in FIG.

Next, thermal oxidation is performed on the surface of the shallow groove in a WH atmosphere, and an oxide film of about 1 nm is formed slowly at an oxidation rate equal to or lower than that in a dry oxygen gas atmosphere. For this reason, the accuracy of the film thickness is improved as compared with the conventional treatment under a nitrogen atmosphere. Subsequently, a process of thermally oxidizing a nitride film corresponding to a single atom deposited on the oxide film by a CVD method is repeated, so that oxynitridation containing a small amount of hydrogen while containing nitrogen at a high concentration of about 50% to 90% is repeated. A gate insulating film 4 is formed by depositing a film (step k). Subsequently, a p-type polycrystalline silicon layer 3a containing B with a high impurity concentration constituting the gate electrode 3 and a metal film 3b obtained by laminating W on WN are formed by CV.
It is formed on the entire surface by the D method (step 1). This state is shown in FIG.

The direct tunneling current decreases exponentially with respect to the physical thickness of the film. For example, 2.5n
The current value differs by one digit or more between the film of m and the film having a dielectric constant of 2 and 5 nm. Therefore, the dielectric constant of an oxynitride film containing 50% or more of nitrogen is several tens% to nearly double that of a conventional thermal oxide film, a nitrided oxide film, or a reoxynitrided oxide film. _{When the} thickness is reduced to ₂ , the physical thickness can be increased, so that the direct tunnel leak current can be drastically reduced.

In addition, the conventional nitride film formed by the CVD method has many structural defects and incorporates high density traps. However, the above-described oxynitride film of the present invention can be easily oxidized at a monoatomic layer level. Defects are repaired and traps in the film are reduced. Further, the elimination of hydrogen in the film is promoted by this oxidation. As a result, the gate leakage current, which has been a problem in the conventional nitride film or NO film, is reduced in the oxynitride film.

Next, a flattening process by CMP is performed.
Polycrystalline silicon layer 3a and metal film 3b other than gate region
Is removed to form a gate electrode 3 (step m).
An insulating film 7a is formed (Step n). This state is shown in FIG.
0 is shown.

Next, an opening exposing the connection region of the source region 5 or the drain region 5 is formed by etching using a resist mask (not shown) patterned by the photolithography technique. An opening exposing the connection region is formed (step o). This state is shown in FIG.

Thereafter, a metal such as tungsten is deposited by a sputtering method, flattened by etch back to form a plug filling the opening, a metal such as aluminum is formed on the entire surface by a sputtering method, and photolithography and etching are performed. When a wiring layer is formed by patterning and the connection wiring 8 is configured by the plug and the wiring layer, the state shown in FIG. 2 is obtained.

Thereafter, a polyimide resin film or the like for improving the α-ray soft error resistance is further applied by coating, and bonding pads serving as external terminals of the semiconductor device are opened to complete the wafer process of the semiconductor device. I do.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0037]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, since the gate electrode is formed after the formation of the source region and the drain region, it is possible to avoid applying a heat load to the gate electrode when forming the source region and the drain region. There is. (2) According to the present invention, there is an effect that a film containing nitrogen can be formed as a gate insulating film. (3) According to the present invention, the effects (1) and (2)
This has the effect of preventing impurities contained in the gate electrode from transmitting to the substrate. (4) According to the present invention, there is an effect that a shallow groove can be formed in a gate region on a main surface of a semiconductor substrate by self-alignment. (5) According to the present invention, since the main surface of the semiconductor substrate in the gate region is lower than the main surface of the semiconductor substrate 1 in which the source region and the drain region are formed due to the above effect (4), The drain region has an effect that an effective shallow junction can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic flow chart showing a conventional formation process of a MISFET.

FIG. 2 is a longitudinal sectional view showing a MISFET which is a main part of the semiconductor device according to one embodiment of the present invention.

FIG. 3 is a schematic flowchart showing a process of forming the MISFET shown in FIG. 2;

FIG. 4 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 5 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 6 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 7 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 8 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 9 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 10 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

FIG. 11 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention for each manufacturing process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate electrode, 3a ... Polycrystalline silicon film, 3b ... Metal film, 4 ... Gate insulating film, 5 ... Drain region, Source region, 5a ... Low concentration region, 5b: High concentration region, 6: Side wall, 7: Interlayer insulating film, 7a: First insulating film, 7b: Second insulating film, 8: Connection wiring, 9: Dummy gate electrode, 10: Pad insulating film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinpei Tsujikawa 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo F-term (reference) 5F040 DA06 DA13 DA25 DC01 EC02 EC04 EC07 EC12 ED03 EE04 EF02 EF11 EH02 EJ03 EK05 EL02 FA02 FA07 FB02 FB05 FC00 5F058 BA05 BA20 BC11 BF02 BF30 BF62 BF64 BJ01 BJ10

Claims (10)

[Claims] 1. An MIS comprising a drain region and a source region formed on a main surface of a semiconductor substrate, and a gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film.
A semiconductor device having an FET, wherein sidewalls are provided on both side surfaces of the gate electrode, and a main surface of the semiconductor substrate between the side walls has a groove shape lower than the main surfaces of the semiconductor substrate in the source region and the drain region. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, wherein said semiconductor device is of a complementary type having a dual gate structure, and a gate electrode including a p-type polycrystalline silicon layer having a high impurity concentration is provided. . 3. The method according to claim 1, wherein the impurity in the p-type polycrystalline silicon layer is B
The semiconductor device according to claim 2, wherein 4. The gate insulating film having a composition of S
4. The semiconductor device according to claim 1, further comprising a film made of iNxOy. 5. The semiconductor device according to claim 1, wherein said side wall is made of silicon nitride. 6. An MIS comprising a drain region and a source region formed on a main surface of a semiconductor substrate, and a gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film.
A method of manufacturing a semiconductor device having an FET, comprising: forming a dummy gate electrode in a gate electrode formation region on a main surface of a semiconductor substrate; and forming sidewalls on both side surfaces of the dummy gate electrode; Forming a source region and a drain region by implanting impurities in a self-aligned manner, annealing the implanted source region and the drain region, and forming an insulating film covering the dummy gate electrode and the source and drain regions. Performing a flattening process on the insulating film; selectively removing a dummy gate electrode exposed by the flattening process; forming a gate insulating film on the main surface of the semiconductor substrate exposed by the removing process Forming a gate electrode between the side walls; and forming an insulating film covering the gate electrode. The method of manufacturing a semiconductor device, characterized in that. 7. The semiconductor device according to claim 6, wherein said semiconductor device is of a complementary type having a dual gate structure, and is provided with a gate electrode including a p-type polycrystalline silicon layer having a high impurity concentration. Manufacturing method. 8. The p-type polycrystalline silicon layer has an impurity of B
The method for manufacturing a semiconductor device according to claim 7, wherein: 9. The gate insulating film having a composition of S
9. The method of manufacturing a semiconductor device according to claim 6, comprising a film made of iNxOy. 10. The semiconductor device according to claim 6, wherein said side wall is made of silicon nitride, and said dummy gate electrode is made of polycrystalline silicon containing no impurity. Production method.