JP2000183315A - Nonvolatile semiconductor memory and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory in which recessed part can be prevented from being formed at a source line. SOLUTION: A polysilicon film 86 is removed by etching so that the polysilicon film 86 is left on the whole face of a source line formation region 88, and one part of a floating gate is patterned. That is, the regions removed are only removal regions 92, 94, and 96 on an element separation region which are removed by etching. Thus, the polysilicon film 86 and the polysilicon film which is a control gate can be laminated on the source line formation region 88. Therefore, the thickness of the film to be etched on the source line formation region 88 can be made the same as that on a region in which a storage element is formed. At patterning the remaining part of the floating gate and the control gate, a recessed part prevented from being formed due to the excessive etching of the source line formation region 88 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device includes, for example, a flash EEPROM.
And the like, there is a structure in which source regions of a group of storage elements are connected by a source line. As a result, batch erasing of a group of storage elements becomes possible. The source line includes an impurity region formed on the main surface of the semiconductor substrate.

[0003] The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device in which a groove is not formed in a source line during patterning for forming a floating gate and a control gate, and a nonvolatile semiconductor memory device manufactured by the manufacturing method. It is to provide.

[0004]

(1) The present invention relates to a semiconductor substrate having a main surface, an active region and an element isolation region formed on the main surface, and an active region and an element isolation region formed on the active region. First and second storage elements separated from each other and having a source region formed in the active region; and an impurity region formed on the main surface, the source region of the first storage element and the second storage element having a second storage element. A method for manufacturing a nonvolatile semiconductor memory device comprising: a source line electrically connected to a source region; and (b) forming an active region and an element isolation region on a main surface; Forming a tunnel insulating film of the first and second storage elements on the active region;
(C) a step of forming a first conductor film serving as a floating gate of the first and second storage elements on the main surface so as to cover the tunnel insulating film, and (d) a region where a source line is formed Selectively etching away the first conductive film on the element isolation region so as to leave the first conductive film on the entire surface, and patterning a part of the floating gate; Forming a dielectric film of the first and second storage elements on the conductor film; and (f) forming a second conductive film on the dielectric film as a control gate of the first and second storage elements. (G) selectively etching away the first and second conductor films to pattern the remaining portion of the floating gate and the control gate; Form source regions and source lines on the surface Comprising the steps of, a.

According to the present invention, in the step (d), the first conductive film is left over the entire region where the source line is formed.
The first conductor film is selectively etched away to pattern a part of the floating gate. Therefore, after the step (f), the first and second conductor films are stacked on the entire surface of the region where the source line is formed. That is, since the first and second conductive films are left over the entire region where the source line is formed, the thickness of the film to be etched over the entire region where the source line is formed, and the first and second memories are stored. The thickness of the film to be etched on the region where the element is formed is the same. Therefore, in step (g),
When patterning the remaining portion of the floating gate and the control gate, the region where the source line is formed is not excessively etched, so that the formation of the concave portion is eliminated. When the concave portion is formed in the source line, the electric resistance of the source line increases, and the operation speed of the memory element is delayed.

A nonvolatile semiconductor memory device to which the present invention can be applied may have any structure provided with a source line including an impurity region. Therefore, the present invention can be applied to, for example, an EEPROM, a flash EEPROM, and an EPROM. The following nonvolatile semiconductor memory device also has this meaning.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, there are the following two modes for etching removal when a part of a floating gate is patterned. That is, in the first aspect, the step (d) includes a step of patterning a part of the floating gate of the third storage element having a common drain region with the first storage element. The removal region that is removed by etching when part of the floating gate is patterned is continuous with the removal region that is removed by etching when part of the floating gate of the first storage element is patterned.

[0008] On the other hand, in a second embodiment, in the step (d)
Includes a step of patterning a part of the floating gate of the third storage element that shares the drain region with the first storage element, and the step of patterning the part of the floating gate of the third storage element is performed. The removed region to be etched away is separated from the removed region to be etched away when a part of the floating gate of the first storage element is patterned.

In the first aspect, since the removal area is continuous, the mask alignment at the time of etching removal becomes easier as compared with the case where the removal area is separated.

In the second aspect, the separation of the removed region means that the first conductive film is etched away only in a region necessary for patterning the floating gate. Since the removal regions are separated, the area of the concave portion of the element isolation region can be reduced as compared with the case where the removal regions are continuous. That is, in order to reduce the area of the concave portion, it is necessary to make the removal region to be etched away as small as possible. In the second aspect, since the removal area is separated, the removal area can be made smaller than in the first aspect in which the removal area is continuous. This will be described in detail in {Explanation of Effects} of the second embodiment.

(2) A non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory device that stores information by accumulating electric charges, and includes a semiconductor substrate having a main surface and an active layer formed on the main surface. Regions and element isolation regions;
And a first and a second storage element formed on the active region and separated from each other by an element isolation region.

Each of the first and second storage elements includes a source region formed in the active region, and a floating gate formed over the active region and over the element isolation region. And the floating gate of the second storage element are opposed on the element isolation region.

[0013] A nonvolatile semiconductor memory device according to the present invention comprises:
A first source line including an impurity region formed on the main surface and electrically connected to the source region of the first storage element and the source region of the second storage element;
And a word line formed on the floating gate of the storage element and extending in the same direction as the direction in which the floating gate extends.

The first element is an element isolation region and the first
A first concave portion is formed outside a region between the floating gate of the storage element and the floating gate of the second storage element. The first recess is not formed from the element isolation region to the first source line.

[0015] The nonvolatile semiconductor memory device according to the present invention comprises:
1 is a nonvolatile semiconductor memory device manufactured by a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. By the above step (g), the first concave portion is inevitably formed. According to the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the first concave portion is formed only in the element isolation region and not in the source line. Therefore, according to the nonvolatile semiconductor memory device of the present invention, it is possible to prevent the formation of the concave portion in the source line, the increase in the electric resistance of the source line, and the delay in the operation speed of the storage element.

The nonvolatile semiconductor memory device according to the present invention has the following aspects. That is, in this aspect, a third storage element sharing a drain region with the first storage element is provided;
A fourth storage element having a common drain region with the second storage element. The third storage element and the fourth storage element are separated from each other by an element isolation region. Further, this aspect includes a second source line including an impurity region formed on the main surface and electrically connected to the source region of the third storage element and the source region of the fourth storage element. A second recess is formed outside the region between the floating gate of the third storage element and the floating gate of the fourth storage element, which is an element isolation region. The second recess is not formed from the element isolation region to the second source line.

In the nonvolatile semiconductor memory device according to the present invention, there is a mode in which the second concave portion is continuous with the first concave portion.

In the nonvolatile semiconductor memory device according to the present invention, there is a mode in which the second recess is separated from the first recess. Since the removal regions are separated, the area of the concave portion of the element isolation region is smaller than when the removal regions are continuous. This will be described in detail in {Explanation of Effects} of the second embodiment.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Description of Structure} FIG. 1A is a plan view of a first embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG.
Is an equivalent circuit diagram thereof. A planar structure and an equivalent circuit according to the first embodiment will be described with reference to FIGS. On a main surface 12 of a silicon substrate 10, which is an example of a semiconductor substrate, element isolation regions 14, 16, and 18 are formed at predetermined intervals. Element isolation regions 14, 16,
An active region 20 is formed on main surface 12 so as to surround 18.

In the active region 20, storage elements 42 and 44 are formed between the element isolation region 14 and the element isolation region 16. The storage element 42 and the storage element 44 share the drain region 46. Storage elements 42, 44
Have source regions 48 and 50, respectively.

In the active region 20, storage elements 52 and 54 are formed between the element isolation region 16 and the element isolation region 18. The storage element 52 and the storage element 54 share the drain region 56. Storage elements 52, 54
Have source regions 58 and 60, respectively.

The source region 48 and the source region 58 are electrically connected to a source line (SL) 62. Also,
The source region 50 and the source region 60 are connected to the source line (S
L) 64. Source line (SL)
62 and 64 are impurity regions formed on the main surface 12.

On the main surface 12, word lines (WL) 22, 24 extending in the horizontal direction are formed. The word lines (WL) 22, 24 are connected to the element isolation regions 14, 16, 18,
Is crossing. A portion of the word line (WL) 22 located on the active region 20 is a control gate of the storage elements 42 and 52. The portion of the word line (WL) 24 located on the active region 20 is the storage element 4
4 and 54 are control gates. Bit line (B
L) is electrically connected to the drain region 46 at the contact portion 74 and to the drain region 56 at the contact portion 76.

FIG. 1B is a cross-sectional view taken along the line AA of FIG. 1A. The sectional structure of the first embodiment will be described with reference to FIG. On the main surface 12 of the silicon substrate 10, storage elements 42 and 52 are formed at intervals from each other. The storage elements 42 and 52 have a structure in which tunnel insulating films 38 and 40, floating gates 34 and 36, dielectric films 30 and 32, and control gates 26 and 28 are stacked.

The storage element 42 includes a drain region 46 and a source region 48, and the storage element 52 includes
6 and a source region 58. The source region 48 and the source region 58 are electrically connected by a source line 62.

An interlayer insulating film 68 is formed on main surface 12 so as to cover storage elements 42 and 52. Contact holes 70 and 72 reaching the drain regions 46 and 56 are formed in the interlayer insulating film 68. Interlayer insulating film 68
Above, bit lines 80 and 82 are formed. The bit lines 80 and 82 are electrically connected to the drain regions 46 and 56 via the conductive films filled in the contact holes 70 and 72.

{Description of Manufacturing Method} The manufacturing method of the first embodiment will be described with reference to FIGS. 1 and 3 to 7. FIGS. 3A to 7A correspond to FIG. 1A, and FIG.
(B) to FIG. 7 (b) correspond to FIG. 1 (b).

As shown in FIG. 3, element isolation regions 14, 16, 18 are formed on the main surface 12 of the silicon substrate 10. As the element isolation regions 14, 16, and 18, for example,
There are a LOCOS oxide film, a semi-recessed LOCOS oxide film, and a shallow trench (depth 0.4 to 0.8 μm). next,
For example, by thermal oxidation, the main surface 12 has a thickness of 7 to 10 n.
An m-th silicon oxide film 84 is formed. Silicon oxide film 8
4 becomes a tunnel insulating film.

As shown in FIG. 4, the main surface 12 of the silicon substrate 10 has a thickness of 100 to 100
A 200 nm polysilicon film 86 is formed. The polysilicon film 86 becomes a floating gate.

As shown in FIG. 5, for example, the element isolation region 14 is formed by photolithography so that the polysilicon film 86 remains on the entire surface of the source line forming regions 88 and 90 where the source lines are formed. The polysilicon film 86 on 16 and 18 is selectively removed by etching, and a part of the floating gate is patterned. The regions to be etched away on the element isolation regions 14, 16, 18 are:
The removal regions are 92, 94, and 96, respectively. The shapes of the removal regions 92, 94, and 96 have the following characteristics.

That is, the storage elements 42 and 44 shown in FIG.
Have a common drain region. Storage elements 42, 4
The region to be etched away when a part of the floating gate 4 is patterned is a removed region 92,
94. As can be seen from FIG.
The region to be etched away when a part of the floating gate 2 is patterned extends to the region to be etched away when a part of the floating gate of the storage element 44 is patterned, and both are continuous. are doing. These are removal areas 92 and 94.

The storage elements 52 and 54 shown in FIG.
The drain region is common. Regions to be etched and removed when a part of the floating gates of the storage elements 52 and 54 are patterned are removed regions 94 and 96.
It is. As can be seen from FIG. 5A, a region to be etched away when a part of the floating gate of the storage element 52 is patterned is removed by etching when a part of the floating gate of the storage element 54 is patterned. And the two are continuous. These are removal areas 94 and 96.

As shown in FIG. 6, an insulating film 98 is formed on the polysilicon film 86. The insulating film 98 becomes a dielectric film. An example of the insulating film 98 is an ONO film. O
The silicon oxide film constituting the NO film can be formed by a CVD method or thermal oxidation. The silicon nitride film constituting the ONO film can be formed by a CVD method. A polysilicon film 100 having a thickness of 200 to 400 nm is formed on the insulating film 98 by using, for example, a CVD method. The polysilicon film 100 becomes a word line (control gate). Incidentally, the polysilicon film having a thickness of 80 to 200 nm, and a silicide consisting of the WSi ₂ thick 80 to 200 nm formed _{on, MoSi 2, CoSi 2, TiSi} 2 , etc., a laminated structure of a word line ( Control gate).

The laminate comprising the polysilicon film 86, the insulating film 98, and the polysilicon film 100 is subjected to predetermined patterning, and as shown in FIG.
4, 36, dielectric films 30, 32, control gate 2
6, 28 (word lines 22, 24) are formed. The silicon oxide film 84 below the floating gates 34, 36 becomes the tunnel insulating films 38, 40. Source line forming region 8
Since the polysilicon films 86 and 100 are formed on the entire surfaces of the source line formation regions 8 and 90, respectively.
8, 90 are excessively etched, and the source line forming region 8 is formed.
No recesses are formed in 8, 90.

However, although the polysilicon film 100 exists in the removal regions 92, 94, and 96, but the polysilicon film 86 does not exist, the word lines 2 are formed in the removal regions 92, 94, and 96.
A concave portion 116 is formed in a portion not overlapping with 2 and 24. This will be further described in cross section. FIG. 8 is a sectional view taken along the line BB of FIG. 7A, and FIG.
It is sectional drawing of CC cross section of (a). A concave portion 116 is formed in the removal area 94.

As shown in FIG. 1, element isolation regions 14, 1
6, 18 and the word lines 22 and 24 are used as a mask, ions are implanted into the main surface 12 to form drain regions 46 and 56, source regions 48, 50, 58 and 60, and source lines 62 and 64.

An interlayer insulating film 68 is formed on the entire main surface 12 by using, for example, a CVD method. As the interlayer insulating film 68, for example, a silicon oxide film, a PSG film, an SOG film,
There is a PSG film. In this case, these may be used alone or in combination.

Then, contact holes 70 and 72 reaching the drain regions 46 and 56 are formed in the interlayer insulating film 68 by using, for example, photolithography. A conductive film is embedded in the contact holes 70 and 72. Interlayer insulating film 6
An aluminum film is formed on 8 by, for example, sputtering. A predetermined patterning is applied to the aluminum film. Thus, bit lines 80 and 82 electrically connected to the drain regions 46 and 56 via the conductive films in the contact holes 70 and 72 are formed.

{Description of Effect} The effect of the first embodiment will be described.

(Effect 1) As shown in FIG. 5, the polysilicon film 86 is selectively etched away so that the polysilicon film 86 remains on the entire surface of the source line forming region 88, and patterning of a part of the floating gate is performed. are doing.
Therefore, as shown in FIG. 6, the polysilicon films 86 and 100 are stacked on the source line forming region 88. That is, since the polysilicon films 86 and 100 remain on the entire surface of the source line forming region 88, the thickness of the film to be etched on the source line forming region 88 and the thickness of the film to be etched on the region where the storage element is formed are reduced. Becomes the same. Therefore, as shown in FIG.
4 and 36 and control gates 26 and 2
When patterning 8 is performed, the source line forming region 88 is not excessively etched, and a concave portion is not formed. Therefore, it is possible to prevent the electric resistance of the source line from being increased due to the concave portion and causing a delay in the operation speed of the memory element.

(Effect 2) As shown in FIG.
2 (see FIG. 1) is a region that is removed by etching when a part of the floating gate is patterned is a region that is removed by etching when a part of the floating gate of the storage element 44 (see FIG. 1) is patterned. And they are continuous (these are the removal areas 92 and 94). For this reason, compared to the second embodiment in which the region to be etched away is separated.
Mask alignment at the time of etching removal becomes easy.

The above (Effect 1) and (Effect 2) describe the source line forming region 88 and the storage elements 42 and 44. However, the same can be said for a region where another source line is formed and a storage element.

[Second Embodiment] In the second embodiment, the polysilicon film is removed by etching only in a region necessary for patterning the floating gate. For this reason, in a relationship between a certain storage element and another storage element having a common drain region with this storage element, a removed region to be etched and removed when a part of the floating gate of the other storage element is patterned. A part of a floating gate of a certain storage element is separated from a removal region which is removed by etching when patterning is performed. This point is different from the first embodiment. This will be described below. In the description of the second embodiment, portions having the same configuration as the first embodiment are denoted by the same reference numerals.

{Description of Manufacturing Method} The steps shown in FIGS. 3 and 4 described in the first embodiment are performed. The conditions are the same as in the first embodiment.

Then, as shown in FIG. 10A, the polysilicon film 86 is selectively etched away to pattern a part of the floating gate. In addition,
FIG. 10B is a sectional view taken along line BB of FIG. FIG. 10C is a cross-sectional view taken along line CC of FIG. The step shown in FIG.
This corresponds to the step shown in FIG. However, the patterning shape is different. That is, the element isolation region 14 includes the removal regions 102 and 104 removed by the etching. Element isolation region 1
6 also shows the removal area 10 removed by this etching.
6, 108. The element isolation region 18 also has removal regions 110 and 112 removed by this etching.
The removal region 102 and the removal region 104 are separated, the removal region 106 and the removal region 108 are separated, and the removal region 110 and the removal region 112 are separated. The meaning of these separations will be described.

In the second embodiment, only the region necessary for patterning the floating gate is removed by etching. Therefore, in a relationship between a certain storage element and another storage element that shares the drain region with the storage element, a removed region that is removed by etching when a part of the floating gate of the other storage element is patterned is A part of a floating gate of a certain storage element is separated from a removal region which is removed by etching when patterning is performed.

The other forming conditions are the same as those in the step shown in FIG.

Next, the step shown in FIG. 11 is performed. The step shown in FIG. 11 corresponds to the step shown in FIG. 6 described in the first embodiment. The formation conditions are the same as those in the step shown in FIG.

Next, the step shown in FIG. 12 is performed. The step shown in FIG. 12 corresponds to the step shown in FIG. 7 described in the first embodiment. In this step, patterning for forming the word lines 22 and 24 is performed. Removal areas 102, 10
In each of 4, 106, 108, 110 and 112, a concave portion 116 is formed in a portion not overlapping with the word lines 22 and 24. This is because, as shown in FIG. 11B, the polysilicon film 100 is present in the removal region (for example, the removal region 106), but the polysilicon film 8
There is no 6. In other regions, the polysilicon films 86, 1
00 is formed. Therefore, the word lines 22, 24
In the etching removal at the time of forming the (control gate, floating gate), there is no polysilicon film 86 but only the polysilicon film 100 in the removal region, so that excessive etching is performed and a concave portion is formed.

The other forming conditions are the same as those in the step shown in FIG.

Steps subsequent to the step shown in FIG. 12 are the same as those in the first embodiment, and a description thereof will be omitted.

{Description of Effect} The effect of the second embodiment will be described. The second embodiment has the same effect as (Effect 1) of the first embodiment.

In the second embodiment, as shown in FIG. 11, the removal area 102, the removal area 104, and the removal area 1 are used.
06 and the removal area 108, and the removal area 110 and the removal area 11
And 2 are separated. Therefore, as shown in FIG.
As compared with the first embodiment, a concave portion (for example, concave portion 116)
Can be reduced in area. The concave portion causes a step in a layer located above the concave portion. The steps cause various inconveniences in the manufacture of the nonvolatile semiconductor memory device (for example, disconnection of the wiring layer). Therefore, it is desirable that the formation area of the concave portion be as small as possible. Therefore,
The second embodiment is superior in this point to the first embodiment.

[Others] FIG. 13 shows a circuit board 1000 on which the nonvolatile semiconductor memory device 1100 manufactured by the method according to the above-described first or second embodiment is mounted. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board 1000.
On the circuit board 1000, a bonding portion made of, for example, copper is formed so as to form a desired circuit. And
By electrically connecting the bonding portion and the external electrodes of the nonvolatile semiconductor memory device 1100, their electrical continuity is achieved.

FIG. 14 shows a notebook personal computer 1200 as an electronic apparatus having the circuit board 1000.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA of FIG. .

FIG. 2 is an equivalent circuit diagram of the first embodiment.

FIG. 3 is a first process chart for describing a manufacturing process according to the first embodiment.

FIG. 4 is a second process chart for describing the manufacturing process of the first embodiment.

FIG. 5 is a third process chart for describing the manufacturing process of the first embodiment.

FIG. 6 is a fourth process chart for describing the manufacturing process of the first embodiment.

FIG. 7 is a fifth process chart for describing the manufacturing process of the first embodiment.

FIG. 8 is a cross-sectional view taken along the line BB of FIG.

FIG. 9 is a cross-sectional view taken along the line CC of FIG. 7 (a).

FIG. 10 shows a second example of the nonvolatile semiconductor memory device according to the present invention.
FIG. 10 is a first process chart for describing the manufacturing process of the embodiment.

FIG. 11 is a second process chart for describing the manufacturing process of the second embodiment.

FIG. 12 is a third process chart for describing the manufacturing process of the second embodiment.

FIG. 13 is a perspective view of a circuit board to which the nonvolatile semiconductor memory device according to the first or second embodiment is attached.

14 is a diagram illustrating an electronic apparatus to which the circuit board illustrated in FIG. 13 is attached.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Main surface 14, 16, 18 Element isolation region 20 Active region 22, 24 Word line 26, 28 Control gate 34, 36 Floating gate 42, 44 Storage device 46 Drain region 48, 50 Source region 52, 54 Storage device 56 Drain region 58, 60 Source region 62, 64 Source line 80, 82 Bit line 88, 90 Source line forming region 92, 94, 96, 102, 104, 106, 108,
110, 112 Removal area 116 Recess

Claims (9)

[Claims] A semiconductor substrate having a main surface; an active region and an element isolation region formed on the main surface; and a semiconductor substrate formed on the active region and separated from each other by the element isolation region. First and second storage elements having a formed source region; and an impurity region formed on the main surface, the source region of the first storage element and the source region of the second storage element. And (b) forming the active region and the element isolation region on the main surface; and (b) forming the active region and the element isolation region on the main surface. Forming a tunnel insulating film of the first and second storage elements on the active region; and (c) forming the first and second tunnels on the main surface so as to cover the tunnel insulating film. 2 storage elements Forming a first conductive film serving as a floating gate, (d) so that the the entire region where the source line is formed first conductor film is left, the first on the isolation region
(E) selectively etching away the conductive film of (a) and patterning a part of the floating gate; and (e) forming the first and second conductive films on the first conductive film.
Forming a dielectric film of the storage element, and (f) forming, on the dielectric film, a second conductor film serving as a control gate of the first and second storage elements. (G) selectively etching away the first and second conductive films to pattern the remaining portion of the floating gate and the control gate; and (h) forming a pattern on the main surface. Forming the source region and the source line. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. The method according to claim 1, wherein the step (d) includes a step of patterning a part of a floating gate of a third storage element having a common drain region with the first storage element. The removal region to be etched away when a part of the floating gate of the third storage element is patterned is removed by etching when the part of the floating gate of the first storage element is patterned. A method for manufacturing a nonvolatile semiconductor memory device which is continuous with a region. 3. The method according to claim 1, wherein the step (d) includes a step of patterning a part of a floating gate of a third storage element that shares a drain region with the first storage element. The removal region to be etched away when a part of the floating gate of the third storage element is patterned is removed by etching when the part of the floating gate of the first storage element is patterned. A method for manufacturing a nonvolatile semiconductor memory device separated from a region. 4. A nonvolatile semiconductor memory device for storing information by accumulating electric charges, comprising: a semiconductor substrate having a main surface; an active region and an element isolation region formed on the main surface; And a first storage element and a second storage element separated from each other by the element isolation region. The first and second storage elements include: a source region formed in the active region; A floating gate formed from over the active region to over the element isolation region, wherein the floating gate of the first storage element and the floating gate of the second storage element are located on the element isolation region. The nonvolatile semiconductor memory device further includes an impurity region formed on the main surface, and the source region of the first storage element. And a first source line electrically connected to the source region of the second storage element, and formed on the floating gate of the first and second storage elements and extending the floating gate. A word line extending in the same direction as the first direction, wherein the element isolation region is a region between the floating gate of the first storage element and the floating gate of the second storage element. A non-volatile semiconductor memory device, wherein a first concave portion is formed outside the semiconductor device, and the first concave portion is not formed from the element isolation region to the first source line. 5. The storage element according to claim 4, wherein a third storage element sharing a drain region with the first storage element, a fourth storage element sharing a drain region with the second storage element, The third storage element and the fourth storage element are separated from each other by the element isolation region, further include an impurity region formed on the main surface, and a source of the third storage element A second source line electrically connected to a region and a source region of the fourth storage element, wherein the second source line is an element isolation region, and the floating gate of the third storage element is A second concave portion is formed outside a region between the storage element and the floating gate, and the second concave portion is not formed from the element isolation region to the second source line. Sex semi-conduct Storage device. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said second concave portion is continuous with said first concave portion. 7. The nonvolatile semiconductor memory device according to claim 5, wherein said second recess is separated from said first recess. 8. The nonvolatile semiconductor memory device according to claim 4, 5, 6, or 7, wherein the nonvolatile semiconductor memory device according to claim 4, 5, 6, or 7 is mounted on a circuit board. 9. The nonvolatile semiconductor memory device according to claim 8, wherein said circuit board is attached to an electronic device.