JP2000181403A - Error diffusion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avert the occurrence of a spurious contour by controlling the error component of the least significant m-n bit so as not to be error diffused to a present video signal of (m) bit when judgment is made that the spurious contour occurs. SOLUTION: This device has a spurious contour occurrence judgment section which judges whether the spurious contour occurs or not when it's subjected to be error diffused and and error component control section which controls the error component of the least significant m-n bit so as not to be error diffused to the present video signal of the (m) bit when judgment is made that the spurious contour occurs. The device is so constituted that judgment is made whether the occurrence of the spurious contour is significant or not in a level comparison section 7 and if the occurrence is signification, the data of the error component is not added to the present video signal in the error component control section 4. Namely, the error component control section 4 turns on and off according to the control signal outputted from the level comparison section 7 and controls the output to an addition section 1 of the data of the error component of the m-n bit outputted from an (n) dot delay section 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PDP, for example.
The present invention relates to an error diffusion device for diffusing an error component of a video signal in order to display a pseudo halftone image in a digital display device having a linear gradation characteristic such as a (Plasma Display Panel).

[0002]

2. Description of the Related Art A subfield method generally used as a gradation display method for a plasma display will be described. 3A and 3B are diagrams for explaining a subfield method which is a gray scale display method of a plasma display. FIG. 3A is a schematic diagram of a display panel of a plasma display, and FIG. 6 is a timing chart showing a lighting time in one field of each pixel of the display panel.

In FIG. 3A, a scanning / discharge sustaining electrode (not shown) is provided on a display panel 10 for each of horizontal lines (scanning directions) Y1 to YN, and for each of vertical lines. Are provided with address electrodes (not shown).

[0004] In FIG. 3 (b), one TV field is composed of eight subfields SF1 to SF8. Each of the subfields SF1 to SF8 has 1
It comprises an address period in which a video signal is written to the address electrodes for the screen, and a discharge sustain period in which light is emitted by a sustain pulse from the scan / discharge electrodes in accordance with the instruction of the video signal written in the address electrodes. The relative ratios of the sustaining periods of the subfields SF1 to SF8 are 1: 2: 4: 8: 16: 32: 64: 1, respectively.
28.

First, a video signal is applied to the address electrodes running in the vertical direction of the display panel 10 at time t0 when the first subfield SF1 starts. When the writing of the video signal to the address electrodes of the entire display panel 10 is completed in the address period of the first subfield SF1 (time t0 to t1), the process proceeds to the discharge sustaining period of the first subfield (time t1 to t2). Only the pixels for which the lighting is instructed by the video signal emit the sustaining pulse during this sustaining period, and the display panel 10 is turned on.

Next, at time t2, the second subfield SF
Then, the same operation as in the first subfield SF1 is repeated. The same applies to the third to eighth subfields SF3 to SF8.

In the above case, since eight sub-fields SF1 to SF8 are provided in one TV field, the video signal is 8-bit data. That is, the video signal is
It is 8-bit data corresponding to the eight sub-fields SF1 to SF8. For example, if the first digit of the 8-bit video signal is 1, the discharge sustain period (time t1 to t2) of the first subfield SF1 is used. If the display panel 10 emits light, and if the eighth digit is 0, on the other hand, the display panel 10 emits light in the discharge sustain period (time t15 to t16) of the eighth subfield SF8.
Does not emit light.

The longer the sustain period that contributes to light emission of the display panel 10 is, the higher the brightness of the display panel 10 is. The brightness of the display panel 10 depends on the combination of the sustain periods of the eight subfields SF1 to SF8. 2
Display of 56 gradations is performed.

However, when the number of subfields increases, the address period cannot be shortened, so that the ratio of the address period to one TV field increases. As a result, the sustain period becomes short, and the brightness of the display panel 10 becomes low. Accordingly, the number of subfields is limited in order to maintain the predetermined luminance of the display panel 10, and the number of display bits of the video signal is correspondingly limited.

Next, error diffusion for diffusing an error component of a video signal will be described. As described above, since the number of display bits of the video signal is limited, if the number of bits of the input video signal is larger than the number of display bits, it is necessary to reduce the number of bits of the video signal. For example, the display bit number of one pixel of the plasma display is 8 bits (0 to 255).
In the case where the input video signal is 10 bits (1024 tones from 0 to 1023), it is necessary to reduce data of 2 bits of the 10-bit video signal.

In this case, simply reducing the data of 2 bits of the 10-bit video signal deteriorates the tone reproducibility of an image (video) displayed on a display.
Therefore, the two-bit data, which is an error component of the video signal, is diffused and reflected on an 8-bit video signal according to the signal level (luminance level) of the video signal, thereby improving the tone reproducibility of the image. To Such a process of diffusing an error component of a video signal is called error diffusion.

The error diffusion is usually performed by weighting the signal level in the horizontal direction or the horizontal and vertical directions of the image. That is, error diffusion is performed by assigning a signal level weight to the lower 2 bits of data of a 10-bit video signal and dividing the weighted 2-bit data in the horizontal direction of the upper 8 bits of data of the 10-bit video signal. Or in the horizontal and vertical directions.

[0013]

By the way, in the above-described subfield method, gradation display is performed by changing the discharge sustaining period during which the display panel 10 emits light, so that a false contour of a moving image is displayed on the display panel 10. (Hereinafter, simply referred to as false contour) may occur.

FIG. 4 is a diagram for explaining the cause of such a false contour. In the case of FIG. 4A, in both the current field and the next field, the 8-bit video signal is 127 (that is, 01111111 in binary), and the period (discharge) from the first subfield SF1 to the seventh subfield SF7 is performed. During the eighth subfield SF8, the display panel 10 emits light during the sustain period).
0 does not emit light. Accordingly, the light emitting period and the light non-emitting period come alternately.

On the other hand, in the case of FIG. 4B, in the current field, the 8-bit video signal is 128 (ie, 10 in binary).
000000), the eighth sub-field SF8
, The display panel 10 emits light, and the display panel 10 does not emit light during the period from the first subfield SF1 to the seventh subfield SF7. In the next field, 8
The bit video signal is 127 (ie, 01111 in binary)
111), the display panel 10 emits light during the first to seventh subfields SF1 to SF7, and does not emit light during the eighth subfield SF8. Therefore, the eighth subfield SF8 of the current field
The display panel 10 emits light from to the period of the seventh subfield SF7 of the next field.

As shown in FIG. 4B, when the light emission time is uneven, a bright false contour occurs due to the afterimage effect of the human eye. Even when the time during which light is not emitted is biased, a dark false contour occurs due to the afterimage effect of the human eye. Therefore, in order to prevent such false contours from occurring, it is necessary to consider the time during which light is emitted from the plasma display to be as uniform as possible.

On the other hand, in the error diffusion processing of a video signal as described above, the error component data is weighted to a signal level and added to the current video signal.
If a carry occurs in the upper bits of the video signal, for example,
The 8-bit current video signal is 127 (that is, 011 in binary).
11111), and as a result of adding the error component data, the 8-bit video signal becomes 128 (ie, 10 in binary).
000000), there is a problem that a false contour is generated as described above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide an error diffusion device capable of avoiding the generation of false contours.

[0019]

According to a first aspect of the present invention, there is provided an error diffusion apparatus comprising: a false contour occurrence determining unit for determining whether a false contour is generated when an error is diffused; , And an error component control unit for controlling the error component of the lower mn bits so as not to be error-diffused in the current video signal of m bits.

According to a second aspect of the present invention, in the error diffusion apparatus, the false contour occurrence determining unit inputs the lower mn bit error component, the m bit current video signal, and the upper n bit video signal, By adding the lower mn bit error component and the m bit current video signal, the influence of the lower mn bit error component on the m bit current video signal is determined.
When the n-bit error component affects the m-bit current video signal, the value of the upper n bits of the m-bit current video signal matches the value of the upper n bits of the video signal, and the value is the upper bit. It is configured to determine whether or not a false contour occurs when error diffusion is performed by determining whether or not the value causes a carry.

According to a third aspect of the present invention, in the error diffusion apparatus, the error component control unit controls the error diffusion of the lower mn bit error component by ON / OFF control.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a configuration of an error diffusion circuit according to an embodiment of the present invention. In FIG.
The adder 1 adds the input m-bit video signal and the lower-order mn-bit error component data output from the error component controller 4 and outputs the result. The error component detector 2 detects lower mn-bit error component data from the error-diffused m-bit video signal output from the adder 1, and converts the lower mn bit error component data into a signal. The output is performed by weighting the level (luminance level).

The n-dot delay unit 3 delays the data of the lower-order mn-bit error component output from the error component detector 2 by n dots in the horizontal direction of the image. This n
The mn-bit error component data delayed by the dot delay unit 3 is output to the error component control unit 4 and the level comparison unit 7. The error component control unit 4 includes a level comparison unit 7
The control of the output of the mn-bit error component data output from the n-dot delay unit 3 to the adder unit 1 is performed in accordance with the control signal output from.

The high-order n-bit output unit 5 extracts high-order n-bit data from the m-bit video signal output from the addition unit 1 and outputs it as a video signal output to a display device (not shown). . The field memory 6 delays the upper n-bit video signal output from the upper n-bit output unit 5 by one field in the image field direction (time direction).

The level comparing section 7 outputs the mn-bit error component data output from the n-dot delay section 3 and the input m-bit current video signal (m-bit video signal input to the adding section 1). , And an n-bit video signal output from the field memory 6, compare the signal levels of the three data, and output a control signal to the error component control unit 4 based on the comparison result. .

Next, the operation will be described. When an m-bit video signal is input, the m-bit video signal is
It is sent to the addition unit 1. The m-bit video signal sent to the adder 1 is subjected to error diffusion by adding the data of the lower mn bit error components output from the error component controller 4 in the adder 1 and performing error diffusion, and outputting the upper n bits. It is output to the section 5 and the error component detection section 2.

The upper n-bit output section 5 extracts the upper n-bit data of the m-bit error-diffused video signal and outputs it to a display device (not shown) and the field memory 6. On the other hand, the error component detection unit 2 detects lower mn bit data of the error-diffused m-bit video signal in order to error-diffuse the next m-bit video signal. Is weighted to a signal level, and output to the n-dot delay unit 3 as error component data.

The lower mn-bit data sent to the n-dot delay unit 3 is delayed by n dots in the horizontal direction of the image by the n-dot delay unit 3 and sent to the error component control unit 4 and the level comparison unit 7. Is output. In this embodiment, the n-dot delay unit 3 is configured to delay n dots in the horizontal direction of the image. However, the present invention is not limited to this. It is also possible to configure to delay by n fields in the direction.

The upper n-bit video signal output to the field memory 6 is delayed by one field in the field direction of the image by the field memory 6, and
The signal is output to the level comparing section 7.

The level comparing section 7 is composed of mn-bit error component data output from the n-dot delay section 3, the input m-bit current video signal, and the n-bit video signal output from the field memory 6. Are input, and the signal levels of the three data are compared. Then, the level controller 7 controls the output of the error component data of the error component controller 4 by outputting a control signal based on the comparison result to the error component controller 4.

FIG. 2 is a flowchart for explaining the processing operation of the level comparing section 7. The level comparison unit 7
When three data of the mn-bit error component data output from the n-dot delay unit 3, the input m-bit current video signal, and the n-bit video signal output from the field memory 6 are input (step ST1 to step ST3) First, the value (signal level) of the data of the mn-bit error component and the value (signal level) of the m-bit current video signal are added (step ST1).
4) Compare the value (signal level) of the upper n bits of the current video signal of m bits with the value (signal level) of the video signal of n bits (step ST5).

Next, it is determined whether or not the addition result of step ST4 appears in the data of the upper n bits of the current video signal of m bits (step ST6). Thus, mn
The effect of the data of the bit error component on the data of the upper n bits of the m-bit current video signal is determined by the fact that the data of the mn bit error component is added to the m-bit current video signal as described above. The addition is performed by the adder 1, and an n-bit video signal is output from the upper n-bit output unit 5. This is to determine the effect on the n-bit output video signal.

As a result of the determination, if the lower mn bit error component data does not appear in the upper n bit data of the m bit video signal, the adder 1 converts the lower mn bit error component data. Even if it is added to the m-bit current video signal,
Since there is no effect on the n-bit output video signal, a control signal for turning on the error component control unit 4 is output (step ST).
8).

On the other hand, as a result of the determination, when the data of the lower mn bit error component appears in the upper n bit data of the m bit video signal, the adder 1 converts the lower mn bit error component data. When added to the current video signal of m bits,
Since this affects the n-bit output video signal, the value of the upper n-bit data of the m-bit current video signal and the value of the n-bit video signal are next determined in order to determine the occurrence of false contour due to the influence. Are matched, and the value is a value that causes a carry in the upper two bits of the output video signal (for example, when the output video signal is 8 bits (n = 8)). 127 and 63) (step ST7).

That is, if the value of the upper n-bit data of the m-bit current video signal is equal to the value of the n-bit video signal, and the value is a value that causes a carry of the upper bit, an error occurs. As a result of adding the component data to the current video signal, a carry is generated from the output video signal 127 or 63 to 128 or 64, the light emission time of the plasma display becomes uneven, and a false contour occurs. .

As a result of the determination, if the value of the upper n bits of the m-bit current video signal does not match the value of the n-bit video signal, or if the values match, the value is shifted to the upper bit. If the value does not cause the false contour, the false contour does not occur (it is unlikely to occur) even if the adder 1 adds the data of the lower mn bit error component to the m-bit current video signal. Then, a control signal for turning on the error component control section 4 is output (step ST8).

On the other hand, as a result of the determination, the value of the upper n-bit data of the m-bit current video signal matches the value of the n-bit video signal, and the value is a value that causes a carry of the upper bit (for example, , 127 and 63), when the error component data is added to the m-bit current video signal by the adder 1, the carry is increased to the upper bits (for example, the upper two bits) of the m-bit current video signal. Occur (ie, 128 and 64
), Since a false contour is remarkable as described above, a control signal for turning off the error component control unit 4 is output (step ST9).

The error component control unit 4 turns ON / OFF according to the control signal output from the level comparison unit 7 as described above.
The output of the mn-bit error component data output from the n-dot delay unit 3 to the addition unit 1 is controlled. That is,
When turned on by the control signal, the error component control unit 4
-Even if the data of the n-bit error component is added to the m-bit current video signal, it does not affect the occurrence of the false contour, so that the data of the mn-bit error component is output to the adder 1. On the other hand, when turned off by the control signal, m
When the data of the error component of -n bits is added to the current video signal of m bits, the occurrence of false contour is remarkable.
Do not output -n bit error component data to the adder 1.

As described above, according to the first embodiment, the level comparison section 7 determines whether or not the occurrence of false contours is remarkable. Since the component data is not added to the current video signal, the emission time of the plasma display can be prevented from being uneven, and as a result, the occurrence of false contour can be avoided. it can.

[0040]

As described above, according to the first aspect of the present invention, a false contour occurrence judging unit for judging whether or not a false contour occurs when error diffusion occurs, Since an error component control unit is provided to control the error component of mn bits not to be error-diffused to the current video signal of m bits, it is possible to prevent the emission time of the plasma display from becoming uneven. As a result, there is an effect that generation of a false contour can be avoided.

According to the second aspect of the present invention, the false contour occurrence judging unit inputs the lower mn bit error component, the m bit current video signal, and the upper n bit video signal, and The n-bit error component and the m-bit current video signal are added to determine the influence of the m-bit current video signal due to the lower-order mn-bit error component. When the current video signal is affected, whether the value of the upper n bits of the m-bit current video signal matches the value of the upper n bits of the video signal, and whether the value is a value that causes a carry of the higher bit By determining whether or not a false contour is generated by error diffusion by determining whether or not the error is diffused, it is possible to reliably determine whether or not a false contour is generated.

According to the third aspect of the present invention, the error component control unit is configured to control the error diffusion of the lower mn-bit error component by ON / OFF control. This has the effect of preventing occurrence.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an error diffusion circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation of a level comparison unit.

FIG. 3 is a diagram for explaining a subfield method which is a gradation display method of a plasma display.

FIG. 4 is a diagram for explaining a cause of the occurrence of a false contour.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 adder 2 error component detector 3 n dot delay unit 4 error component controller 5 upper n-bit output unit 6 field memory 7 level comparison unit (false contour occurrence determination unit)

Claims (3)

[Claims] An error component of lower m-n bits of an m-bit previous video signal is added to an m-bit current video signal to perform error diffusion, and an upper n-bit video signal of the m-bit current video signal is added. An error diffusion device that outputs a false contour occurrence determining unit that determines whether or not a false contour of a moving image is generated by error diffusion;
An error component control unit for controlling an error component of n bits not to be error-diffused in the current video signal of m bits. 2. A false contour occurrence judging section inputs a lower mn bit error component, an m bit current video signal, and a higher n bit video signal, and inputs the lower mn bit error component and the lower mn bit error component. By adding the m-bit current video signal, the lower m
Determining the influence of the n-bit error component on the m-bit current video signal, and if the lower-order mn-bit error component affects the m-bit current video signal, The value of the upper n bits of the video signal and the value of the upper n bits of the video signal match, and it is determined whether or not the value is a value that causes a carry of the upper bit. The error diffusion device according to claim 1, wherein it is determined whether or not a contour occurs. 3. The error diffusion device according to claim 1, wherein the error component control unit controls error diffusion of an error component of lower mn bits by ON / OFF control.