JP2000180498A - Operational amplifier circuit and method for evaluating semiconductor device - Google Patents

Operational amplifier circuit and method for evaluating semiconductor device

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Publication number
JP2000180498A
JP2000180498A JP10355947A JP35594798A JP2000180498A JP 2000180498 A JP2000180498 A JP 2000180498A JP 10355947 A JP10355947 A JP 10355947A JP 35594798 A JP35594798 A JP 35594798A JP 2000180498 A JP2000180498 A JP 2000180498A
Authority
JP
Japan
Prior art keywords
input
operational amplifier
capacitor
amplifier circuit
feedback capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10355947A
Other languages
Japanese (ja)
Other versions
JP3311309B2 (en
Inventor
Yoshihiro Hirota
良浩 廣田
Kazuhiro Yamamoto
一弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yozan Inc
Nippon Steel Corp
Original Assignee
Yozan Inc
Sumitomo Metal Industries Ltd
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Filing date
Publication date
Application filed by Yozan Inc, Sumitomo Metal Industries Ltd filed Critical Yozan Inc
Priority to JP35594798A priority Critical patent/JP3311309B2/en
Publication of JP2000180498A publication Critical patent/JP2000180498A/en
Application granted granted Critical
Publication of JP3311309B2 publication Critical patent/JP3311309B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To accurately, easily measure inner element characteristics of a semiconductor device without measuring a film thickness of a capacity insulating layer by measuring an output voltage of a closed loop operational amplifier circuit having an inverter and a feedback capacitor. SOLUTION: The operational amplifier circuit AMP has an inverter in which CMOS inverters inv1, inv2 and inv3 are connected in series, and an output of the inverter is connected to its input Vf through a feedback capacitor Cf. An input capacitor C1 is connected to the input Vf and an input voltage Vin is connected to the capacitor C1. Further, a balanced resistance element R is connected to a connector of the inverters inv2, inv3 between a power source Vdd and a ground. A ground capacitor CL is connected to the output of the inverter. With the constitution, an oscillation in a feedback system having the capacitor Cf as a feedback circuit is prevented. In order to obtain an infinitesimal leakage current of the capacity insulating layer, the voltage Vin is maintained constantly, and an output Vout is measured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の内部素
子の特性を測定するための演算増幅回路と、それを用い
た半導体装置の評価方法に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to an operational amplifier circuit for measuring characteristics of internal elements of a semiconductor device, and a method of evaluating a semiconductor device using the same.

【0002】[0002]

【従来技術】一般に半導体装置の内部素子の特性を知る
ことは容易でない。たとえば、容量絶縁膜の誘電率測定
においては、光干渉膜圧計やエリプソメータによって、
予め容量絶縁膜の厚さdを測定しておき、基準となるキ
ャパシタの容量を測定し、式(1)から誘電率εiを求
めるが、この場合は膜厚の実測が不可欠であった。
2. Description of the Related Art Generally, it is not easy to know the characteristics of internal elements of a semiconductor device. For example, in measuring the dielectric constant of a capacitive insulating film, an optical interference film pressure gauge or an ellipsometer is used.
The thickness d of the capacitive insulating film is measured in advance, the capacitance of the reference capacitor is measured, and the dielectric constant εi is obtained from Expression (1). In this case, the actual measurement of the film thickness is indispensable.

【数1】 (Equation 1)

【0003】更に、式(1)のCox測定は容量測定器
を使用し、複数個のキャパシタについて測定を行った後
に測定結果を除算して平均値を求めるが、測定精度は容
量測定器の精度によって制限されるものとなっている。
Furthermore, the Cox measurement of the formula (1) uses a capacitance measuring device, and after measuring a plurality of capacitors, divides the measurement result to obtain an average value. Is limited by

【0004】[0004]

【発明が解決しようとする課題】本発明はこのような従
来の問題点を解決すべく創案されたもので、半導体内部
の膜厚等の実測が不測であり、容易かつ高精度に内部素
子特性の測定が可能な演算増幅回路と半導体装置の評価
方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in order to solve such a conventional problem, and the actual measurement of the film thickness and the like inside the semiconductor is unpredictable. It is an object of the present invention to provide an operational amplifier circuit and a method for evaluating a semiconductor device, which are capable of measuring the temperature.

【0005】[0005]

【課題を解決するための手段】請求項1によれば、奇数
段直列のCMOSインバータよりなるインバータ回路
と、前記インバータ回路の出力と入力との間で接続され
る帰還キャパシタとからなる閉ループオペアンプ回路
と、前記閉ループオペアンプ回路の出力電圧を出力する
ための出力端子と、前記閉ループオペアンプ回路の入力
に接続された入力キャパシタと、外部から前記入力キャ
パシタに既知の第1の入力電圧を入力し得る入力端子と
を備え、前記閉ループオペアンプ回路の出力電圧に基づ
いて内部素子の特性を測定しうる演算増幅回路によって
なるものにより解決される。
According to the first aspect of the present invention, a closed loop operational amplifier circuit comprising an inverter circuit composed of odd-numbered stages of CMOS inverters and a feedback capacitor connected between an output and an input of the inverter circuit. An output terminal for outputting an output voltage of the closed-loop operational amplifier circuit, an input capacitor connected to an input of the closed-loop operational amplifier circuit, and an input capable of externally inputting a known first input voltage to the input capacitor And an operational amplifier circuit having a terminal and capable of measuring characteristics of an internal element based on an output voltage of the closed loop operational amplifier circuit.

【0006】これにより、いちいち容量絶縁層の膜厚測
定をすることなく、半導体装置の内部素子特性が高精度
に容易に測定出来るようになる。
Thus, the internal element characteristics of the semiconductor device can be easily and accurately measured without measuring the thickness of the capacitance insulating layer.

【0007】請求項2によれば、奇数段直列のCMOS
インバータよりなるインバータ回路と、前記インバータ
回路の出力と入力との間で接続される帰還キャパシタと
からなる閉ループオペアンプ回路と、前記閉ループオペ
アンプ回路の出力電圧を出力するための出力端子と、前
記閉ループオペアンプ回路の入力に接続された入力キャ
パシタと、外部から前記入力キャパシタに既知の第1の
入力電圧を入力し得る入力端子とを備え、前記入力端子
に入力される一定の第1の入力電圧に対する前記出力電
圧の変化から、前記閉ループオペアンプ回路の第2の入
力電圧の変化量を求め、前記帰還キャパシタおよび前記
入力キャパシタの容量絶縁層の電荷移動量から前記容量
絶縁層のリーク電流を求めることができる。
According to the second aspect, an odd-numbered series CMOS
A closed loop operational amplifier circuit including an inverter circuit including an inverter, a feedback capacitor connected between an output and an input of the inverter circuit, an output terminal for outputting an output voltage of the closed loop operational amplifier circuit, and the closed loop operational amplifier An input capacitor connected to an input of a circuit; and an input terminal capable of externally inputting a known first input voltage to the input capacitor, wherein the input capacitor is connected to a constant first input voltage input to the input terminal. The amount of change in the second input voltage of the closed loop operational amplifier circuit can be obtained from the change in the output voltage, and the leakage current of the capacitive insulating layer can be obtained from the amount of charge transfer of the capacitive insulating layer of the feedback capacitor and the input capacitor. .

【0008】これにより、回路規模が小さく、簡単なD
C(直流)測定器で10-15A以下の各容量絶縁層のリ
ーク電流値が高精度に測定できるようになる。
As a result, the circuit scale is small and the simple D
The leak current value of each capacitance insulating layer of 10 -15 A or less can be measured with high accuracy by a C (direct current) measuring device.

【0009】請求項3によれば、少なくとも2つの入力
キャパシタを選択的に接続するスイッチを備えた前記閉
ループオペアンプ回路を少なくとも1つ有することを特
徴とする請求項1記載の演算増幅回路が示されており、
これを半導体ウエハ面内に適宜配置することにより、半
導体装置の内部素子特性のウエハ面内分布が分かる。
According to a third aspect of the present invention, there is provided an operational amplifier circuit according to the first aspect, further comprising at least one closed loop operational amplifier circuit having a switch for selectively connecting at least two input capacitors. And
By appropriately arranging this in the semiconductor wafer surface, the distribution of the internal element characteristics of the semiconductor device in the wafer surface can be determined.

【0010】請求項4によれば、少なくとも2つの入力
キャパシタを選択的に接続するスイッチを備えた前記閉
ループオペアンプ回路を少なくとも1つ有しており、前
記スイッチを切り替えて前記帰還キャパシタおよび各々
の前記入力キャパシタの容量絶縁層のリーク電流を請求
項2記載の方法において測定した後、該リーク電流のウ
エハの面内に於ける分布を測定する事ができる。
According to a fourth aspect of the present invention, there is provided at least one closed-loop operational amplifier circuit having a switch for selectively connecting at least two input capacitors, and switching the switch to switch the feedback capacitor and each of the feedback capacitors. After measuring the leak current of the capacitive insulating layer of the input capacitor by the method of claim 2, the distribution of the leak current in the plane of the wafer can be measured.

【0011】これにより、回路規模が小さく、簡単なD
C(直流)測定器で10-15A以下の各容量絶縁層のリ
ーク電流値のウエハ面内分布が高精度に測定できるよう
になる。
As a result, the circuit scale is small and the simple D
With a C (direct current) measuring device, the distribution of the leakage current value of each capacitance insulating layer of 10 -15 A or less in the wafer surface can be measured with high accuracy.

【0012】請求項5によれば、前記入力キャパシタと
前記帰還キャパシタとが同一の誘電率を有する容量絶縁
層からなることを特徴とする請求項1または3記載の演
算増幅回路が示されている。ここで同一の誘電率とは、
0.05%以下に有ることが望ましく、特に0.01%
以下で良好な結果が得られる。
According to claim 5, the operational amplifier circuit according to claim 1 or 3, wherein the input capacitor and the feedback capacitor are formed of a capacitive insulating layer having the same dielectric constant. . Here, the same dielectric constant means
It is desirable that it is less than 0.05%, especially 0.01%
Good results are obtained below.

【0013】この演算増幅回路を用いれば、高精度な膜
厚計を用いることなく、半導体装置内部の各容量絶縁膜
の相対的な膜厚が容易に分かる。
By using this operational amplifier circuit, the relative thickness of each capacitance insulating film inside the semiconductor device can be easily determined without using a highly accurate thickness gauge.

【0014】請求項6によれば、前記入力キャパシタと
前記帰還キャパシタとが同一の誘電率を有する容量絶縁
層からなり、前記閉ループオペアンプ回路の第2の入力
電圧の変化量に対する前記出力電圧の変化量に基づい
て、前記入力キャパシタと前記帰還キャパシタとの容量
比を求め、前記容量絶縁層のウエハ面内における相対的
な膜厚を求めることができる。
According to the sixth aspect, the input capacitor and the feedback capacitor are formed of a capacitive insulating layer having the same dielectric constant, and the change of the output voltage with respect to the change of the second input voltage of the closed loop operational amplifier circuit. A capacitance ratio between the input capacitor and the feedback capacitor is determined based on the amount, and a relative film thickness of the capacitive insulating layer in a wafer surface can be determined.

【0015】これによれば、半導体ウエハの容量絶縁膜
の膜厚の相対的な面内分布が、容易に分かり、半導体装
置の評価が容易になる。
According to this, the relative in-plane distribution of the film thickness of the capacitive insulating film of the semiconductor wafer can be easily understood, and the evaluation of the semiconductor device can be easily performed.

【0016】請求項7によれば、前記入力キャパシタと
前記帰還キャパシタとのそれぞれの容量絶縁層が同一の
厚さに形成されていることを特徴とする請求項1または
3記載の演算増幅回路が示されている。ここで同一の厚
さとは、例えば同じ8インチウエハ面内でその誤差の分
布が10%以下に有る事を示すものとする。同一回路素
子内の入力キャパシタと帰還キャパシタのキャパシタの
組では、それらキャパシタが非常に近接しているので云
うまでもなく全く等しい厚さであり、キャパシタの組同
士の間で、上記条件のとき同一厚さであると云う。
According to a seventh aspect of the present invention, in the operational amplifier circuit according to the first or third aspect, the respective capacitive insulating layers of the input capacitor and the feedback capacitor are formed to have the same thickness. It is shown. Here, the same thickness means, for example, that the error distribution is 10% or less in the same 8-inch wafer surface. It is needless to say that the input capacitor and the feedback capacitor set in the same circuit element are very close to each other because they are so close to each other that they have the same thickness. It is called thickness.

【0017】この演算増幅回路を用いれば、高精度な容
量計を用いることなく、半導体装置内部の各容量絶縁膜
の相対的な静電容量が容易に分かる。
By using this operational amplifier circuit, the relative capacitance of each capacitance insulating film inside the semiconductor device can be easily determined without using a high-precision capacitance meter.

【0018】請求項8によれば、前記入力キャパシタと
前記帰還キャパシタとのそれぞれの容量絶縁層が同一の
厚さに形成されており、前記閉ループオペアンプ回路の
第2の入力電圧の変化量に対する前記出力電圧の変化量
に基づいて、前記入力キャパシタと前記帰還キャパシタ
との容量比を求め、前記容量絶縁層のウエハ面内におけ
る相対的な誘電率を求めることができる。こうすること
により、高精度な容量計を用いることなく、半導体装置
内部の各容量絶縁膜の静電容量の半導体ウエハ面内に於
ける相対的な分布が容易に測定できる。
According to the eighth aspect, the respective capacitive insulating layers of the input capacitor and the feedback capacitor are formed to have the same thickness, and the capacitance insulating layers of the input capacitor and the feedback capacitor are formed with respect to the variation of the second input voltage of the closed loop operational amplifier circuit. A capacitance ratio between the input capacitor and the feedback capacitor is determined based on a change amount of the output voltage, and a relative dielectric constant of the capacitive insulating layer in a wafer plane can be determined. By doing so, the relative distribution of the capacitance of each capacitance insulating film inside the semiconductor device within the semiconductor wafer surface can be easily measured without using a highly accurate capacitance meter.

【0019】請求項9によれば、前記入力キャパシタと
前記帰還キャパシタとのそれぞれの容量絶縁層が同一サ
イズのMOSキャパシタによって形成されていることを
特徴とする請求項1、3または7記載の演算増幅回路が
示される。ここで同一サイズとは、その誤差が規定値に
対して0.05μm以下であることを示すものとする。
According to a ninth aspect of the present invention, the respective capacitive insulating layers of the input capacitor and the feedback capacitor are formed by MOS capacitors of the same size. An amplifier circuit is shown. Here, the same size indicates that the error is 0.05 μm or less with respect to a specified value.

【0020】また、請求項10によれば、奇数段直列の
CMOSインバータよりなるインバータ回路と、前記イ
ンバータ回路の出力と入力との間で接続される帰還キャ
パシタとからなる閉ループオペアンプ回路と、前記閉ル
ープオペアンプ回路の出力電圧を出力するための出力端
子と、前記閉ループオペアンプ回路の入力に接続された
入力キャパシタと、外部から前記入力キャパシタに既知
の第1の入力電圧を入力し得る入力端子とを備え、前記
入力キャパシタと前記帰還キャパシタとのそれぞれの容
量絶縁層が同一サイズのMOSキャパシタによって形成
されており、第1の入力電圧に対する前記出力電圧に基
づいて、前記入力キャパシタと前記帰還キャパシタとの
容量比から、前記容量絶縁層のウエハ面内における相対
的な界面準位を求めることが出来る。
According to a tenth aspect of the present invention, there is provided a closed loop operational amplifier circuit including an inverter circuit including an odd-numbered series of CMOS inverters, a feedback capacitor connected between an output and an input of the inverter circuit, and the closed loop. An output terminal for outputting an output voltage of the operational amplifier circuit, an input capacitor connected to an input of the closed loop operational amplifier circuit, and an input terminal capable of externally inputting a known first input voltage to the input capacitor The respective capacitance insulating layers of the input capacitor and the feedback capacitor are formed by MOS capacitors of the same size, and the capacitances of the input capacitor and the feedback capacitor are determined based on the output voltage with respect to a first input voltage. From the ratio, the relative interface state in the wafer surface of the capacitive insulating layer was determined. Rukoto can be.

【0021】これらの演算増幅回路と半導体装置の評価
方法によって、容量測定器の精度以上の微小容量のキャ
パシタのウエハ面内の相対的な界面準位分布が得られ
る。
By using the operational amplifier circuit and the semiconductor device evaluation method, a relative interface state distribution in a wafer surface of a capacitor having a minute capacitance equal to or higher than the accuracy of the capacitance measuring device can be obtained.

【0022】[0022]

【実施の態様】図1は、内部素子特性の測定のために半
導体装置内部に設けられる演算増幅回路AMPを示す。
演算増幅回路AMPはCMOSインバータinv1、i
nv2、inv3を直列に接続したインバータ回路を有
し、このCMOSインバータに用いられるトランジスタ
の物理的なサイズは、Lp=1.0μm、Wp=6.1
μm、Ln=0.8μm、Wn=2.2μmである。こ
のインバータ回路の出力を2pFの帰還キャパシタCf
によってその入力Vfに接続している。このインバータ
回路の入力Vfには2pFの入力キャパシタC1が接続
され、入力キャパシタC1には入力電圧Vinが接続さ
れている。さらに、CMOSインバータinv2とin
v3との接続部には、45kΩの平衡抵抗素子Rが演算
増幅回路AMPの電源Vddおよびグランドとの間にそ
れぞれ接続されており、該インバータ回路のゲインを抑
制している。また該インバータ回路の出力には接地キャ
パシタCLがグランドとの間に接続されローパスフィル
タが構成されている。以上の構成により、キャパシタC
fを帰還路とするフィードバック系における発振が防止
されている。なお、入力電圧Vinは半導体装置の外部
に形成された入力端子(入力ピン)から供給され、出力
電圧Voutは外部に形成された出力端子(出力ピン)
から出力される。
FIG. 1 shows an operational amplifier circuit AMP provided inside a semiconductor device for measuring internal element characteristics.
The operational amplifier circuit AMP is a CMOS inverter inv1, i
It has an inverter circuit in which nv2 and inv3 are connected in series, and the physical size of the transistor used in this CMOS inverter is Lp = 1.0 μm and Wp = 6.1.
μm, Ln = 0.8 μm, and Wn = 2.2 μm. The output of this inverter circuit is connected to a 2 pF feedback capacitor Cf.
Connected to the input Vf. An input capacitor C1 of 2 pF is connected to an input Vf of the inverter circuit, and an input voltage Vin is connected to the input capacitor C1. Further, CMOS inverters inv2 and inv
At the connection with v3, a 45 kΩ balanced resistance element R is connected between the power supply Vdd of the operational amplifier circuit AMP and the ground, thereby suppressing the gain of the inverter circuit. Further, a ground capacitor CL is connected between the output of the inverter circuit and the ground to form a low-pass filter. With the above configuration, the capacitor C
Oscillation in a feedback system having f as a feedback path is prevented. The input voltage Vin is supplied from an input terminal (input pin) formed outside the semiconductor device, and the output voltage Vout is output from an output terminal (output pin) formed outside.
Output from

【0023】容量絶縁層の微小リーク電流を求める測定
に際しては、入力電圧Vinを一定にし、インバータ回
路の出力電圧Voutを測定することにする。いま、帰還
キャパシタCf、入力キャパシタC1、インバータ回路
の出力電圧Vout、インバータ回路の入力電圧Vf、入
力電圧Vin間では電荷保存則が成り立ち、それらの関
係は式(2)の様に記載でき、両辺をCfで除算すると
式(3)のようになる。いま、Cf=C1=2pFなの
で、前記の式(3)は、式(4)から更に式(5)へと
書き改められる。
In the measurement for obtaining the minute leakage current of the capacitance insulating layer, the input voltage Vin is kept constant, and the output voltage Vout of the inverter circuit is measured. Now, a charge conservation law is established between the feedback capacitor Cf, the input capacitor C1, the output voltage Vout of the inverter circuit, the input voltage Vf of the inverter circuit, and the input voltage Vin, and the relationship therebetween can be described as in equation (2). Is divided by Cf to obtain Equation (3). Now, since Cf = C1 = 2 pF, Equation (3) is rewritten from Equation (4) to Equation (5).

【数2】 ここで図4に示すようにリーク電流が生じたことによ
り、1時間=3600秒でVoutが3.00Vから2.
64Vまで0.38V低下している。Vinは一定であ
るのと式(5)より、インバータ回路の入力電圧Vfの
1時間当たりのリーク電流による変化であるΔVf=
0.19Vを得る。
(Equation 2) Here, as shown in FIG. 4, Vout changes from 3.00 V to 2.0 in 1 hour = 3600 seconds due to the occurrence of a leak current.
It has dropped by 0.38V to 64V. From equation (5) that Vin is constant, ΔVf = the change due to the leak current per hour of the input voltage Vf of the inverter circuit.
Obtain 0.19V.

【0024】一方で電荷の移動は、Q=CVより、 ΔQ=(C1+Cf)×ΔVf =(2×10ー12+2×10ー12)×0.19 =7.6×10ー12 となる。従って求めるリーク電流iは、 i=7.6×10ー12÷3600(A) =2.1×10ー15(A) =2.1(fA) となる。インバータ入力電圧Vfの電圧変化量がこの例
の10分の1以下であっても、簡単な電圧計で測定が可
能であるので、これらのことからリーク電流が10
ー15(A)以下であってもこの実施例のような簡便な
装置で容易に測定が出来る。
The movement of the one in charge, from Q = CV, the ΔQ = (C1 + Cf) × ΔVf = (2 × 10 over 12 + 2 × 10 over 12) × 0.19 = 7.6 × 10 over 12. Accordingly, the leak current i to be obtained is as follows: i = 7.6 × 10−12 ÷ 3600 (A) = 2.1 × 10−15 (A) = 2.1 (fA) Even if the amount of change in the inverter input voltage Vf is less than one-tenth of this example, it is possible to measure with a simple voltmeter.
-15 (A) Even below, measurement can be easily performed with a simple device as in this embodiment.

【0025】図3に示すように、入力電圧Vinを変化
させた時のVoutーVin特性の変化を測定すること
からリーク電流を測定することも可能である。リークが
無いときの入力特性をp1、リークが生じた後のp2と
すると、両者はほぼ平行な直線として表現される。リー
ク前とリーク後とのVinとVoutとが分かれば、式
(3)とからインバータ入力電圧Vfの変化量が分か
り、その後は上記と同様にリーク電流が求められる。こ
こで入力電圧の変更は、外部入力ピンから与えられる入
力電圧を直接変化させるか、あるいは複数の入力電圧を
外部入力ピンに予め印加しておき、内部のスイッチでこ
れを切り替える。
As shown in FIG. 3, the leakage current can be measured by measuring the change in the Vout-Vin characteristic when the input voltage Vin is changed. Assuming that the input characteristic when there is no leak is p1 and the input characteristic is p2 after the leak has occurred, both are represented as substantially parallel straight lines. If Vin and Vout before and after the leak are known, the amount of change in the inverter input voltage Vf can be determined from Equation (3), and thereafter, the leak current is obtained in the same manner as described above. Here, the input voltage is changed by directly changing the input voltage supplied from the external input pin, or by applying a plurality of input voltages to the external input pin in advance and switching between them by an internal switch.

【0026】ところで式(3)によれば、入力電圧と出
力電圧の比が帰還キャパシタと入力キャパシタとの容量
比で表される。これは、帰還キャパシタと入力キャパシ
タとの間に容量測定器の精度以下の微小な容量差が有っ
た場合でも本発明の演算増幅回路AMPから得られる出
力電圧によりその差が分かることを示している。ここで
は敢えて図示しないが、ウエハ面内に多数この演算増幅
回路AMPを形成し、微小な差がある相対容量の面内分
布を求めることが確認できた。
According to the equation (3), the ratio between the input voltage and the output voltage is represented by the capacitance ratio between the feedback capacitor and the input capacitor. This indicates that even if there is a small capacitance difference between the feedback capacitor and the input capacitor, which is smaller than the accuracy of the capacitance measuring device, the difference can be determined by the output voltage obtained from the operational amplifier circuit AMP of the present invention. I have. Although not shown here, it was confirmed that a large number of the operational amplifier circuits AMP were formed on the wafer surface and the in-plane distribution of the relative capacitance having a small difference was obtained.

【0027】帰還キャパシタCfの膜厚をdfとしその
相対誘電率をεf、入力キャパシタC1の膜厚をd1と
しその相対誘電率をε1とした時、式(3)は式(6)
のように書き直せる。
When the film thickness of the feedback capacitor Cf is df, its relative permittivity is εf, and the film thickness of the input capacitor C1 is d1 and its relative permittivity is ε1, equation (3) becomes equation (6).
Can be rewritten as

【数3】 この式(6)から明らかになったように、半導体ウエハ
面内の相対的な膜厚分布が明らかで有ればウエハ面内の
相対的な誘電率分布を求めることが出来る一方で、相対
的な誘電率分布が分かれば相対的な膜厚分布を求めるこ
とが出来る。
(Equation 3) As is clear from the equation (6), if the relative film thickness distribution in the semiconductor wafer surface is clear, the relative dielectric constant distribution in the wafer surface can be obtained, while the relative dielectric constant distribution in the wafer surface can be obtained. If a proper dielectric constant distribution is known, a relative film thickness distribution can be obtained.

【0028】演算増幅回路AMPを構成する帰還キャパ
シタCfと入力キャパシタC1が、厚み誤差が10%以
下の同一膜厚の公知の材料による絶縁膜によって形成さ
れる約100μm×約500μmの多数の前記演算増幅
回路AMPからなる半導体装置を作成した。この条件下
では同一膜厚の為、式(6)は式(7)の様に書き直せ
る。
The feedback capacitor Cf and the input capacitor C1 which constitute the operational amplifier circuit AMP are formed of a large number of the above-mentioned operations of about 100 μm × about 500 μm each formed of an insulating film of a known material having the same thickness and having a thickness error of 10% or less. A semiconductor device including the amplifier circuit AMP was manufactured. Under this condition, since the film thickness is the same, Expression (6) can be rewritten as Expression (7).

【数4】 これから、個々の演算増幅回路AMPの入力電圧と出力
電圧の比が、これらの絶縁膜の相対誘電率を示し、結果
として半導体装置に多数形成された演算増幅回路AMP
により、半導体装置面内の相対的な誘電率分布を求める
ことが確認できた。
(Equation 4) From this, the ratio of the input voltage to the output voltage of each operational amplifier circuit AMP indicates the relative permittivity of these insulating films, and as a result, a large number of operational amplifier circuits AMP formed in the semiconductor device.
As a result, it was confirmed that the relative dielectric constant distribution in the semiconductor device surface was determined.

【0029】また、演算増幅回路AMPを構成する帰還
キャパシタCfと入力キャパシタC1が、0.01%以
下の誘電率誤差にある材料による同一誘電率の絶縁膜に
よって形成される約100μm×約500μmの多数の
前記演算増幅回路AMPからなる半導体装置を作成し
た。この条件下では同一誘電率の為、式(6)は式
(8)の様に書き直せる。
Further, the feedback capacitor Cf and the input capacitor C1 constituting the operational amplifier circuit AMP are about 100 μm × about 500 μm each formed by an insulating film having the same dielectric constant made of a material having a dielectric constant error of 0.01% or less. A semiconductor device including a large number of the operational amplifier circuits AMP was manufactured. Under this condition, since the dielectric constant is the same, equation (6) can be rewritten as equation (8).

【数5】 これから、個々の演算増幅回路AMPの入力電圧と出力
電圧の比が、これらの絶縁膜の相対膜厚を示し、結果と
して半導体装置に多数形成された演算増幅回路AMPに
より、半導体装置面内の相対的な絶縁膜の膜厚分布を求
めることが確認できた。更に追試した結果0.05%の
誘電率誤差までは、膜厚分布を十分に求めることが出
来、好ましい範囲であることが分かった。
(Equation 5) From this, the ratio of the input voltage to the output voltage of each operational amplifier circuit AMP indicates the relative film thickness of these insulating films. As a result, the operational amplifier circuits AMP formed in a large number on the semiconductor device cause It was confirmed that a typical film thickness distribution of the insulating film was obtained. Furthermore, as a result of additional tests, it was found that the film thickness distribution could be sufficiently obtained up to a dielectric constant error of 0.05%, which was a preferable range.

【0030】これらの演算は入力電圧Vinと出力電圧
Voutとの比の算出から求まるものである。前記して
きたように電圧計は容量計に比べて精度が高く、それに
よる電圧比の算出も高精度化が容易なため、膜厚や誘電
率から直接的にウエハ面内の分布を求める場合に比較し
て、微妙な差異を検出した相対分布が得られた。
These calculations are obtained by calculating the ratio between the input voltage Vin and the output voltage Vout. As described above, the voltmeter has higher accuracy than the capacitance meter, and the calculation of the voltage ratio can be easily performed with higher accuracy. Therefore, when the distribution in the wafer surface is directly obtained from the film thickness or the dielectric constant, By comparison, a relative distribution that detected subtle differences was obtained.

【0031】界面準位はMOS界面の物理的欠陥によっ
て電荷が捕獲される容量のことで、総捕獲電荷量Qをq
(電気素量)で割ったもので示される。この界面準位は
MOSデバイスの特性を大きく左右するものである。こ
の界面準位分布の測定に際しては、入力キャパシタC
1、帰還キャパシタCfを同一サイズのMOSキャパシ
タ(規定値に対して0.05μm以内の精度にあるも
の)で構成し、出力電圧Voutを測定する。ここで酸
化膜中の固定電荷密度が等しいとし、図2に示すよう
に、帰還キャパシタ、入力キャパシタそれぞれのCV曲
線がずれていることから界面準位の差を求めることが出
来た。
The interface level is a capacitance at which electric charges are captured by a physical defect at the MOS interface.
(Electricity). This interface state greatly affects the characteristics of the MOS device. When measuring this interface state distribution, the input capacitor C
1. The feedback capacitor Cf is constituted by a MOS capacitor of the same size (with an accuracy within 0.05 μm with respect to a specified value), and the output voltage Vout is measured. Here, assuming that the fixed charge density in the oxide film is equal, as shown in FIG. 2, since the CV curves of the feedback capacitor and the input capacitor are shifted, the difference in the interface state can be obtained.

【0032】界面準位に起因して、C1、Cfの容量値
がCa、Cbに変化したとき、出力電圧Voutは式
(9)の様に表すことが出来る。ここにα=(Ca/C
b)である。また、Ca、Cbの差は式(10)で表現
される。これらとQ=CVより、界面準位密度の差は式
(11)で与えられる。
When the capacitance values of C1 and Cf change to Ca and Cb due to the interface state, the output voltage Vout can be expressed as in equation (9). Where α = (Ca / C
b). Further, the difference between Ca and Cb is expressed by equation (10). From these and Q = CV, the difference in interface state density is given by equation (11).

【数6】 基準となるキャパシタ容量Cbを一つ求めることで、式
(10)、式(11)より2つのキャパシタの界面準位
の差が求められることが確認できた。なお、界面準位の
絶対値を求めるには既知の基準キャパシタ界面準位を別
途求めておく必要がある。
(Equation 6) It was confirmed that the difference between the interface states of the two capacitors can be obtained from Equations (10) and (11) by obtaining one reference capacitor capacity Cb. In order to obtain the absolute value of the interface state, it is necessary to separately obtain a known reference capacitor interface state.

【0033】[0033]

【発明の効果】前述の通り、奇数段直列のCMOSイン
バータよりなるインバータ回路と、前記インバータ回路
の出力と入力との間で接続される帰還キャパシタとから
なる閉ループオペアンプ回路と、前記閉ループオペアン
プ回路の出力電圧を出力するための出力端子と、前記閉
ループオペアンプ回路の入力に接続された入力キャパシ
タと、外部から前記入力キャパシタに既知の第1の入力
電圧を入力し得る入力端子とを備え、前記閉ループオペ
アンプ回路の出力電圧に基づいて内部素子の特性を測定
しうる演算増幅回路としたので、容量絶縁層の膜厚測定
をすることなく、半導体装置の内部素子特性が高精度に
容易に測定出来る。そして、前記帰還キャパシタおよび
前記入力キャパシタの容量絶縁層の電荷移動量から前記
容量絶縁層のリーク電流を求めるので、回路規模が小さ
く、簡単なDC(直流)測定器で10-15A以下の各容
量絶縁層のリーク電流値が高精度に測定できるようにな
る。
As described above, a closed loop operational amplifier circuit comprising an inverter circuit composed of odd-numbered series CMOS inverters, a feedback capacitor connected between the output and the input of the inverter circuit, and a closed loop operational amplifier circuit comprising: An output terminal for outputting an output voltage, an input capacitor connected to an input of the closed-loop operational amplifier circuit, and an input terminal capable of externally inputting a known first input voltage to the input capacitor; Since the operational amplifier circuit can measure the characteristics of the internal elements based on the output voltage of the operational amplifier circuit, the internal element characteristics of the semiconductor device can be easily measured with high accuracy without measuring the film thickness of the capacitive insulating layer. Then, the leak current of the capacitive insulating layer is obtained from the amount of charge transfer of the capacitive insulating layer of the feedback capacitor and the input capacitor. Therefore, the circuit scale is small and a DC (direct current) measuring device of 10 -15 A or less is used. The leak current value of the capacitive insulating layer can be measured with high accuracy.

【0034】また、少なくとも2つの入力キャパシタを
選択的に接続するスイッチを備えた前記閉ループオペア
ンプ回路を少なくとも1つ有することを演算増幅回路の
半導体ウエハ面内に適宜配置することにより、半導体装
置の内部素子特性のウエハ面内分布が分かり、特にリー
ク電流のウエハの面内に於ける分布を測定する事ができ
るとともに、回路規模が小さく、簡単なDC(直流)測
定器で10-15A以下の各容量絶縁層のリーク電流値の
ウエハ面内分布が高精度に測定できるようになる。
Further, at least one closed-loop operational amplifier circuit having a switch for selectively connecting at least two input capacitors is provided on the semiconductor wafer surface of the operational amplifier circuit as appropriate, so that the inside of the semiconductor device is The distribution of the device characteristics in the wafer plane can be understood. In particular, the distribution of the leakage current in the wafer plane can be measured, and the circuit scale is small, and a simple DC (direct current) measuring device of 10 -15 A or less can be obtained. The distribution of the leakage current value of each capacitance insulating layer within the wafer surface can be measured with high accuracy.

【0035】更に、入力キャパシタと帰還キャパシタと
が同一の誘電率を有する容量絶縁層からなる演算増幅回
路を用いたので、高精度な膜厚計を用いることなく、半
導体装置内部の各容量絶縁膜の相対的な膜厚が容易に分
かる。またこの時、入力キャパシタと帰還キャパシタと
の容量比を求め、前記容量絶縁層のウエハ面内における
相対的な膜厚を求めたので、半導体ウエハの容量絶縁膜
の膜厚の相対的な面内分布が、容易に分かり、半導体装
置の評価が容易になる。
Further, since the input and feedback capacitors use an operational amplifier circuit composed of capacitive insulating layers having the same dielectric constant, each capacitive insulating film inside the semiconductor device can be used without using a highly accurate film thickness gauge. Can be easily understood. Also, at this time, the capacitance ratio between the input capacitor and the feedback capacitor was determined, and the relative thickness of the capacitive insulating layer in the wafer surface was determined. The distribution is easily understood, and the evaluation of the semiconductor device is facilitated.

【0036】加えて、入力キャパシタと帰還キャパシタ
とのそれぞれの容量絶縁層が同一の厚さに形成されてい
る演算増幅回路を用いたので、高精度な容量計を用いる
ことなく、半導体装置内部の各容量絶縁膜の相対的な静
電容量が容易に分かる。またこの時、入力キャパシタと
帰還キャパシタとの容量比を求め、前記容量絶縁層のウ
エハ面内における相対的な誘電率を求めたので、高精度
な容量計を用いることなく、半導体装置内部の各キャパ
シタの静電容量の半導体ウエハ面内に於ける相対的な分
布が容易に測定できる。
In addition, since the operational amplifier circuits in which the respective capacitive insulating layers of the input capacitor and the feedback capacitor are formed to have the same thickness are used, the inside of the semiconductor device can be used without using a highly accurate capacitance meter. The relative capacitance of each capacitance insulating film can be easily understood. Also, at this time, the capacitance ratio between the input capacitor and the feedback capacitor was obtained, and the relative permittivity of the capacitance insulating layer in the wafer plane was obtained. The relative distribution of the capacitance of the capacitor in the plane of the semiconductor wafer can be easily measured.

【0037】更に加えて、入力キャパシタと帰還キャパ
シタとのそれぞれの容量絶縁層が同一サイズのMOSキ
ャパシタによって形成されている演算増幅回路とし、入
力キャパシタと帰還キャパシタとの容量比から、容量絶
縁層のウエハ面内における相対的な界面準位を求めるこ
とが出来、容量測定器の精度以上の微小容量のキャパシ
タのウエハ面内の相対的な界面準位分布が得られる等
に、示してきたように優れた効果を有する。
In addition, an operational amplifier circuit in which the respective capacitance insulating layers of the input capacitor and the feedback capacitor are formed by MOS capacitors of the same size is provided. As shown above, the relative interface state in the wafer surface can be obtained, and the relative interface state distribution in the wafer surface of a capacitor having a small capacitance exceeding the accuracy of the capacitance measuring device can be obtained. Has excellent effects.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体装置の内部に設けられる回
路を示す回路図である。
FIG. 1 is a circuit diagram showing a circuit provided inside a semiconductor device according to the present invention.

【図2】同実施例により測定される容量を示すグラフで
ある。
FIG. 2 is a graph showing a capacity measured according to the example.

【図3】図1の回路の入出力関係を示すグラフであ
る。。
FIG. 3 is a graph showing an input / output relationship of the circuit of FIG. 1; .

【図4】図1の回路の出力の経時変化を示すグラフであ
る。
FIG. 4 is a graph showing the change over time of the output of the circuit of FIG. 1;

【符号の説明】[Explanation of symbols]

C1、Cf、CL...キャパシタ inv1、inv2、inv3...CMOSインバー
タ R...抵抗 Vin...入力電圧 Vout...出力電圧。
C1, Cf, CL. . . Capacitors inv1, inv2, inv3. . . CMOS inverter . . Resistance Vin. . . Input voltage Vout. . . Output voltage.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山本 一弘 兵庫県尼崎市扶桑町1番8番 住友金属工 業株式会社エレクトロニクス技術研究所内 Fターム(参考) 2G003 AA07 AA10 AB01 AB05 AB07 AH05 2G032 AA10 AB01 AD01 AD03 AL00 2G036 AA04 AA19 AA21 BA41 BB09 CA10 CA12 9A001 BB02 BB04 BB05 JJ45 KK37 KK54 LL08  ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Kazuhiro Yamamoto 1-8 Fuso-cho, Amagasaki City, Hyogo Sumitomo Metal Industries, Ltd. Electronics Technology Research Laboratory F-term (reference) 2G003 AA07 AA10 AB01 AB05 AB07 AH05 2G032 AA10 AB01 AD01 AD03 AL00 2G036 AA04 AA19 AA21 BA41 BB09 CA10 CA12 9A001 BB02 BB04 BB05 JJ45 KK37 KK54 LL08

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】奇数段直列のCMOSインバータよりなる
インバータ回路と、前記インバータ回路の出力と入力と
の間で接続される帰還キャパシタとからなる閉ループオ
ペアンプ回路と;前記閉ループオペアンプ回路の出力電
圧を出力するための出力端子と;前記閉ループオペアン
プ回路の入力に接続された入力キャパシタと;外部から
前記入力キャパシタに既知の第1の入力電圧を入力し得
る入力端子と;を備え、前記閉ループオペアンプ回路の
出力電圧に基づいて内部素子の特性を測定しうる演算増
幅回路。
1. A closed loop operational amplifier circuit comprising an inverter circuit composed of odd-numbered series CMOS inverters and a feedback capacitor connected between an output and an input of the inverter circuit; and an output voltage of the closed loop operational amplifier circuit. An input terminal connected to an input of the closed loop operational amplifier circuit; and an input terminal capable of externally inputting a known first input voltage to the input capacitor. An operational amplifier circuit that can measure the characteristics of internal elements based on the output voltage.
【請求項2】奇数段直列のCMOSインバータよりなる
インバータ回路と、前記インバータ回路の出力と入力と
の間で接続される帰還キャパシタとからなる閉ループオ
ペアンプ回路と;前記閉ループオペアンプ回路の出力電
圧を出力するための出力端子と;前記閉ループオペアン
プ回路の入力に接続された入力キャパシタと;外部から
前記入力キャパシタに既知の第1の入力電圧を入力し得
る入力端子と;を備え、前記入力端子に入力される一定
の第1の入力電圧に対する前記出力電圧の変化から、前
記閉ループオペアンプ回路の第2の入力電圧の変化量を
求め、前記帰還キャパシタおよび前記入力キャパシタの
容量絶縁層の電荷移動量から前記容量絶縁層のリーク電
流を求める半導体装置の評価方法。
2. A closed loop operational amplifier circuit comprising an inverter circuit composed of odd-numbered stages of CMOS inverters and a feedback capacitor connected between an output and an input of the inverter circuit; and outputting an output voltage of the closed loop operational amplifier circuit. An input terminal connected to an input of the closed-loop operational amplifier circuit; and an input terminal capable of inputting a known first input voltage to the input capacitor from outside. The change amount of the second input voltage of the closed loop operational amplifier circuit is obtained from the change of the output voltage with respect to the given first input voltage, and the charge transfer amount of the feedback capacitor and the capacitance insulating layer of the input capacitor is calculated from the change amount. A method for evaluating a semiconductor device in which leakage current of a capacitor insulating layer is obtained.
【請求項3】少なくとも2つの入力キャパシタを選択的
に接続するスイッチを備えた前記閉ループオペアンプ回
路を少なくとも1つ有することを特徴とする請求項1記
載の演算増幅回路。
3. The operational amplifier circuit according to claim 1, further comprising at least one closed-loop operational amplifier circuit having a switch for selectively connecting at least two input capacitors.
【請求項4】少なくとも2つの入力キャパシタを選択的
に接続するスイッチを備えた前記閉ループオペアンプ回
路を少なくとも1つ有しており、前記スイッチを切り替
えて前記帰還キャパシタおよび各々の前記入力キャパシ
タの容量絶縁層のリーク電流を請求項2記載の方法にお
いて測定した後、該リーク電流のウエハの面内に於ける
分布を測定する事を特徴とする半導体装置の評価方法。
4. The circuit of claim 1, further comprising at least one closed-loop operational amplifier circuit having a switch for selectively connecting at least two input capacitors, wherein said switch is switched to capacitively insulate said feedback capacitor and each of said input capacitors. 3. A method of evaluating a semiconductor device, comprising: measuring a leakage current of a layer by the method according to claim 2, and measuring a distribution of the leakage current in a plane of the wafer.
【請求項5】前記入力キャパシタと前記帰還キャパシタ
とが同一の誘電率を有する容量絶縁層からなることを特
徴とする請求項1または3記載の演算増幅回路。
5. The operational amplifier circuit according to claim 1, wherein said input capacitor and said feedback capacitor are formed of a capacitive insulating layer having the same dielectric constant.
【請求項6】前記入力キャパシタと前記帰還キャパシタ
とが同一の誘電率を有する容量絶縁層からなり、前記閉
ループオペアンプ回路の第2の入力電圧の変化量に対す
る前記出力電圧の変化量に基づいて、前記入力キャパシ
タと前記帰還キャパシタとの容量比を求め、前記容量絶
縁層のウエハ面内における相対的な膜厚を求めることを
特徴とする請求項4記載の半導体装置の評価方法。
6. The input capacitor and the feedback capacitor are each formed of a capacitive insulating layer having the same dielectric constant, and based on a change in the output voltage with respect to a change in a second input voltage of the closed loop operational amplifier circuit, 5. The evaluation method for a semiconductor device according to claim 4, wherein a capacitance ratio between the input capacitor and the feedback capacitor is obtained, and a relative thickness of the capacitance insulating layer in a wafer surface is obtained.
【請求項7】前記入力キャパシタと前記帰還キャパシタ
とのそれぞれの容量絶縁層が同一の厚さに形成されてい
ることを特徴とする請求項1または3記載の演算増幅回
路。
7. The operational amplifier circuit according to claim 1, wherein the capacitance insulating layers of the input capacitor and the feedback capacitor are formed to have the same thickness.
【請求項8】前記入力キャパシタと前記帰還キャパシタ
とのそれぞれの容量絶縁層が同一の厚さに形成されてお
り、前記閉ループオペアンプ回路の第2の入力電圧の変
化量に対する前記出力電圧の変化量に基づいて、前記入
力キャパシタと前記帰還キャパシタとの容量比を求め、
前記容量絶縁層のウエハ面内における相対的な誘電率を
求めることを特徴とする請求項4記載の半導体装置の評
価方法。
8. A change amount of the output voltage with respect to a change amount of a second input voltage of the closed-loop operational amplifier circuit, wherein respective capacitance insulating layers of the input capacitor and the feedback capacitor are formed to have the same thickness. Based on, to determine the capacitance ratio of the input capacitor and the feedback capacitor,
5. The method for evaluating a semiconductor device according to claim 4, wherein a relative dielectric constant of the capacitance insulating layer in a wafer plane is obtained.
【請求項9】前記入力キャパシタと前記帰還キャパシタ
とのそれぞれの容量絶縁層が同一サイズのMOSキャパ
シタによって形成されていることを特徴とする請求項
1、3または7記載の演算増幅回路。
9. The operational amplifier circuit according to claim 1, wherein the respective capacitive insulating layers of the input capacitor and the feedback capacitor are formed by MOS capacitors of the same size.
【請求項10】奇数段直列のCMOSインバータよりな
るインバータ回路と、前記インバータ回路の出力と入力
との間で接続される帰還キャパシタとからなる閉ループ
オペアンプ回路と;前記閉ループオペアンプ回路の出力
電圧を出力するための出力端子と;前記閉ループオペア
ンプ回路の入力に接続された入力キャパシタと;外部か
ら前記入力キャパシタに既知の第1の入力電圧を入力し
得る入力端子と;を備え、前記入力キャパシタと前記帰
還キャパシタとのそれぞれの容量絶縁層が同一サイズの
キャパシタによって形成されており、第1の入力電圧に
対する前記出力電圧に基づいて、前記入力キャパシタと
前記帰還キャパシタとの容量比から、前記容量絶縁層の
ウエハ面内における相対的な界面準位を求めることを特
徴とする半導体装置の評価方法。
10. A closed-loop operational amplifier circuit comprising an inverter circuit composed of odd-numbered series CMOS inverters and a feedback capacitor connected between an output and an input of the inverter circuit; and outputting an output voltage of the closed-loop operational amplifier circuit. An input terminal connected to an input of the closed-loop operational amplifier circuit; and an input terminal capable of externally inputting a known first input voltage to the input capacitor. The respective capacitive insulating layers of the feedback capacitor are formed by capacitors of the same size, and based on the output voltage with respect to a first input voltage, the capacitance insulating layer is determined based on a capacitance ratio between the input capacitor and the feedback capacitor. Semiconductor device characterized in that relative interface states in a wafer surface of the semiconductor device are obtained. The method of evaluation.
JP35594798A 1998-12-15 1998-12-15 Evaluation method of semiconductor device Expired - Fee Related JP3311309B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019216317A (en) * 2018-06-11 2019-12-19 日立オートモティブシステムズ株式会社 Semiconductor device and sensor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019216317A (en) * 2018-06-11 2019-12-19 日立オートモティブシステムズ株式会社 Semiconductor device and sensor system
US11467016B2 (en) 2018-06-11 2022-10-11 Hitachi Astemo, Ltd. Semiconductor device and sensor system

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