JP2000174829A - Vsb receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a VSB receiver with which high speed conversion in time required until a convergence processing end in an AGC circuit and a clock reproducing circuit is made to be compatible with high performance conversion in ghost interference removal and correct clock reproduction. SOLUTION: The loop gain of an AGC circuit and that of a clock reproducing circuit 6 are increased, until a synchronizing signal (a segment synchronizing signal or a field synchronizing signal) is detected (the gain of an amplifier is increased or the range of a loop filter is made wide). Then, the loop gain of the AGC circuit 7 and that of the clock reproducing circuit 6 are made to be small (the gain of the amplifier is reduced or the band of the loop filter narrowed).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a VSB receiver, and more particularly to a Vestigial Side-Ban.
d: VSB) The present invention relates to a VSB receiver that receives a terrestrial digital broadcast signal transmitted after being subjected to modulation.

[0002]

2. Description of the Related Art As is well known, in recent years, in the field of video broadcasting, the broadcasting form is changing from analog to digital in order to provide viewers with higher quality video. The digitization of broadcasting is being carried out not only for satellite wave broadcasting, which has already been partially put into practical use, but also for terrestrial wave broadcasting. In.

[0003] Various digital modulation schemes used in digital terrestrial broadcasting are currently being devised.
As one of the methods, in the United States, a signal is represented by a multi-valued VSB (8
ATS for value VSB or 16-value VSB) modulated and transmitted
The C (Advanced Television System Committee) standard has been adopted.

[0004] A receiver for receiving terrestrial digital broadcasting is basically different from a receiver used in satellite digital broadcasting or the like if it performs digital demodulation corresponding to digital modulation applied to a signal. This can be realized by a similar configuration. Regarding a receiver that receives the multi-level VSB-modulated signal (hereinafter, referred to as a VSB receiver), a document “GUIDE TO TH” issued by the ATSC
E USE OF THE ATSC DIGITAL
TELEVISION STANDARD (Doc.
A / 54) "shows a general configuration.

FIG. 20 shows an example of the configuration of the VSB receiver disclosed in the above-mentioned document issued by the ATSC. FIG.
, A VSB receiver disclosed in the literature includes a tuner 201, a digital demodulation unit 202, a waveform equalizer 2
03, an error correction circuit 204, a transport decoder 205, a video decoder 206, and an audio decoder 207. The tuner 201
The SB-modulated signal is received. Digital demodulation unit 20
2 digitally demodulates the signal received by the tuner 201 and converts it into a digital video signal. Waveform equalizer 20
Reference numeral 3 corrects a signal waveform distortion or the like generated in a transmission path or the like. The error correction circuit 204 performs error correction on the signal waveform in which distortion and the like have been corrected. The transport decoder 205 separates the multiplexed video signal and audio signal. The video decoder 206 decodes the separated video signal. The audio decoder 207 decodes the separated audio signal.

Although not explicitly shown in the VSB receiver shown in FIG. 20, an automatic gain control (hereinafter, referred to as AGC) circuit, which is generally indispensable for processing a signal, is generally provided in the digital demodulation section 202. It is considered that the clock recovery circuit and the clock recovery circuit are naturally included as components. As is well known, the AGC circuit is a circuit that controls the gain by a negative feedback loop so that the amplitude of a predetermined reference signal is always at a constant level in order to eliminate the influence of signal attenuation or the like on a transmission line. Also, as is well known, the clock recovery circuit also recovers the clock that gives the timing for determining each data (symbol) of the digital signal, so that the clock frequency of the received signal and the clock frequency of the receiver match (synchronize). , A circuit for controlling the gain by a negative feedback loop.

The AGC circuit and the clock recovery circuit operate so that the signal to be controlled is converged to a constant value by the negative feedback loop. This affects the time taken from receiving the signal until outputting the video on the screen. Therefore, generally, the loop gain in the AGC circuit and the clock recovery circuit is fixed to a predetermined optimum value at which the convergence process is performed quickly and accurately.

[0008]

By the way, in terrestrial digital broadcasting, unlike satellite digital broadcasting,
It is necessary to consider that ghost interference occurs in the transmission path. Against this ghost disturbance, the above-mentioned VS
The B receiver considers that it is possible to remove the effect of ghost in the processing of the waveform equalizer 203. However, considering that the configuration of the VSB receiver includes the AGC circuit and the clock recovery circuit, the following problems occur depending on how the loop gain is set in each circuit.

First, consider the case where the loop gain in the AGC circuit is set large. In this case, the follow-up speed of the AGC process with respect to the feedback signal increases, so that the AGC circuit converges at high speed. However, in this case, the value of the AGC detection result (AGC voltage) tends to change, so that if a ghost interference exists in the received signal, the AGC detection result will change due to the ghost component. For this reason, there is a problem that an error occurs in the signal processing in the waveform equalizer 203 in the subsequent stage, and the ghost removal capability is deteriorated.

Here, the cause of an error in signal processing in the above case will be described with reference to an example of the configuration of the waveform equalizer 203 shown in the above document. FIG. 21 is a block diagram showing a configuration of the waveform equalizer 203 shown in the above document. FIG. 22 is a diagram illustrating the reason for the determination error in the waveform equalizer 203. The waveform equalizer 203 calculates an error signal based on the output of the feedback filter and the output through the slicer, and calculates coefficients of each filter based on the error signal. The filter coefficient gradually changes so as to remove the ghost, and the value change becomes small after the ghost is removed. That is, the waveform equalizer 203
For each data, a filter coefficient is calculated based on an error from a reference value of a region including the data. Therefore, the waveform equalizer 203 outputs the data in the +5 area (FIG. 2).
With regard to 2 (●), the error from the value of +5 is calculated, and
A filter coefficient is calculated based on the error. But,
Data originally in the +5 area is +7 due to ghost interference
In the case where the waveform has changed to the area (indicated by the mark in FIG. 22), the waveform equalizer 20
No. 3 calculates an error from the value of +7 for this data, and calculates an incorrect filter coefficient based on the error.

Similarly, consider a case where the loop gain in the clock recovery circuit is set large. in this case,
Since the follow-up speed of the clock recovery process with respect to the feedback signal increases, the convergence of the clock synchronization is performed at high speed. However, in this case, if ghost interference exists in the received signal,
There is a problem that the ghost component is sensitively responded (the clock frequency is likely to fluctuate), jitter occurs in the reproduced clock of the VSB receiver, and an error occurs in the received signal.

Next, consider the case where the loop gains in the AGC circuit and the clock recovery circuit are set small. In this case, in the AGC circuit, the follow-up speed of the AGC process for the feedback signal is slowed, so that the ghost removal capability is increased. In the clock recovery circuit, the follow-up speed of the clock recovery process for the feedback signal is slowed, so that the jitter is reduced. An accurate clock can be reproduced without occurrence. However, in this case, as described above, the time required for the loop gain of each circuit to complete the convergence, that is, the time required for receiving the video signal and outputting the video on the screen becomes longer. come.

Therefore, it is an object of the present invention to achieve both high speed of the time required for the convergence in the AGC circuit to be completed and high performance of ghost interference removal, and further to the completion of the convergence in the clock recovery circuit. Faster time,
An object of the present invention is to provide a VSB receiver compatible with accurate clock recovery.

[0014]

According to a first aspect of the present invention, a segment synchronization signal is provided at the beginning of each segment.
A terrestrial digital broadcast signal is transmitted in which video and audio data configured in a format having a field synchronization signal at the head of each field is subjected to multi-level VSB (8-level or 16-level VSB) modulation and transmitted. A VSB receiver, comprising: a segment synchronization detecting means for detecting a segment synchronization signal from a received multilevel VSB modulated signal; and a segment synchronization signal based on the segment synchronization signal detected by the segment synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter so that the level is constant, wherein the automatic gain control means According to the sync detection signal, a loop filter is used until a segment sync signal is detected. The band, after being detected and controls the loop filter to a narrow band.

A second invention is an invention according to the first invention, wherein the loop filters are a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means is The bandwidth of the loop filter is controlled by switching the value of a time constant determined by a resistor and a capacitor by a switching process according to a segment synchronization detection signal.

A third invention is an invention according to the first invention, wherein the loop filter is a digital filter capable of varying a bandwidth according to a separately provided filter coefficient, and the automatic gain control means includes a segment synchronization detecting means. The bandwidth of the loop filter is controlled by switching the filter coefficient given to the digital filter according to the signal.

As described above, according to the first to third aspects of the present invention, the loop filter of the automatic gain control means transmits the segment synchronizing signal over a wide band so as to shorten the detection time until the segment synchronizing signal is detected. After the detection, the band is switched to a narrow band to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and improve the ghost elimination performance against ghost interference.

According to a fourth aspect of the present invention, video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are multi-valued VSB (8- or 16-valued). VSB)
A VSB receiver for receiving a terrestrial digital broadcast signal that is modulated and transmitted, wherein the received multi-level VSB is received.
From the modulated signal, a segment synchronization detection means for detecting a segment synchronization signal, and a gain detector based on the segment synchronization signal detected by the segment synchronization detection means, so that the level of the segment synchronization signal is constant. Automatic gain control means for feedback-controlling a loop gain via an amplifier and a loop filter, wherein the automatic gain control means detects a segment synchronization signal according to a segment synchronization detection signal indicating whether or not a segment synchronization signal has been detected. Until the gain is detected, the gain of the amplifier is controlled to be small.

A fifth invention is an invention according to the fourth invention, wherein the amplifier comprises two of a large-gain operational amplifier and a small-gain operational amplifier, and the automatic gain control means includes a segment synchronous The gain of the amplifier is controlled by switching the operational amplifier to either one according to the detection signal.

A sixth invention is a invention according to the fourth invention, wherein the amplifier is a multiplier capable of changing an amplification value according to a separately given coefficient, and the automatic gain control means is provided in accordance with the segment synchronization detection signal. The gain of the amplifier is controlled by switching the coefficient given to the multiplier.

As described above, according to the fourth to sixth aspects of the present invention, the amplification gain of the automatic gain control means is set to a large value so as to shorten the detection time until the segment synchronization signal is detected. Is detected, the value is switched to a small value to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and improve the ghost elimination performance against ghost interference.

According to a seventh aspect of the present invention, video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is a multi-level VSB (8-level or 16-level). VSB)
A VSB receiver for receiving a terrestrial digital broadcast signal that is modulated and transmitted, wherein the received multi-level VSB is received.
From the modulated signal, a segment synchronization detection means for detecting a segment synchronization signal, and a gain detector based on the segment synchronization signal detected by the segment synchronization detection means, so that the level of the segment synchronization signal is constant. Automatic gain control means for feedback controlling the loop gain through an amplifier and a loop filter, based on the segment synchronization signal detected by the segment synchronization detection means, so that the clock frequency to be reproduced matches the clock frequency of the received signal, A clock frequency detector, an amplifier, a loop filter, and a clock recovery unit that feedback-controls a loop gain via a variable clock oscillator, wherein the automatic gain control unit and the clock recovery unit notify the presence or absence of a segment synchronization signal. According to the synchronization detection signal, A loop filter until note synchronization signal is detected in the wide band, after being detected and controlling respective loop filter to a narrow band.

An eighth invention is an invention according to the seventh invention, wherein the loop filter of the automatic gain control means and the loop filter of the clock recovery means are each composed of a resistor and a capacitor. A loop filter, wherein the automatic gain control means and the clock recovery means control the bandwidth of the loop filter by switching the value of the time constant determined by the resistor and the capacitor in accordance with the segment synchronization detection signal by switching processing. Features.

A ninth invention is a invention according to the seventh invention, wherein both the automatic gain control means and the loop filter of the clock recovery means are digital filters capable of varying the bandwidth in accordance with separately provided filter coefficients. ,
The automatic gain control means and the clock recovery means control the bandwidth of the loop filter by switching the filter coefficient applied to the digital filter according to the segment synchronization detection signal.

A tenth invention is according to the seventh invention, wherein the loop filter of the automatic gain control means is a wide-band loop filter and a narrow-band loop filter comprising a resistor and a capacitor, The loop filter of the clock recovery means is a digital filter capable of varying the bandwidth in accordance with a separately provided filter coefficient. By switching, the clock regenerating means, according to the segment synchronization detection signal,
By switching the filter coefficients applied to the digital filters, the bandwidth of each loop filter is controlled.

An eleventh invention is an invention according to the seventh invention, wherein the loop filter of the automatic gain control means is a digital filter whose bandwidth can be varied according to a separately provided filter coefficient, and The loop filter is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means switches the filter coefficient given to the digital filter in accordance with the segment synchronization detection signal, so that the clock recovery means Is characterized in that the bandwidth of a loop filter is controlled by switching the value of a time constant determined by a resistor and a capacitor according to a segment synchronization detection signal by switching processing.

As described above, according to the seventh to eleventh aspects, the loop filter of the automatic gain control means and the clock recovery means is provided in a wide band so as to shorten the detection time until the detection of the segment synchronization signal. After the detection of the segment synchronization signal, the band is switched to a narrow band to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and to improve the ghost removal performance against the ghost interference. Since no error occurs, no error occurs in the received signal.

According to a twelfth aspect of the present invention, video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are represented by a multi-level VSB (8-level or 16-level). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
A segment synchronization detecting means for detecting a segment synchronization signal from the signal subjected to the SB modulation, and a gain detector for controlling the level of the segment synchronization signal to be constant based on the segment synchronization signal detected by the segment synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the segment synchronization signal detected by the segment synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
The automatic gain control means and the clock recovery means increase the gain of the amplifier until the segment synchronization signal is detected, and decrease the gain of the amplifier after the detection, in accordance with the segment synchronization detection signal indicating whether or not the segment synchronization signal is detected. Each of them is controlled.

A thirteenth invention is an invention according to the twelfth invention, wherein the amplifiers of the automatic gain control means and the clock recovery means are both composed of a large-gain operational amplifier and a small-gain operational amplifier. The automatic gain control means and the clock recovery means control the gain of each amplifier by switching the operational amplifier to one of them according to the segment synchronization detection signal.

A fourteenth invention is an invention according to the twelfth invention, wherein the amplifier of the automatic gain control means and the amplifier of the clock recovery means are both multipliers capable of varying the amplification value according to separately given coefficients. The gain control means and the clock recovery means, according to the segment synchronization detection signal,
It is characterized in that the gain of each amplifier is controlled by switching the coefficient given to the multiplier.

A fifteenth invention is an invention according to the twelfth invention, wherein the amplifier of the automatic gain control means is constituted by two of a large gain operational amplifier and a small gain operational amplifier, and Is a multiplier that can vary the amplification value according to a separately given coefficient, the automatic gain control means according to the segment synchronization detection signal,
By switching the operational amplifier to either one, the clock recovery means controls the gain of each amplifier by switching the coefficient given to the multiplier according to the segment synchronization detection signal.

A sixteenth invention is a invention according to the twelfth invention, wherein the amplifier of the automatic gain control means is a multiplier capable of changing an amplification value according to a separately given coefficient,
The amplifier of the clock recovery means is composed of two of a large gain operational amplifier and a small gain operational amplifier, and the automatic gain control means operates in accordance with the segment synchronization detection signal.
By switching the coefficient to be applied to the multiplier, the clock recovery means controls the gain of each amplifier by switching the operational amplifier to one of the operational amplifiers according to the segment synchronization detection signal.

As described above, according to the twelfth to sixteenth aspects, the amplification gain of the automatic gain control means and the clock recovery means is set to a large value so as to shorten the detection time until the segment synchronization signal is detected. After detecting the segment synchronizing signal, the signal is switched to a small value to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and to improve the ghost removal performance against the ghost interference. Since no error occurs, no error occurs in the received signal.

According to a seventeenth aspect, video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is a multi-level VSB (8-level or 16-level). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
A segment synchronization detecting means for detecting a segment synchronization signal from the signal subjected to the SB modulation, and a gain detector for controlling the level of the segment synchronization signal to be constant based on the segment synchronization signal detected by the segment synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the segment synchronization signal detected by the segment synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
The automatic gain control means controls the loop filter to a wide band until the segment synchronization signal is detected, and controls the loop filter to a narrow band after the detection, in accordance with the segment synchronization detection signal notifying the presence or absence of the detection of the segment synchronization signal,
The clock regenerating means controls the gain of the amplifier until the segment synchronization signal is detected, and controls the gain of the amplifier after detection, in accordance with the segment synchronization detection signal.

An eighteenth invention is according to the seventeenth invention, wherein the loop filter of the automatic gain control means comprises:
A wide-band loop filter and a narrow-band loop filter each composed of a resistor and a capacitor. The amplifier of the clock recovery means is composed of two operational amplifiers having a large gain and a small gain. In accordance with the segment synchronization detection signal, the value of the time constant determined by the resistor and the capacitor is switched by switching processing to control the bandwidth of the loop filter. , The gain of the amplifier is controlled.

A nineteenth invention is according to the seventeenth invention, wherein the loop filter of the automatic gain control means comprises:
A wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor; the amplifier of the clock recovery unit is a multiplier that can vary the amplification value according to a separately given coefficient; and the automatic gain control unit is The bandwidth of the loop filter is controlled by switching the value of the time constant determined by the resistor and the capacitor by the switching process according to the detection signal, and the clock recovery unit switches the coefficient to be applied to the multiplier according to the segment synchronization detection signal. And the gain of the amplifier is controlled.

A twentieth invention is according to the seventeenth invention, wherein the loop filter of the automatic gain control means comprises:
A digital filter whose bandwidth can be varied according to a separately given filter coefficient. The amplifier of the clock recovery means is composed of two high-gain operational amplifiers and a small-gain operational amplifier. The bandwidth of the loop filter is controlled by switching the filter coefficient given to the digital filter according to the signal, and the clock recovery means controls the gain of the amplifier by switching the operational amplifier to either one according to the segment synchronization detection signal. It is characterized by the following.

A twenty-first invention is an invention according to the seventeenth invention, wherein the loop filter of the automatic gain control means comprises:
A digital filter capable of varying the bandwidth according to a separately provided filter coefficient, the amplifier of the clock recovery means is a multiplier capable of varying the amplification value according to the separately provided coefficient, and the automatic gain control means is provided according to a segment synchronization detection signal. The bandwidth of the loop filter is controlled by switching the filter coefficient applied to the digital filter, and the clock recovery means controls the gain of the amplifier by switching the coefficient applied to the multiplier in accordance with the segment synchronization detection signal. And

As described above, according to the seventeenth to twenty-first aspects, the loop filter of the automatic gain control means and the amplification gain of the clock recovery means are set so that the detection time is shortened until the detection of the segment synchronization signal. After detecting the segment synchronizing signal to a wide band and a large value, it is switched to a narrow band and a small value to improve ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and to improve the ghost removal performance against the ghost interference. Since no error occurs, no error occurs in the received signal.

According to a twenty-second aspect of the present invention, video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are multi-valued VSB (8- or 16-valued). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
A segment synchronization detecting means for detecting a segment synchronization signal from the signal subjected to the SB modulation, and a gain detector for controlling the level of the segment synchronization signal to be constant based on the segment synchronization signal detected by the segment synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the segment synchronization signal detected by the segment synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
The automatic gain control means increases the gain of the amplifier until the segment synchronization signal is detected, according to the segment synchronization detection signal that notifies the presence or absence of the detection of the segment synchronization signal,
After the detection, the gain of the amplifier is controlled to be small, and the clock recovery means adjusts the loop filter to a wide band until the segment synchronization signal is detected, and narrows the loop filter after the detection, according to the segment synchronization detection signal. Is controlled.

According to a twenty-third aspect, the invention according to the twenty-second aspect, wherein the amplifier of the automatic gain control means comprises two of a large-gain operational amplifier and a small-gain operational amplifier. Are a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means switches the operational amplifier to one of them according to the segment synchronization detection signal, so that the amplifier gain And the clock recovery means switches the value of the time constant determined by the resistor and the capacitor by switching processing according to the segment synchronization detection signal,
It is characterized in that the bandwidth of the loop filter is controlled.

A twenty-fourth aspect of the present invention is the invention according to the twenty-second aspect, wherein the amplifier of the automatic gain control means comprises two of a large gain operational amplifier and a small gain operational amplifier. Is a digital filter that can vary the bandwidth according to a separately given filter coefficient, the automatic gain control means controls the amplifier gain by switching the operational amplifier to either one according to the segment synchronization detection signal, The clock regenerating means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter according to the segment synchronization detection signal.

A twenty-fifth invention is the invention according to the twenty-second invention, wherein the amplifier of the automatic gain control means is a multiplier capable of changing an amplification value according to a separately given coefficient,
The loop filter of the clock recovery unit is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control unit switches the coefficient given to the multiplier according to the segment synchronization detection signal. The gain of the amplifier is controlled, and the clock recovery means controls the bandwidth of the loop filter by switching the value of the time constant determined by the resistor and the capacitor by switching processing in accordance with the segment synchronization detection signal.

A twenty-sixth invention is the invention according to the twenty-second invention, wherein the amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately given coefficient,
The loop filter of the clock recovery means is a digital filter capable of varying the bandwidth in accordance with a separately provided filter coefficient. The clock recovery means controls the bandwidth of the loop filter by switching the filter coefficient applied to the digital filter according to the segment synchronization detection signal.

As described above, according to the twenty-second to twenty-sixth aspects, the amplification gain of the automatic gain control means and the loop filter of the clock recovery means are set so that the detection time becomes short until the segment synchronization signal is detected. After detecting the segment synchronization signal, the value is switched to a small value and a narrow band to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal and to improve the ghost removal performance against the ghost interference. Since no error occurs, no error occurs in the received signal.

According to a twenty-seventh aspect, video and audio data formed in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are represented by a multi-level VSB (8-level or 16-level). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detecting means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detecting means. Automatic gain control means for feedback-controlling the loop gain via an amplifier and a loop filter, wherein the automatic gain control means detects a field synchronization signal in accordance with a field synchronization detection signal indicating whether or not a field synchronization signal has been detected. Until the loop filter is controlled to a wide band, and after the loop filter is detected, the loop filter is controlled to a narrow band.

A twenty-eighth invention is an invention according to the twenty-seventh invention, wherein the loop filter is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means is The bandwidth of the loop filter is controlled by switching the value of a time constant determined by a resistor and a capacitor by a switching process according to a field synchronization detection signal.

A twenty-ninth invention is an invention according to the twenty-seventh invention, wherein the loop filter is a digital filter capable of varying a bandwidth in accordance with a separately provided filter coefficient, and the automatic gain control means comprises: The bandwidth of the loop filter is controlled by switching a filter coefficient given to the digital filter according to a signal.

As described above, according to the twenty-seventh to twenty-ninth aspects, the loop filter of the automatic gain control means is applied to the field synchronization signal over a wide band so as to shorten the detection time until the field synchronization signal is detected. After the detection, the band is switched to a narrow band to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the field synchronization signal and improve the ghost removal performance against the ghost interference.

According to a thirtieth aspect of the present invention, video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are multi-valued VSB (8-valued or 16-valued). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detecting means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detecting means. Automatic gain control means for feedback-controlling the loop gain via an amplifier and a loop filter, wherein the automatic gain control means detects a field synchronization signal in accordance with a field synchronization detection signal indicating whether or not a field synchronization signal has been detected. Until the gain of the amplifier is controlled, the gain of the amplifier is controlled to be small after detection.

A thirty-first aspect is an invention according to the thirty-third aspect, wherein the amplifier is composed of two high-gain operational amplifiers and a small-gain operational amplifier, and the automatic gain control means controls the field synchronization. The gain of the amplifier is controlled by switching the operational amplifier to either one according to the detection signal.

A thirty-second invention is a invention according to the thirtieth invention, wherein the amplifier is a multiplier capable of varying an amplification value according to a separately given coefficient, and the automatic gain control means is provided in accordance with the field synchronization detection signal. The gain of the amplifier is controlled by switching the coefficient given to the multiplier.

As described above, according to the thirtieth to thirty-second aspects, the amplification gain of the automatic gain control means is set to a large value so as to shorten the detection time until the field synchronization signal is detected. Is detected, the value is switched to a small value to improve the ghost removal performance, and the loop gain is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the field synchronization signal and improve the ghost removal performance against the ghost interference.

According to a thirty-third aspect, video and audio data formed in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is a multi-level VSB (8-level or 16-level). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detection means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the field synchronization signal detected by the field synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
The automatic gain control means and the clock recovery means adjust the loop filter to a wide band until the field sync signal is detected, and to narrow the loop filter after the field sync signal is detected, according to the field sync detection signal indicating whether or not the field sync signal is detected. , Respectively.

A thirty-fourth invention is an invention according to the thirty-third invention, wherein the loop filter of the automatic gain control means and the loop filter of the clock recovery means are each composed of a resistor and a capacitor. A loop filter, wherein the automatic gain control means and the clock recovery means switch the value of the time constant determined by the resistor and the capacitor by switching processing in accordance with the field synchronization detection signal, thereby controlling the bandwidth of the loop filter, respectively. Features.

A thirty-fifth invention is a invention according to the thirty-third invention, wherein the automatic gain control means and the loop filter of the clock recovery means are digital filters capable of varying the bandwidth in accordance with separately provided filter coefficients. The automatic gain control means and the clock recovery means control the bandwidth of the loop filter by switching the filter coefficient applied to the digital filter according to the field synchronization detection signal.

A thirty-sixth invention is a invention according to the thirty-third invention, wherein the loop filter of the automatic gain control means comprises:
A wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor. By switching the value of the time constant determined by the resistor and the capacitor by the switching process in accordance with the field synchronization detection signal, the clock regenerating means can perform
By switching the filter coefficients applied to the digital filters, the bandwidth of each loop filter is controlled.

A thirty-seventh aspect is an invention according to the thirty-third aspect, wherein the loop filter of the automatic gain control means comprises:
A digital filter whose bandwidth can be varied according to a separately given filter coefficient, wherein the loop filter of the clock recovery means is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means is: By switching the filter coefficient to be applied to the digital filter according to the field synchronization detection signal, the clock recovery means switches the value of the time constant determined by the resistor and the capacitor by switching processing according to the field synchronization detection signal. It is characterized by controlling the bandwidth.

As described above, according to the thirty-third to thirty-seventh aspects, the loop filter of the automatic gain control means and the clock recovery means is provided over a wide band so as to shorten the detection time until the field synchronization signal is detected. After detecting the field synchronization signal, the band is switched to a narrow band to improve the ghost removal performance, and the loop gain is controlled. This makes it possible to shorten the detection time of the field synchronization signal and improve the ghost elimination performance against ghost interference even when the received signal has ghost interference, and furthermore, jitter is generated in the reproduction clock of the VSB receiver. Since no error occurs, no error occurs in the received signal.

According to a thirty-eighth aspect, video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are multi-valued VSB (8- or 16-valued). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detection means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the field synchronization signal detected by the field synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
The automatic gain control means and the clock recovery means increase the gain of the amplifier until the field synchronization signal is detected, and decrease the gain of the amplifier after the detection, in accordance with the field synchronization detection signal indicating whether or not the field synchronization signal is detected. Each of them is controlled.

A thirty-ninth aspect is an invention according to the thirty-eighth aspect, wherein the amplifiers of the automatic gain control means and the clock recovery means are both composed of a large gain operational amplifier and a small gain operational amplifier. The automatic gain control means and the clock recovery means control the gain of each amplifier by switching the operational amplifier to one of them according to the field synchronization detection signal.

A fortieth invention is according to the thirty-eighth invention, wherein the amplifiers of the automatic gain control means and the clock recovery means are both multipliers capable of varying the amplification value according to separately given coefficients. The gain control means and the clock recovery means, according to the field synchronization detection signal,
It is characterized in that the gain of each amplifier is controlled by switching the coefficient given to the multiplier.

A forty-first invention is an invention according to the thirty-eighth invention, wherein the amplifier of the automatic gain control means comprises two of a large gain operational amplifier and a small gain operational amplifier. Is a multiplier that can vary the amplification value according to a separately given coefficient, the automatic gain control means according to the field synchronization detection signal,
By switching the operational amplifier to either one, the clock recovery means controls the gain of each amplifier by switching the coefficient given to the multiplier according to the field synchronization detection signal.

A forty-second invention is an invention according to the thirty-eighth invention, wherein the amplifier of the automatic gain control means is a multiplier capable of changing an amplification value according to a separately given coefficient,
The amplifier of the clock recovery means is composed of two of a large-gain operational amplifier and a small-gain operational amplifier, and the automatic gain control means operates in accordance with the field synchronization detection signal.
The clock recovery means controls the gain of each amplifier by switching one of the operational amplifiers in accordance with the field synchronization detection signal by switching the coefficient given to the multiplier.

As described above, according to the thirty-eighth to forty-second aspects, the amplification gain of the automatic gain control means and the clock recovery means is set to a large value so as to shorten the detection time until the field synchronization signal is detected. After detecting the field synchronization signal, the value is switched to a small value to improve the ghost removal performance, and the loop gain is controlled. This makes it possible to shorten the detection time of the field synchronization signal and improve the ghost elimination performance against ghost interference even when the received signal has ghost interference, and furthermore, jitter is generated in the reproduction clock of the VSB receiver. Since no error occurs, no error occurs in the received signal.

According to a forty-third aspect, video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are multi-valued VSB (8-value or 16-value). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detection means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the field synchronization signal detected by the field synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
Automatic gain control means controls the loop filter to a wide band until the field sync signal is detected, and controls the loop filter to a narrow band after the field sync signal is detected, according to the field sync detection signal indicating whether or not the field sync signal is detected,
The clock regenerating means controls the gain of the amplifier until the field synchronization signal is detected, and controls the gain of the amplifier after detection, in accordance with the field synchronization detection signal.

A forty-fourth invention is an invention according to the forty-third invention, wherein the loop filter of the automatic gain control means comprises:
A wide-band loop filter and a narrow-band loop filter each composed of a resistor and a capacitor. The amplifier of the clock recovery means is composed of two operational amplifiers having a large gain and a small gain. By switching the value of the time constant determined by the resistor and the capacitor in accordance with the field synchronization detection signal by switching processing, the bandwidth of the loop filter is controlled, and the clock recovery means switches one of the operational amplifiers according to the field synchronization detection signal. The gain of the amplifier is controlled by switching to.

A forty-fifth invention is an invention according to the forty-third invention, wherein the loop filter of the automatic gain control means comprises:
A wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, wherein the amplifier of the clock recovery means is a multiplier capable of varying the amplification value according to a separately given coefficient, and the automatic gain control means The bandwidth of the loop filter is controlled by switching the value of the time constant determined by the resistor and the capacitor by the switching process according to the detection signal, and the clock recovery unit switches the coefficient to be applied to the multiplier according to the field synchronization detection signal. And the gain of the amplifier is controlled.

A forty-sixth invention is a invention according to the forty-third invention, wherein the loop filter of the automatic gain control means comprises:
A digital filter whose bandwidth can be varied according to a separately given filter coefficient. The amplifier of the clock recovery means is composed of two operational amplifiers having a large gain and a small gain. The bandwidth of the loop filter is controlled by switching the filter coefficient given to the digital filter in accordance with the signal, and the clock recovery means controls the gain of the amplifier by switching the operational amplifier to either one in accordance with the field synchronization detection signal. It is characterized by the following.

A forty-seventh invention is an invention according to the forty-third invention, wherein the loop filter of the automatic gain control means comprises:
A digital filter capable of varying the bandwidth according to a separately provided filter coefficient, the amplifier of the clock recovery means is a multiplier capable of varying the amplification value according to the separately provided coefficient, and the automatic gain control means is provided according to a field synchronization detection signal. The bandwidth of the loop filter is controlled by switching the filter coefficient applied to the digital filter, and the clock recovery means controls the gain of the amplifier by switching the coefficient applied to the multiplier in accordance with the field synchronization detection signal. And

As described above, according to the forty-third to forty-seventh aspects, the loop filter of the automatic gain control means and the amplification gain of the clock recovery means are set so that the detection time becomes short until the field synchronization signal is detected. After detecting the field synchronization signal to a wide band and a large value, it is switched to a narrow band and a small value to improve ghost removal performance, and the loop gain is controlled. This makes it possible to shorten the detection time of the field synchronization signal and improve the ghost elimination performance against ghost interference even when the received signal has ghost interference, and furthermore, jitter is generated in the reproduction clock of the VSB receiver. Since no error occurs, no error occurs in the received signal.

According to a forty-eighth aspect, video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is a multi-level VSB (8-level or 16-level). VS
B) A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being modulated, wherein the received multilevel V
Field synchronization detection means for detecting a field synchronization signal from a signal subjected to SB modulation, and a gain detector for controlling the level of the field synchronization signal to be constant based on the field synchronization signal detected by the field synchronization detection means. And automatic gain control means for feedback controlling the loop gain through the amplifier and the loop filter, based on the field synchronization signal detected by the field synchronization detection means,
Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be recovered matches the clock frequency of the received signal,
Automatic gain control means increases the gain of the amplifier until a field synchronization signal is detected, according to a field synchronization detection signal indicating whether or not a field synchronization signal has been detected,
After the detection, the gain of the amplifier is controlled to be small, and the clock regenerating means adjusts the loop filter to a wide band until the field synchronization signal is detected according to the field synchronization detection signal, and narrows the loop filter after the detection. Is controlled.

The forty-ninth invention is the invention according to the forty-eighth invention, wherein the amplifier of the automatic gain control means is composed of two operational amplifiers having a large gain and a small gain, and Are a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain control means switches the operational amplifier to one of them according to the field synchronization detection signal, thereby obtaining the gain of the amplifier. The clock recovery means switches the value of the time constant determined by the resistor and the capacitor by switching processing according to the field synchronization detection signal,
It is characterized in that the bandwidth of the loop filter is controlled.

A fiftyth invention is an invention according to the forty-eighth invention, wherein the amplifier of the automatic gain control means comprises two of a large gain operational amplifier and a small gain operational amplifier. Is a digital filter that can vary the bandwidth according to a separately given filter coefficient, the automatic gain control means controls the amplifier gain by switching the operational amplifier to either one according to the field synchronization detection signal, The clock regenerating means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter according to the field synchronization detection signal.

A fifty-first invention is an invention according to the forty-eighth invention, wherein the amplifier of the automatic gain control means is a multiplier capable of changing an amplification value according to a separately given coefficient,
The loop filter of the clock recovery means is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor. The gain of the amplifier is controlled, and the clock recovery means controls the bandwidth of the loop filter by switching the value of the time constant determined by the resistor and the capacitor by switching processing in accordance with the field synchronization detection signal.

A fifty-second invention is an invention according to the forty-eighth invention, wherein the amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately given coefficient,
The loop filter of the clock recovery means is a digital filter capable of varying the bandwidth in accordance with a separately provided filter coefficient. The clock recovery means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter according to the field synchronization detection signal.

As described above, according to the forty-eighth to fifty-second inventions, the amplification gain of the automatic gain control means and the loop filter of the clock recovery means are set so that the detection time becomes short until the field synchronization signal is detected. After detecting the field sync signal to a large value and a wide band, it is switched to a small value and a narrow band to improve the ghost removal performance, and the loop gain is controlled. This makes it possible to shorten the detection time of the field synchronization signal and improve the ghost elimination performance against ghost interference even when the received signal has ghost interference, and furthermore, jitter is generated in the reproduction clock of the VSB receiver. Since no error occurs, no error occurs in the received signal.

[0078]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in order by taking a VSB receiver for receiving a terrestrial digital broadcast signal subjected to 8-level VSB modulation defined by the ATSC standard as an example. I do.

First, an outline of a VSB receiver using the configuration of each embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a VSB receiver according to one embodiment of the present invention. In FIG. 1, a VSB receiver according to an embodiment of the present invention includes a tuner 1, a digital demodulation unit 2, a waveform equalizer 10, an error correction circuit 11, a transport decoder 13, a video decoder 16, , An audio decoder 17. Also, the digital demodulation unit 2
VSB detector 3, AD converter 4, synchronization detection circuit 5
, A clock recovery circuit 6 and an AGC circuit 7.

The 8-level VSB-modulated signal is supplied to tuner 1
Is input to Tuner 1 converts the eight-level VSB modulated signal to I
Convert to F signal. The VSB detector 3 detects the IF signal and performs VSB demodulation. AD converter 4 has a VS
The B-demodulated analog signal is converted into 8-level digital data and output. The digital data output from the AD converter 4 is data configured in the format shown in FIG. 2 according to the ATSC standard. , 22 exist, one segment is composed of 832 symbol data, and one field is composed of 313 segment data. FIG. 3 shows the data structure of the segment synchronization signal 20 and the field synchronization signals 21 and 22. In FIG. 3, the segment synchronization signal 20 has four values out of eight-valued data represented by −7 to +7.
Symbol data is "+5, -5, -5, +5"
It consists of a specific pattern. Further, the field synchronization signals 21 and 22 are composed of 828 symbol data of a predetermined specific pattern in a level range of -5 to +5.

The synchronization detection circuit 5 detects the segment synchronization signal 20 or the field synchronization signals 21 and 22 from the digital data output from the AD converter 4. The method of detecting a synchronization signal performed by the synchronization detection circuit 5 will be described in an embodiment described later. The AGC circuit 7 sends a signal to the VSB detector 3 based on the synchronization signal detected by the synchronization detection circuit 5 so that the data level of the segment synchronization signal 20 or the field synchronization signals 21 and 22 becomes “−5 to +5”. AGC voltage 8 is feedback-controlled. The clock recovery circuit 6 sends a clock signal to the AD converter 4 based on the synchronization signal detected by the synchronization detection circuit 5 so that the clock frequency of the VSB receiver matches the clock frequency of the transmitted digital data. 9 is feedback-controlled.

On the other hand, the digital data converted by the AD converter 4 is output to the waveform equalizer 10. The waveform equalizer 10 corrects signal waveform distortion or the like generated in a transmission path or the like (removes ghost interference). Error correction circuit 11
Performs error correction on a signal waveform in which distortion or the like has been corrected, and outputs the resulting signal as a transport stream 12. The transport decoder 13 separates the transport stream 12 into video data 14 and audio data 15 of an arbitrary channel. The video decoder 16 decodes the separated video data 14 and outputs it as a video signal 18. The audio decoder 17 decodes the separated audio data 15 and outputs it as an audio signal 19.

Next, in the VSB receiver according to one embodiment of the present invention having the above configuration, a more detailed description of the VSB receiver of the present invention will be given in order based on the configuration that the digital demodulation unit 2 can take.

(First Embodiment) FIG. 4 shows a first embodiment of the present invention.
It is a block diagram which shows the structure of the digital demodulation part 2 in the VSB receiver which concerns on embodiment. In FIG. 4, the digital demodulation unit 2 of the first embodiment includes a VSB detector 3
, An AD converter 4, a segment synchronization detection circuit 28,
It includes a gain detector 25, an amplifier 26, a wide band loop filter 32, a narrow band loop filter 33, a switching circuit 34, and a clock recovery circuit 6.

As shown in FIG. 4, in the digital demodulation unit 2 of the first embodiment, the synchronization detection circuit 5 shown in FIG. , A wideband loop filter 32,
It comprises a narrow band loop filter 33 and a switching circuit 34. In FIG. 4, portions having the same configuration as in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, each configuration of the digital demodulation unit 2 of the first embodiment will be described in order.

The digital data (FIG. 2) output from the AD converter 4 is input to the waveform equalizer 10 and the segment synchronization detection circuit 28. Segment synchronization detection circuit 28
Performs segment synchronization detection on input digital data, and outputs a detected segment synchronization signal 20 to a gain detector 25 and a segment synchronization detection signal 30 for determining whether or not it has been detected to a switching circuit 34. Here, the segment synchronization detection method performed by the segment synchronization detection circuit 28 will be described with further reference to FIG. FIG.
6 is a flowchart illustrating a procedure of segment synchronization detection performed by a segment synchronization detection circuit.

First, when the segment synchronization detecting circuit 28 starts the segment synchronization detecting operation, the segment synchronization detecting signal 30 is initialized to a low level "L" (step S).
101). Next, the segment synchronization detection circuit 28 determines whether or not a pattern of symbol data with a sign of “+, −, −, +” has been detected (step S102). When a pattern is detected in the determination in step S102, the segment synchronization detection circuit 28 sets the segment synchronization detection signal 30 to a high level “H” and sets the number N of segment synchronization pattern detections to “1” (step S103). Then, the segment synchronization detection circuit 28 determines in step S102
Is detected for the first time, the code pattern of the data after 832 symbols from the detection of the symbol data pattern of “+, −, −, +” is similarly “+, −, −, +”. A determination is made (step S104). When a pattern is detected in the determination in step S104, the segment synchronization detection circuit 28 sets the value of the number N of times of segment synchronization pattern detection to 1
Number is increased (step S106). This step S104
And the procedure of S106 are repeated until N = M (M is the number of segment synchronization pattern detections at which the segment synchronization signal detection is determined and is arbitrarily determined in advance)
The segment synchronization detection is determined (step S107).
If the pattern cannot be detected in the determination in step S104, the segment synchronization detection circuit 28 resets the number N of segment synchronization pattern detections (step S104).
105), the detection of the code pattern of the symbol data "+,-,-, +" is started again from the beginning.

Then, even after the number N of segment synchronization pattern detections reaches the value M and the segment synchronization signal detection is determined, the segment synchronization detection circuit 28 continues to change the code pattern of the data after 832 symbols to "+,-,-". , + "
Is determined (step S109). If no pattern is detected in the determination in step S109, the segment synchronization detection circuit 28 increases the value of the segment synchronization pattern non-detection frequency L initialized in step S108 by one (step S110). This step S109-
If the procedure of S110 is repeated and L = I (I is the number of undetected segment synchronization patterns in which segment synchronization signal undetection is determined and is arbitrarily determined in advance), the segment synchronization detection circuit 28 Then, it is determined that the segment synchronization detection has transitioned to undetermined, and the process returns to step S101 to perform processing for segment synchronization detection determination again (step S111).

The gain detector 25 controls the level of the segment synchronization signal 20 of the digital data output from the AD converter 4 to a value of -5 to +5 which is a reference level (defined by the ATSC standard). A determination signal for controlling the gain of the VSB detector 3 is output to the amplifier 26. Specifically, the gain detector 25 adjusts the level of the segment synchronization signal 20 detected by the segment synchronization detection circuit 28 to -5 to +
If the level is smaller than 5 (for example, -3 to +3),
On the other hand, when the determination signal for increasing the gain of the VSB detector 3 is large (for example, −7 to +7), a determination signal for decreasing the gain of the VSB detector 3 is output. The amplifier 26 receives the determination signal output from the gain detector 25, performs predetermined amplification, and outputs the amplified signal to the wideband loop filter 32 and the narrowband loop filter 33.

The wideband loop filter 32 has a higher loop gain in the AGC circuit 7 (higher AGC followability), that is, a priority is given to shortening the detection time of the segment synchronization signal 20 over ghost interference removal performance. , Filter coefficients are set. On the other hand, in the narrow band loop filter 33, the loop gain in the AGC circuit 7 is reduced (the AGC tracking performance is poor), that is, the ghost interference removal performance is prioritized over the shortening of the detection time of the segment synchronization signal 20. , Filter coefficients are set. After the amplified determination signal output from the amplifier 26 passes through the wide band loop filter 32 and the narrow band loop filter 33, respectively, the switching circuit 3
4 is input.

The switching circuit 34 inputs the signal passed through the wide band loop filter 32 and the signal passed through the narrow band loop filter 33, and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28. Then, according to the segment synchronization detection signal 30, when the segment synchronization detection signal 30 is “L” (the segment synchronization signal 20 is not detected), the switching circuit 34 When the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20 is detected), the signal passing through the narrow band loop filter 33 is selectively switched, and the AGC voltage 8 is set to VSB.
The signal is fed back to the detector 3.

Here, the results of specific experiments will be described.
In this experiment, the ratio of the loop gain of the AGC circuit 7 is set to 5: 1 when large: small.
When the loop gain of the AGC circuit 7 is increased with respect to a signal without ghost interference, the detection time of the segment synchronization signal 20 is 0.35 seconds (average value measured 20 times, the same applies hereinafter), and the loop gain of the AGC circuit 7 Is small, the detection time of the segment synchronizing signal 20 is 0.31 second, and there is almost no difference. On the other hand, for a signal having a ghost disturbance of 1 μsec and D / U = 6 dB, when the loop gain of the AGC circuit 7 is increased, the detection time of the segment synchronization signal 20 is 4.5 seconds, and the loop gain of the AGC circuit is reduced. The detection time of the segment synchronization signal 20 is 6.5 seconds when the length is reduced, and the detection time of the segment synchronization signal 20 is shorter when the loop gain is increased. When the loop gain of the AGC circuit 7 is fixed at a large value, the ghost elimination performance of the ghost interference 1 μsec is D / U = 13 dB, but before and after the detection of the segment synchronization signal 20. When the loop gain of the AGC circuit 7 is switched from a large value to a small value, the ghost interference 1 μsec removal performance is D / U = 8 dB. Note that D represents a desired wave (Disere) and U represents an interference wave (Undesire), and the smaller the D / U, the higher the level of ghost interference.

As described above, according to the VSB receiver according to the first embodiment of the present invention, the loop filter is broadened so that the detection time is short until the segment synchronization signal 20 is detected. After detecting 20, the loop filter is switched to a narrow band to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
It is a block diagram which shows the structure of the digital demodulation part 2 in the VSB receiver which concerns on embodiment. In FIG. 6, the digital demodulation unit 2 according to the second embodiment includes a VSB detector 3
, An AD converter 4, a segment synchronization detection circuit 28,
A gain detector 25, an amplifier 26, a DA converter 29,
It includes resistors 35 to 37, capacitors 38 and 39, a switch diode 40, and a clock recovery circuit 6.

As shown in FIG. 6, in the digital demodulation unit 2 of the second embodiment, the synchronization detection circuit 5 shown in FIG. , DA converter 29 and resistor 3
5 to 37, a capacitor 38, 39, and a switch diode 40. In FIG. 6, portions having the same configuration as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, each configuration of the digital demodulation unit 2 of the second embodiment will be described in order.

The DA converter 29 receives the amplified digital decision signal output from the amplifier 26, converts the signal into an analog decision signal, and outputs the signal. The output signal of the DA converter 29 is input to one terminal of the resistor 35 of the discrete circuit. The other terminal of the resistor 35 is connected to one terminal of the resistor 36 and is fed back to the VSB detector 3. The other terminal of resistor 36 is connected to one terminal of capacitors 38 and 39, respectively.
The other terminal of the capacitor 38 is connected to a switch diode 40
And one terminal of the resistor 37.
The other terminal of the capacitor 39 and the switch diode 4
The 0 cathode terminals are each grounded. A segment synchronization detection signal 30 output from the segment synchronization detection circuit 28 is input to the other terminal of the resistor 37.

First, until the segment synchronization signal 20 is detected, the switch 40 is turned off because the segment synchronization detection signal 30 is "L". Therefore,
In this case, the discrete circuit functions as a wide band loop filter including the resistors 35 and 36 and the capacitor 39. Next, after the segment synchronization signal 20 is detected, the segment synchronization detection signal 30 becomes “H”, so that the switch diode 40 is turned on. Therefore,
In this case, the discrete circuit functions as a narrow band loop filter including the resistors 35 and 36 and the capacitors 38 and 39.

Therefore, when the segment synchronizing signal 20 is not detected, the AGC voltage 8 fed back from the other terminal of the resistor 35 to the VSB detector 3 becomes the AGC voltage 8 that has passed through the wide band loop filter. When the signal 20 is detected, the AGC voltage 8 that has passed through the narrow band loop filter is selectively switched according to the segment synchronization detection signal 30 and output.

As described above, according to the VSB receiver according to the second embodiment of the present invention, the loop filter is broadened so that the detection time is short until the segment synchronization signal 20 is detected. After detecting 20, the loop filter is switched to a narrow band to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
It is a block diagram which shows the structure of the digital demodulation part 2 in the VSB receiver which concerns on embodiment. In FIG. 7, the digital demodulation unit 2 according to the third embodiment includes a VSB detector 3
, An AD converter 4, a segment synchronization detection circuit 28,
It includes a gain detector 25, an amplifier 26, a digital filter 42, a switching circuit 34, a wideband coefficient 43, a narrowband coefficient 44, a DA converter 29, and a clock recovery circuit 6.

As shown in FIG. 7, in the digital demodulation unit 2 of the third embodiment, the synchronization detection circuit 5 shown in FIG. , Digital filter 42, switching circuit 34, broadband coefficient 43, narrowband coefficient 44
And a DA converter 29. In FIG. 7, parts having the same configurations as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted.
Hereinafter, each configuration of the digital demodulation unit 2 of the third embodiment will be described in order.

The amplified digital decision signal output from the amplifier 26 is filtered by the digital filter 42, converted into the analog AGC voltage 8 by the DA converter 29, and fed back to the VSB detector 3. The broadband coefficient 43 includes a digital filter 42
The filter coefficients necessary to make the function of the... Function in a wide band are stored. The narrow-band coefficient 44 stores a filter coefficient necessary for the digital filter 42 to function in a narrow band. Then, the switching circuit 34
According to the segment synchronization detection signal 30, if the segment synchronization detection signal 30 is "L" (the segment synchronization signal 20 is not detected), the wideband coefficient 43
Is written into the digital filter 42, and the segment synchronization detection signal 30 is "H" (the segment synchronization signal 20
Is detected), the narrow-band coefficient 44 is written to the digital filter 42.

Therefore, when the segment sync signal 20 is not detected, the digital filter 42 functions as a wide band loop filter,
When 0 is detected, the AGC voltage 8 fed back to the VSB detector 3 is selectively switched in band according to the segment synchronization detection signal 30 and output as it functions as a narrow band loop filter.

As described above, according to the VSB receiver according to the third embodiment of the present invention, the loop filter is broadened so that the detection time is shortened until the segment synchronization signal 20 is detected. After detecting 20, the loop filter is switched to a narrow band to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
It is a block diagram which shows the structure of the digital demodulation part 2 in the VSB receiver which concerns on embodiment. In FIG. 8, the digital demodulation unit 2 of the fourth embodiment includes a VSB detector 3
, An AD converter 4, a segment synchronization detection circuit 28,
It includes a gain detector 25, an amplifier (high gain) 52, an amplifier (low gain) 53, a switching circuit 34, a loop filter 54, and a clock recovery circuit 6.

As shown in FIG. 8, in the digital demodulation unit 2 of the fourth embodiment, the synchronization detection circuit 5 in FIG. 1 is constituted by a segment synchronization detection circuit 28, the AGC circuit 7 is a gain detector 25, High gain) 52, Amplifier (low gain)
53, a switching circuit 34 and a loop filter 54. In FIG. 8, FIGS.
Portions having the same configuration as those described above are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, each configuration of the digital demodulation unit 2 of the fourth embodiment will be described in order.

The judgment signal output from the gain detector 25 is input to an amplifier (high gain) 52 and an amplifier (low gain) 53, respectively. The amplifier (high gain) 52 is configured so that the loop gain in the AGC circuit 7 is large (the tracking performance of the AGC is good), that is, the reduction of the detection time of the segment synchronization signal 20 is prioritized over the ghost interference removal performance. An amplification gain value has been set. On the other hand, the amplifier (small gain) 53 makes the loop gain in the AGC circuit 7 small (the AGC tracking performance is poor), that is, gives priority to the ghost interference removal performance over the shortening of the detection time of the segment synchronization signal 20. In addition, an amplification gain value is set. As described above, the determination signal output from the gain detector 25 includes the amplifier (high gain) 52 and the amplifier (low gain) 53
, And then input to the switching circuit 34.

The switching circuit 34 includes an amplifier (high gain) 5
2 and the signal amplified by the amplifier (small gain) 53 and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28 are input. Then, the switching circuit 34
According to the segment synchronization detection signal 30, if the segment synchronization detection signal 30 is "L" (the segment synchronization signal 20 is not detected), the amplifier (large gain)
The signal amplified at 52 is converted to a segment synchronization detection signal 30.
Is "H" (the segment synchronization signal 20 is detected), the signal amplified by the amplifier (small gain) 53 is selectively switched and output. The signal selectively output from the switching circuit 34 is supplied to the loop filter 5.
4, the signal is fed back to the VSB detector 3 as an AGC voltage 8.

As described above, according to the VSB receiver according to the fourth embodiment of the present invention, the amplification gain is set to a large value so as to shorten the detection time until the segment synchronization signal 20 is detected. After detecting the signal 20, the amplification gain is switched to a small value to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Fifth Embodiment) FIG. 9 shows a fifth embodiment of the present invention.
It is a block diagram which shows the structure of the digital demodulation part 2 in the VSB receiver which concerns on embodiment. In FIG. 9, the digital demodulation unit 2 according to the fifth embodiment includes a VSB detector 3
, An AD converter 4, a segment synchronization detection circuit 28,
It includes a gain detector 25, a DA converter 29, an operational amplifier (high gain) 55, an operational amplifier (low gain) 56, a switching circuit 34, a loop filter 54, and a clock recovery circuit 6.

As shown in FIG. 9, in the digital demodulation unit 2 of the fifth embodiment, the synchronization detection circuit 5 shown in FIG. Device 29, operational amplifier (high gain) 5
5, an operational amplifier (small gain) 56, a switching circuit 34, and a loop filter 54. In FIG. 9, portions having the same configuration as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted.
Hereinafter, each configuration of the digital demodulation unit 2 of the fifth embodiment will be described in order.

The DA converter 29 receives the digital decision signal output from the gain detector 25, converts the signal into an analog decision signal, and outputs the signal. The analog determination signal is supplied to an operational amplifier (high gain) 55 and an operational amplifier (low gain) 5
6, respectively. Operational amplifier (large gain) 55
Means that the loop gain in the AGC circuit 7 is large (AGC
, The amplification gain value is set such that the reduction of the detection time of the segment synchronization signal 20 is prioritized over the ghost interference removal performance. on the other hand,
The operational amplifier (small gain) 56 is configured so that the loop gain in the AGC circuit 7 is small (the AGC tracking performance is poor), that is, the ghost interference removal performance is prioritized over the shortening of the detection time of the segment synchronization signal 20. An amplification gain value has been set. As described above, the analog determination signal output from the DA converter 29 is output from the operational amplifier (high gain) 5.
After being amplified by the operational amplifier 5 and the operational amplifier (small gain) 56, they are input to the switching circuit 34.

The switching circuit 34 receives the signals amplified by the operational amplifier (large gain) 55 and the operational amplifier (small gain) 56 and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28. Then, according to the segment synchronization detection signal 30, when the segment synchronization detection signal 30 is “L” (the segment synchronization signal 20 is not detected), the switching circuit 34 is amplified by the operational amplifier (high gain) 55. The signal is such that the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20
Is detected), the signal amplified by the operational amplifier (small gain) 56 is selectively switched and output. The signal selectively output from the switching circuit 34 is
After passing through the loop filter 54, the AGC voltage 8 becomes V
The signal is fed back to the SB detector 3.

As described above, according to the VSB receiver according to the fifth embodiment of the present invention, the amplification gain is set to a large value so as to shorten the detection time until the segment synchronization signal 20 is detected. After detecting the signal 20, the amplification gain is switched to a small value to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Sixth Embodiment) FIG. 10 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a sixth embodiment of the present invention. In FIG. 10, the digital demodulation unit 2 of the sixth embodiment includes a VSB detector 3, an AD converter 4, and a segment synchronization detection circuit 2.
8, a gain detector 25, a multiplier 57, and a large coefficient 58
, Small coefficient 59, switching circuit 34, DA converter 2
9, a loop filter 54, and a clock recovery circuit 6.

As shown in FIG. 10, in the digital demodulation unit 2 of the sixth embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the AGC circuit 7 is a gain detector 25 and a multiplier. 57, large coefficient 58, small coefficient 5
9, a switching circuit 34, a DA converter 29 and a loop filter 54. In FIG. 10, parts having the same configuration as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, each configuration of the digital demodulation unit 2 of the sixth embodiment will be described in order.

The digital decision signal output from the gain detector 25 is amplified by the multiplier 57 and
After being converted into an analog AGC voltage 8 at 9, it is fed back to the VSB detector 3. The large coefficient 58 stores a coefficient necessary for increasing the amplification gain of the multiplier 57. The coefficient 59 stores a coefficient necessary for reducing the amplification gain of the multiplier 57.
Then, the switching circuit 34 inputs the large coefficient 58 to the multiplier 57 according to the segment synchronization detection signal 30 when the segment synchronization detection signal 30 is “L” (the segment synchronization signal 20 is not detected). , When the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20 is detected), the small coefficient 59 is multiplied by the multiplier 57.
To enter.

Therefore, the multiplier 57 functions as a high-gain amplifier when the segment synchronization signal 20 is not detected, and functions as a low-gain amplifier when the segment synchronization signal 20 is detected. VSB detector 3
The AGC voltage 8 fed back to is output with its gain value selectively switched according to the segment synchronization detection signal 30.

As described above, according to the VSB receiver according to the sixth embodiment of the present invention, the amplification gain is set to a large value so as to shorten the detection time until the segment synchronization signal 20 is detected. After detecting the signal 20, the amplification gain is switched to a small value to improve the ghost removal performance, and the loop gain of the AGC circuit 7 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.

(Seventh Embodiment) In the first to sixth embodiments, by switching the loop gain of the AGC circuit 7, the detection time of the segment synchronizing signal 20 is shortened, and ghost elimination against ghost interference is performed. A VSB receiver that also improves performance has been described. Next, in the following embodiment, by also switching the loop gain of the clock recovery circuit 6, the detection time of the segment synchronization signal 20 can be further shortened, and accurate clock recovery can be performed even when ghost disturbance occurs. The VSB receiver will be described.

FIG. 11 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a seventh embodiment of the present invention. In FIG. 11, the digital demodulation unit 2 of the seventh embodiment includes a VSB detector 3, an AD converter 4, a segment synchronization detection circuit 28, a clock frequency detector 60, an amplifier 61, and a broadband loop filter 6
2, a narrow band loop filter 63, and a switching circuit 64
, A variable clock oscillator 65, and an AGC circuit 7.

As shown in FIG. 11, in the digital demodulation unit 2 of the seventh embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60, It comprises an amplifier 61, a wide band loop filter 62, a narrow band loop filter 63, a switching circuit 64 and a variable clock oscillator 65. In FIG. 11, parts having the same configurations as those in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof will be omitted. The configuration of any of the first to sixth embodiments is used for the AGC circuit 7 in FIG. Hereinafter, each configuration of the digital demodulation unit 2 of the seventh embodiment will be described in order.

The digital data (FIG. 2) output from the AD converter 4 is input to the waveform equalizer 10 and the segment synchronization detection circuit 28. Segment synchronization detection circuit 28
Performs segment synchronization detection on input digital data, and outputs the detected segment synchronization signal 20 to the clock frequency detector 60 and the segment synchronization detection signal 30 for determining whether or not it has been detected to the switching circuit 64. . Since the segment synchronization detection method performed by the segment synchronization detection circuit 28 has been described in the first embodiment, a detailed description thereof will be omitted.

The clock frequency detector 60 determines whether the frequency of the clock signal 9 of the VSB receiver is higher or lower than the clock frequency of the transmitted data, and outputs the determination signal to the amplifier 61. Here, the method of determining the clock frequency performed by the clock frequency detector 60 will be described with further reference to FIG. FIG. 12 is a diagram illustrating the concept of a method of determining the clock frequency performed by the clock frequency detector 60.

As a premise, since the signal input to the AD converter 4 is band-limited, the actual segment synchronization signal 20 has four symbols as shown in FIG.
Instead of a rectangular wave of "-5, -5, +5", the waveform is as shown in FIG. First, when the clock signal 9 of the VSB receiver is higher than the clock frequency of the transmission data (FIG. 12).
(A)), when the AD converter 4 converts the symbol data “−5, −5” of the segment synchronization signal 20 at the rising timing of the clock signal 9 of the VSB receiver,
These are converted into digital data of d1 and d2 (d1> d2), respectively. Conversely, when the clock signal 9 of the VSB receiver is lower than the clock frequency of the transmission data (FIG. 12).
(B)) When the AD converter 4 converts the symbol data “−5, −5” of the segment synchronization signal 20 at the rising timing of the clock signal 9 of the VSB receiver,
They are converted into digital data of d1 and d2 (d1 <d2), respectively.

The clock frequency detector 60 determines the difference between the two data (d1> d2 or d1 <d2) and eliminates the difference between the two data at the output of the AD converter 4 (d1 = d2). 9 is output from the variable clock oscillator 65. By this processing, when the clock signal 9 of the VSB receiver matches the clock frequency of the transmission data (FIG. 12).
(C)), when the AD converter 4 converts the symbol data of “−5, −5” of the segment synchronization signal 20 at the rising timing of the clock signal 9 of the VSB receiver, d1 and d2 ( It is controlled so that it is converted into digital data of (d1 = d2). Amplifier 6
Reference numeral 1 inputs the determination signal output from the clock frequency detector 60, performs predetermined amplification, and outputs the amplified signal to the wide band loop filter 62 and the narrow band loop filter 63.

The wide-band loop filter 62 is designed so that the loop gain in the clock recovery circuit 6 is large (the followability of clock recovery is good), that is, the detection time of the segment synchronizing signal 20 can be shortened accurately. For example, a filter coefficient is set that gives priority to ghost interference removal performance). On the other hand, the narrow band loop filter 63 controls the segment recovery signal 20 so that the loop gain in the clock recovery circuit 6 is small (the followability of clock recovery is poor), that is, the clock recovery is accurate.
, A filter coefficient is set that gives priority to shortening the detection time. Then, the amplified determination signal output from the amplifier 61 passes through the wide band loop filter 62 and the narrow band loop filter 63, and is then input to the switching circuit 64.

The switching circuit 64 receives the signals passed through the wide band loop filter 62 and the narrow band loop filter 63 and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28. When the segment synchronization detection signal 30 is “L” (the segment synchronization signal 20 is not detected), the switching circuit 64 converts the signal passed through the wideband loop filter 62 according to the segment synchronization detection signal 30. When the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20 is detected), the signal (DC voltage) that has passed through the narrow band loop filter 63 is selectively switched and output to the variable clock oscillator 65. I do. The variable clock oscillator 65 changes the frequency of the clock signal 9 oscillating based on the signal (DC voltage) output from the switching circuit 64 and feeds back to the AD converter 4.

As described above, according to the VSB receiver according to the seventh embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. As described above, after detecting the segment synchronization signal 20, the loop filter is switched to a narrow band in order to perform accurate clock recovery (that is, to improve ghost removal performance). Control. This allows
Even if the received signal has ghost interference, the detection time of the segment synchronization signal 20 can be shortened, the ghost removal performance against ghost interference can be improved, and no jitter occurs in the reproduced clock of the VSB receiver. Therefore, no error occurs in the received signal.

(Eighth Embodiment) FIG. 13 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to an eighth embodiment of the present invention. In FIG. 13, the digital demodulation unit 2 of the eighth embodiment includes a VSB detector 3, an AD converter 4, a segment synchronization detection circuit 2
8, clock frequency detector 60, amplifier 61, D
A converter 69, resistors 75 to 77, capacitor 78,
79, a switch diode 80, a variable clock oscillator 65, and an AGC circuit 7.

As shown in FIG. 13, in the digital demodulation unit 2 of the eighth embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60, It comprises a discrete circuit including an amplifier 61, a DA converter 69, resistors 75 to 77, capacitors 78 and 79, and a switch diode 80, and a variable clock oscillator 65. In addition,
13, parts having the same configuration as those in FIGS. 1, 4, and 11 are denoted by the same reference numerals, and description thereof will be omitted. The AGC circuit 7 in FIG.
Any one of the configurations of the first to sixth embodiments is used. Hereinafter, each configuration of the digital demodulation unit 2 of the eighth embodiment will be described in order.

The DA converter 69 receives the amplified digital decision signal output from the amplifier 61, converts the signal into an analog decision signal, and outputs the signal. The output signal of the DA converter 69 is input to one terminal of a resistor 75 of a discrete circuit. The other terminal of the resistor 75 is connected to one terminal of the resistor 76 and is output to the variable clock oscillator 65. The other terminal of resistor 76 is connected to one terminal of capacitors 78 and 79, respectively. The other terminal of the capacitor 78 is connected to the anode terminal of the switch diode 80 and one terminal of the resistor 77. The other terminal of the capacitor 79 and the cathode terminal of the switch diode 80 are grounded. The segment synchronization detection signal 30 output from the segment synchronization detection circuit 28 is input to the other terminal of the resistor 77.

First, until the segment synchronization signal 20 is detected, the switch diode 80 is turned off since the segment synchronization detection signal 30 is "L". Therefore,
In this case, the discrete circuit functions as a wide band loop filter including the resistors 75 and 76 and the capacitor 79. Next, after the segment synchronization signal 20 is detected, the segment synchronization detection signal 30 becomes “H”, so that the switch diode 80 is turned on. Therefore,
In this case, the discrete circuit functions as a narrow-band loop filter including the resistors 75 and 76 and the capacitors 78 and 79.

Therefore, the clock signal 9 fed back from the other terminal of the resistor 75 to the VSB detector 3 via the variable clock oscillator 65 has passed through the wide band loop filter when the segment synchronization signal 20 has not been detected. When the segment synchronization signal 20 is detected, the decision signal that has passed through the narrow band loop filter is selectively switched according to the segment synchronization detection signal 30 and output.

Here, the results of specific experiments will be described.
The value of each element is 18 kΩ for the resistor 35, 1 kΩ for the resistor 36, 1 μF for the capacitor 38, and 3.3 μF for the capacitor 39. Without switching the loop filter before and after the detection of the segment synchronization signal 20, the resistors 75, 7
6 and the capacitor 79 alone, the detection time of the segment synchronization signal 20 is 1.05 seconds (average value measured 20 times, the same applies hereinafter), and the bandwidth of the loop filter before and after the detection of the segment synchronization signal 20 The detection time of the segment synchronization signal 20 when the switching was performed was 0.36 seconds. In addition, when the loop of the clock recovery circuit 6 is fixed in a wide band (that is, when only the loop gain of the AGC circuit 7 is switched), the performance of the ghost interference elimination of 1 μsec is D / Although U = 8 dB, when the band of the loop filter of the clock recovery circuit 6 is switched from a wide band to a narrow band before and after the detection of the segment synchronization signal 20, the ghost elimination performance of the ghost disturbance of 1 μsec becomes D / U = It is further improved to 6 dB.

As described above, according to the VSB receiver according to the eighth embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. As described above, after detecting the segment synchronization signal 20, the loop filter is switched to a narrow band in order to perform accurate clock recovery (that is, to improve ghost removal performance). Control. This allows
Even if the received signal has ghost interference, the detection time of the segment synchronization signal 20 can be shortened, the ghost removal performance against ghost interference can be improved, and no jitter occurs in the reproduced clock of the VSB receiver. Therefore, no error occurs in the received signal.

(Ninth Embodiment) FIG. 14 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a ninth embodiment of the present invention. In FIG. 14, the digital demodulation unit 2 of the ninth embodiment includes a VSB detector 3, an AD converter 4, a segment synchronization detection circuit 2
8, a clock frequency detector 60, an amplifier 61, a digital filter 82, a switching circuit 64, a wide band coefficient 83, a narrow band coefficient 84, and a DA converter 69.
, A variable clock oscillator 65, and an AGC circuit 7.

As shown in FIG. 14, in the digital demodulation unit 2 of the ninth embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60. Amplifier 61, digital filter 82, switching circuit 64, wideband coefficient 8
3, a narrow band coefficient 84, a DA converter 69, and a variable clock oscillator 65. Note that, in FIG. 14, portions having the same configuration as in FIGS. 1, 4, and 11 are denoted by the same reference numerals, and description thereof will be omitted. The AGC circuit 7 shown in FIG.
Any of the configurations of the sixth to sixth embodiments is used. Hereinafter, each configuration of the digital demodulation unit 2 of the ninth embodiment will be described in order.

The amplified digital decision signal output from the amplifier 61 is filtered by a digital filter 82, converted into an analog signal (DC voltage) by a DA converter 69, and then passed through a variable clock oscillator 65. 9 is fed back to the VSB detector 3. The wide band coefficient 83 includes a digital filter 8
The filter coefficients required to make 2 function in a wide band are stored. The narrow-band coefficient 84 stores a filter coefficient necessary for the digital filter 82 to function in a narrow band. Then, the switching circuit 64
According to the segment synchronization detection signal 30, if the segment synchronization detection signal 30 is "L" (the segment synchronization signal 20 is not detected), the wideband coefficient 83
Is written into the digital filter 82, and the segment synchronization detection signal 30 is "H" (the segment synchronization signal 20
Is detected), the narrow-band coefficient 84 is written to the digital filter 82.

Therefore, when the segment sync signal 20 is not detected, the digital filter 82 functions as a wide band loop filter, and
When “0” is detected, the clock signal 9 fed back to the VSB detector 3 is selectively switched in band according to the segment synchronization detection signal 30 and output as it functions as a narrow band loop filter.

As described above, according to the VSB receiver according to the ninth embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. As described above, after detecting the segment synchronization signal 20, the loop filter is switched to a narrow band in order to perform accurate clock recovery (that is, to improve ghost removal performance). Control. This allows
Even if the received signal has ghost interference, the detection time of the segment synchronization signal 20 can be shortened, the ghost removal performance against ghost interference can be improved, and no jitter occurs in the reproduced clock of the VSB receiver. Therefore, no error occurs in the received signal.

(Tenth Embodiment) FIG. 15 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a tenth embodiment of the present invention. In FIG. 15, the digital demodulation unit 2 according to the tenth embodiment includes a VS
B detector 3, AD converter 4, segment synchronization detection circuit 28, clock frequency detector 60, amplifier (high gain) 92, amplifier (small gain) 93, switching circuit 6
4, the loop filter 94, and the variable clock oscillator 65
And an AGC circuit 7.

As shown in FIG. 15, in the digital demodulation unit 2 of the tenth embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60, Amplifier (high gain) 9
2. It comprises an amplifier (small gain) 93, a switching circuit 64, a loop filter 94 and a variable clock oscillator 65. Note that, in FIG. 15, portions having the same configuration as those in FIGS. 1, 4, and 11 are denoted by the same reference numerals, and description thereof will be omitted. The configuration of any of the first to sixth embodiments is used for the AGC circuit 7 in FIG. Hereinafter, each configuration of the digital demodulation unit 2 of the tenth embodiment will be described in order.

The determination signal output from the clock frequency detector 60 includes an amplifier (high gain) 92 and an amplifier (low gain)
93 respectively. The amplifier (high gain) 92
The loop gain in the clock recovery circuit 6 is increased (the follow-up of the clock recovery is improved), that is, the shortening of the detection time of the segment synchronizing signal 20 can be shortened by more accurate clock recovery (in other words, ghost interference removal performance). The priority gain gain value is set. On the other hand, the amplifier (small gain) 93 reduces the loop gain in the clock recovery circuit 6 (poor in clock recovery), that is, performs accurate clock recovery more than shortening the detection time of the segment synchronization signal 20. The priority gain gain value is set. As described above, the determination signal output from the clock frequency detector 60 is amplified by the amplifier (high gain) 92 and the amplifier (low gain) 93, respectively, and then input to the switching circuit 64.

The switching circuit 64 includes an amplifier (high gain) 9
2 and the signal amplified by the amplifier (small gain) 93 and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28 are input. Then, the switching circuit 64
According to the segment synchronization detection signal 30, if the segment synchronization detection signal 30 is "L" (the segment synchronization signal 20 is not detected), the amplifier (large gain)
The signal amplified at 92 is converted to a segment synchronization detection signal 30.
Is "H" (the segment synchronization signal 20 is detected), the signal amplified by the amplifier (small gain) 93 is selectively switched and output. The signal (DC voltage) selectively output from the switching circuit 64 is fed back to the VSB detector 3 as the clock signal 9 after passing through the loop filter 94 and the variable clock oscillator 65.

As described above, according to the VSB receiver according to the tenth embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. To increase the amplification gain
After detecting the segment synchronizing signal 20, the amplification gain is switched to a small value and the loop gain of the clock recovery circuit 6 is controlled in order to perform accurate clock recovery (that is, to improve ghost removal performance). As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.
Further, since no jitter occurs in the reproduced clock of the VSB receiver, no error occurs in the received signal.

(Eleventh Embodiment) FIG. 16 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to an eleventh embodiment of the present invention. In FIG. 16, the digital demodulation unit 2 of the eleventh embodiment has a VS
B detector 3, AD converter 4, segment synchronization detection circuit 28, clock frequency detector 60, DA converter 6
9, an operational amplifier (high gain) 95, an operational amplifier (low gain) 96, a switching circuit 64, a loop filter 94
, A variable clock oscillator 65, and an AGC circuit 7.

As shown in FIG. 16, in the digital demodulation unit 2 of the eleventh embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60, DA converter 69, operational amplifier (high gain) 95, operational amplifier (low gain) 96,
It comprises a switching circuit 64, a loop filter 94 and a variable clock oscillator 65. Note that, in FIG. 16, portions having the same configuration as those in FIGS. 1, 4, and 11 are denoted by the same reference numerals, and description thereof will be omitted. The AGC circuit 7 shown in FIG.
Any of the configurations of the sixth to sixth embodiments is used. Hereinafter, each configuration of the digital demodulation unit 2 of the eleventh embodiment will be described in order.

The DA converter 69 receives the digital decision signal output from the clock frequency detector 60, converts it into an analog decision signal, and outputs it. The analog determination signal is input to an operational amplifier (high gain) 95 and an operational amplifier (low gain) 96, respectively. The operational amplifier (high gain) 95 is designed so that the loop gain in the clock recovery circuit 6 is large (the followability of clock recovery is good).
That is, the amplification gain value is set such that the shortening of the detection time of the segment synchronization signal 20 is prioritized over the accurate clock reproduction (in other words, the ghost interference removal performance).
On the other hand, the operational amplifier (small gain) 96 makes the loop gain in the clock recovery circuit 6 small (the follow-up performance of the clock recovery is poor), that is, the accurate clock recovery is performed more than the reduction of the detection time of the segment synchronization signal 20. The priority gain gain value is set. Thus, DA
The analog determination signal output from the converter 69 is amplified by an operational amplifier (high gain) 95 and an operational amplifier (low gain) 96, respectively, and then input to the switching circuit 64.

The switching circuit 64 receives the signals amplified by the operational amplifier (high gain) 95 and the operational amplifier (low gain) 96, respectively, and the segment synchronization detection signal 30 from the segment synchronization detection circuit 28. Then, according to the segment synchronization detection signal 30, when the segment synchronization detection signal 30 is “L” (the segment synchronization signal 20 is not detected), the switching circuit 64 is amplified by the operational amplifier (high gain) 95. The signal is set such that the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20
Is detected), the signal amplified by the operational amplifier (small gain) 96 is selectively switched and output. The signal selectively output from the switching circuit 64 is
After passing through the loop filter 94 and the variable clock oscillator 65, it is fed back to the VSB detector 3 as the clock signal 9.

As described above, according to the VSB receiver according to the eleventh embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. To increase the amplification gain
After detecting the segment synchronizing signal 20, the amplification gain is switched to a small value and the loop gain of the clock recovery circuit 6 is controlled in order to perform accurate clock recovery (that is, to improve ghost removal performance). As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.
Further, since no jitter occurs in the reproduced clock of the VSB receiver, no error occurs in the received signal.

(Twelfth Embodiment) FIG. 17 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a twelfth embodiment of the present invention. In FIG. 17, the digital demodulation unit 2 of the twelfth embodiment has
B detector 3, AD converter 4, segment synchronization detection circuit 28, clock frequency detector 60, multiplier 97
Large coefficient 98, small coefficient 99, switching circuit 64
, A DA converter 69, a loop filter 94, a variable clock oscillator 65, and an AGC circuit 7.

As shown in FIG. 17, in the digital demodulation unit 2 of the twelfth embodiment, the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28, and the clock recovery circuit 6 is a clock frequency detector 60. Multiplier 97, large coefficient 98, small coefficient 99, switching circuit 64, DA converter 6
9. Loop filter 94 and variable clock oscillator 65
It consists of. In FIG. 17, portions having the same configurations as those in FIGS. 1, 4, and 11 are denoted by the same reference numerals, and description thereof will be omitted. FIG.
For the AGC circuit 7 in 7, the configuration of any of the first to sixth embodiments is used. Hereinafter, each configuration of the digital demodulation unit 2 of the twelfth embodiment will be described in order.

The digital decision signal output from the clock frequency detector 60 is amplified in the multiplier 97 and
After being converted into an analog DC voltage by the A converter 69, it is fed back to the VSB detector 3 via the loop filter 94 and the variable clock oscillator 65. Large coefficient 98
Stores a coefficient necessary for increasing the amplification gain of the multiplier 97. The coefficient small 99 stores a coefficient necessary for reducing the amplification gain of the multiplier 97. Then, the switching circuit 64 generates the segment synchronization detection signal 30 according to the segment synchronization detection signal 30.
Is "L" (the segment synchronization signal 20 is not detected), the large coefficient 98 is input to the multiplier 97,
When the segment synchronization detection signal 30 is “H” (the segment synchronization signal 20 has been detected), the small coefficient 99 is input to the multiplier 97.

Therefore, the multiplier 97 functions as a high gain amplifier when the segment synchronization signal 20 is not detected, and functions as a low gain amplifier when the segment synchronization signal 20 is detected. VSB detector 3
The clock signal 9 fed back to is output with its amplification value selectively switched according to the segment synchronization detection signal 30.

As described above, according to the VSB receiver according to the twelfth embodiment of the present invention, in addition to controlling the loop gain of the AGC circuit 7, the detection time is shortened until the segment synchronization signal 20 is detected. To increase the amplification gain
After detecting the segment synchronizing signal 20, the amplification gain is switched to a small value and the loop gain of the clock recovery circuit 6 is controlled in order to perform accurate clock recovery (that is, to improve ghost removal performance). As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and to improve ghost removal performance against ghost interference.
Further, since no jitter occurs in the reproduced clock of the VSB receiver, no error occurs in the received signal.

(Thirteenth Embodiment) In the first to twelfth embodiments, the AGC circuit 7 and the clock recovery circuit are used by using the segment synchronization signal 20 and the segment synchronization detection signal 30 obtained by performing the segment synchronization detection. Circuit 6
Was switched. Next, the thirteenth
In the embodiment, a VSB receiver that switches the loop gain of the AGC circuit 7 and the clock recovery circuit 6 by using the field synchronization signals 21 and 22 and the field synchronization detection signal 101 obtained by performing the field synchronization detection will be described.

FIG. 18 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a thirteenth embodiment of the present invention. In FIG. 18, the digital demodulation unit 2 of the thirteenth embodiment includes a VSB detector 3, an AD converter 4, a segment synchronization detection circuit 28, a field synchronization detection circuit 100, a clock recovery circuit 6, an AGC
And a circuit 7.

As shown in FIG. 18, the digital demodulation unit 2 of the thirteenth embodiment is such that the synchronization detection circuit 5 in FIG. 1 is composed of a segment synchronization detection circuit 28 and a field synchronization detection circuit 100. In FIG. 18, portions having the same configuration as in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The AGC circuit 7 in FIG. 18 uses the configuration of any of the first to sixth embodiments, and the clock recovery circuit 6 includes the configuration of any of the seventh to twelfth embodiments. Is used. Hereinafter, each configuration of the digital demodulation unit 2 of the thirteenth embodiment will be described in order.

The digital data (FIG. 2) output from the AD converter 4 is input to the waveform equalizer 10 and the segment synchronization detection circuit 28. Segment synchronization detection circuit 28
Performs segment synchronization detection on input digital data, and outputs the detected segment synchronization signal 20 to the field synchronization detection circuit 100. Since the segment synchronization detection method performed by the segment synchronization detection circuit 28 has been described in the first embodiment, a detailed description thereof will be omitted.

The field synchronization detection circuit 100 performs field synchronization detection based on the input segment synchronization signal 20, and outputs the detected field synchronization signals 21, 22 and the field synchronization detection signal 101 to the clock recovery circuit 6.
And AGC circuit 7 respectively. Here, the field synchronization detection method performed by the field synchronization detection circuit 100 will be described with further reference to FIG. FIG. 19 is a flowchart illustrating a procedure of the field synchronization detection performed by the field synchronization detection circuit 100.

[0162] As shown in FIG.
Since it is known in advance what kind of data will be sent as 1 and 22, the segment synchronization detection circuit 28 detects the segment synchronization signal 20 of the transmission data, whereby the beginning of each segment can be known. Therefore, the field synchronization detection circuit 100 detects the field synchronization signals 21 and 22 based on the detected position of the segment synchronization signal 20 as follows. First,
When the field synchronization detection circuit 100 starts the field synchronization detection operation, it initializes the field synchronization detection signal 101 to a low level “L” (Step S201). Next, the field synchronization detection circuit 100 calculates, for one field (313 segments), the sum (error amount) of the error between the data of 832 symbols of each segment and the specific pattern of the field synchronization signals 21 and 22 for each segment. (Step S202). Then, the field synchronization detection circuit 100 sets the A-th segment having the smallest error amount in one field as a field synchronization candidate (step S203). Next, the field synchronization detection circuit 100 calculates the segment having the smallest error amount for each field, and determines the number of times that the calculated segment becomes the A-th segment continuously (step S20).
4). In the determination in step S204, the number of segments calculated for each field is B times (B is the number of times the field synchronization pattern is detected to determine the detection of the field synchronization signal and is arbitrarily determined in advance). In the event that the field synchronization detection circuit 100
The A-th segment is determined as the field synchronization signals 21 and 22, and the process proceeds to step S206. On the other hand, step S2
If the segment calculated for each field does not become the A-th segment consecutively B times in the judgment of 04, the field synchronization detecting circuit 100 proceeds to step S20.
Returning to step 1, the process of confirming the field synchronization detection is performed again.

Further, the field synchronization detecting circuit 100
Indicates that, after the field synchronization signal detection is determined, the determined field synchronization signal 2
It is determined whether or not the error amount of the segment 313 segments away from the segments 1 and 22 is minimum (step S206). Then, in the determination of step S206, when the error amount of the segment separated by 313 segments is not the minimum, the field synchronization detection circuit 100 increases the value of the field synchronization pattern non-detection number C initialized in step S205 by one ( Step S207). The procedure of steps S206 to S207 is repeated, and C =
D (D is the number of undetected field synchronization patterns at which field synchronization signal undetection is determined and is arbitrarily determined in advance), the field synchronization detection circuit 10
If it is 0, it is determined that the field synchronization detection has transitioned to undetermined, and the process returns to step S201 to perform the processing for field synchronization detection determination again (step S208).

By the above processing, the field synchronization detection circuit 1
00, the field synchronization signals 21 and 22 detected
Is the field synchronization detection signal 101 instead of the segment synchronization signal 20 and the segment synchronization detection signal 30
Are output to the AGC circuit 7 and the clock recovery circuit 6 described in the first to twelfth embodiments, respectively. The AGC circuit 7 and the clock recovery circuit 6 respectively configure large and small loop gains based on the field synchronization signals 21 and 22 as described above, and appropriately switch between large and small loop gains according to the field synchronization detection signal 101.

As described above, according to the VSB receiver according to the thirteenth embodiment of the present invention, the field synchronization signal 2
The band or the amplification value is increased to a large value so that the detection time is shortened until the detection of the field synchronization signal 2 is completed.
After the detection of the AGC and the AGC, the band or the amplification value is switched to a small value to improve the ghost removal performance.
The loop gain of the circuit 7 and the clock recovery circuit 6 is controlled. As a result, even when the received signal has ghost interference, it is possible to shorten the detection time of the segment synchronization signal 20 and the field synchronization signals 21 and 22 and to improve the ghost removal performance against the ghost interference, and further, it is possible to improve the VSB. Since no jitter occurs in the reproduction clock of the receiver, no error occurs in the received signal.

In the thirteenth embodiment, the AGC circuit 7 and the clock recovery circuit 6 use the field synchronization signals 21 and 22 and the field synchronization detection signal 101.
Is described as controlling both loop gains,
The loop gain of only the C circuit 7 may be controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a VSB receiver according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a transmission format of an 8-level VSB modulation signal.

FIG. 3 is a diagram showing a data configuration of a segment synchronization signal 20 and field synchronization signals 21 and 22 of FIG.

FIG. 4 is a block diagram illustrating a configuration of a digital demodulation unit 2 in the VSB receiver according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating a procedure of segment synchronization detection performed by a segment synchronization detection circuit 28 of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a seventh embodiment of the present invention.

12 is a diagram illustrating the concept of a method of determining a clock frequency performed by a clock frequency detector 60 in FIG. 11;

FIG. 13 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to an eighth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a ninth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to a tenth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a digital demodulation unit 2 in a VSB receiver according to an eleventh embodiment of the present invention.

FIG. 17 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a twelfth embodiment of the present invention.

FIG. 18 is a block diagram illustrating a configuration of a digital demodulation unit 2 in a VSB receiver according to a thirteenth embodiment of the present invention.

FIG. 19 is a flowchart illustrating a procedure of field synchronization detection performed by the field synchronization detection circuit 100 of FIG. 18;

FIG. 20 is a block diagram illustrating an example of a configuration of a conventional VSB receiver.

21 is a block diagram illustrating an example of a detailed configuration of a waveform equalizer 203 in FIG.

FIG. 22 is a diagram illustrating a problem that occurs in a conventional VSB receiver.

[Explanation of symbols]

1,201 Tuner 2,202 Digital demodulator 3, VSB detector 4, AD converter 5, Synchronous detection circuit 6, Clock recovery circuit 7, AGC circuit 8, AGC voltage 9, Clock signal 10, 203, Waveform, etc. , Error correction circuit 12, transport stream 13, 205, transport decoder 14, video data 15, audio data 16, 206, video decoder 17, 207, audio decoder 18, video signal 19, audio signal 20 ... Segment synchronization signal 21,22 ... Field synchronization signal 25 ... Gain detector 26,52,53,61,92,93 ... Amplifier 28 ... Segment synchronization detection circuit 29,69 ... DA converter 30 ... Segment synchronization detection signal 32, 33, 54, 62, 63, 94 ... Loop filter 34, 64 ... Off Replacement circuit 35-37, 75-77 Resistance 38, 39, 78, 79 Capacitor 40, 80 Switch diode 42, 82 Digital filter 43, 44, 58, 59, 83, 84, 98, 99 Coefficient 55 , 56, 95, 96 ... operational amplifiers 57, 97 ... multipliers 60 ... clock frequency detectors 65 ... variable clock oscillators 100 ... field synchronization detection circuits 101 ... field synchronization detection signals

Claims (52)

[Claims] The video and audio data in a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field are modulated by multi-level VSB (8-level or 16-level VSB) modulation. A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being applied, wherein: a segment synchronization detecting means for detecting the segment synchronization signal from the received signal subjected to the multi-level VSB modulation; Automatic gain control means for performing feedback control of a loop gain via a gain detector, an amplifier, and a loop filter so that the level of the segment synchronization signal is constant based on the segment synchronization signal detected by the segment synchronization detection means. The automatic gain control means notifies the presence or absence of the detection of the segment synchronization signal. According to the segment sync detection signal,
The VSB receiver controls the loop filter to have a wide band until the segment synchronization signal is detected, and controls the loop filter to have a narrow band after detection. 2. The loop filter according to claim 1, wherein the loop filter is a wide-band loop filter and a narrow-band loop filter each including a resistor and a capacitor. The VSB receiver according to claim 1, wherein a bandwidth of the loop filter is controlled by switching a value of a determined time constant by a switching process. 3. The loop filter is a digital filter capable of varying a bandwidth according to a separately given filter coefficient, and the automatic gain control means switches a filter coefficient to be given to the digital filter according to the segment synchronization detection signal. The VSB receiver according to claim 1, wherein a bandwidth of the loop filter is controlled. 4. A video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is subjected to multi-level VSB (8-level or 16-level VSB) modulation. A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being applied, wherein: a segment synchronization detecting means for detecting the segment synchronization signal from the received signal subjected to the multi-level VSB modulation; Automatic gain control means for performing feedback control of a loop gain via a gain detector, an amplifier, and a loop filter so that the level of the segment synchronization signal is constant based on the segment synchronization signal detected by the segment synchronization detection means. The automatic gain control means notifies the presence or absence of the detection of the segment synchronization signal. According to the segment sync detection signal,
A VSB receiver, wherein the gain of the amplifier is controlled to be large until the segment synchronization signal is detected, and the gain of the amplifier is controlled to be small after detection. 5. The amplifier according to claim 1, wherein the amplifier is composed of an operational amplifier having a large gain and an operational amplifier having a small gain. The automatic gain control means switches the operational amplifier to one of the operational amplifiers in accordance with the segment synchronization detection signal. The VSB receiver according to claim 4, wherein the VSB receiver controls the gain of the amplifier. 6. The amplifier is a multiplier that can vary an amplification value according to a separately given coefficient. The automatic gain control means switches a coefficient to be given to the multiplier according to the segment synchronization detection signal, 5. The VSB receiver according to claim 4, wherein the VSB receiver controls an amplifier gain. 7. A video and audio data having a format having a segment synchronization signal at the beginning of each segment and a field synchronization signal at the beginning of each field is subjected to multi-level VSB (8-level or 16-level VSB) modulation. A VSB receiver for receiving a terrestrial digital broadcast signal transmitted after being applied, wherein: a segment synchronization detecting means for detecting the segment synchronization signal from the received signal subjected to the multi-level VSB modulation; Automatic gain control means for performing feedback control of a loop gain via a gain detector, an amplifier, and a loop filter so that the level of the segment synchronization signal is constant based on the segment synchronization signal detected by the segment synchronization detection means. Playback based on the segment synchronization signal detected by the segment synchronization detection means. Clock recovery means for feedback-controlling the loop gain via a clock frequency detector, an amplifier, a loop filter, and a variable clock oscillator so that the clock frequency to be matched with the clock frequency of the received signal, the automatic gain control means And the clock recovery means comprises:
According to a segment synchronization detection signal that notifies the presence or absence of the detection of the segment synchronization signal, the loop filter is controlled to a wide band until the segment synchronization signal is detected, and the loop filter is controlled to a narrow band after the detection. A VSB receiver, characterized by: 8. The automatic gain control means and the clock recovery means, wherein the loop filters of the automatic gain control means and the clock recovery means are a wide-band loop filter and a narrow-band loop filter, both comprising a resistor and a capacitor. The reproduction means
8. The VSB according to claim 7, wherein a bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to the segment synchronization detection signal. Receiving machine. 9. The automatic gain control means and the loop filter of the clock recovery means are digital filters each of which can vary a bandwidth according to a separately provided filter coefficient. The automatic gain control means and the clock recovery means
8. The VSB receiver according to claim 7, wherein a bandwidth of each of the loop filters is controlled by switching a filter coefficient applied to the digital filter according to the segment synchronization detection signal. 10. The loop filter of the automatic gain control means includes a wide-band loop filter and a narrow-band loop filter including a resistor and a capacitor,
The loop filter of the clock recovery means is a digital filter capable of varying a bandwidth according to a separately provided filter coefficient, and the automatic gain control means has a time constant determined by the resistor and the capacitor according to the segment synchronization detection signal. The clock recovery means controls the bandwidth of the loop filter by switching the filter coefficient applied to the digital filter in accordance with the segment synchronization detection signal. The VSB receiver according to claim 7. 11. The loop filter of the automatic gain control means is a digital filter whose bandwidth can be varied according to a separately given filter coefficient, and the loop filter of the clock recovery means has a wide band composed of a resistor and a capacitor. The automatic gain control means switches a filter coefficient to be applied to the digital filter according to the segment synchronization detection signal, so that the clock regenerating means according to the segment synchronization detection signal. 8. The VSB receiver according to claim 7, wherein a bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process. 12. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having A segment synchronization detection unit for detecting the segment synchronization signal from the signal subjected to the multi-level VSB modulation; and a level of the segment synchronization signal based on the segment synchronization signal detected by the segment synchronization detection unit. Automatic gain control means for feedback-controlling the loop gain through a gain detector, an amplifier, and a loop filter; and a clock frequency to be reproduced based on the segment synchronization signal detected by the segment synchronization detection means. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means and said clock reproducing means,
The gain of the amplifier is controlled to be large until the segment synchronization signal is detected, and the gain of the amplifier is controlled to be small after the detection, in accordance with a segment synchronization detection signal indicating whether or not the segment synchronization signal is detected. VSB receiver. 13. The amplifier of the automatic gain control means and the amplifier of the clock recovery means are both composed of a large gain operational amplifier and a small gain operational amplifier. The automatic gain control means and the clock recovery means ,
13. The VSB receiver according to claim 12, wherein the gain of each of the operational amplifiers is controlled by switching the operational amplifier to one of the operational amplifiers according to the segment synchronization detection signal. 14. The automatic gain control unit and the amplifier of the clock recovery unit are multipliers each of which can vary an amplification value according to a separately provided coefficient. The automatic gain control unit and the clock recovery unit each include:
The V gain according to claim 12, wherein a gain given to each of the amplifiers is controlled by switching a coefficient given to the multiplier according to the segment synchronization detection signal.
SB receiver. 15. The amplifier of the automatic gain control means is constituted by two operational amplifiers having a large gain and a small gain. The amplifier of the clock recovery means has an amplification value according to a coefficient given separately. A variable multiplier, wherein the automatic gain control means switches the operational amplifier to one of them according to the segment synchronization detection signal, and the clock recovery means provides the multiplier to the multiplier according to the segment synchronization detection signal. 13. The VSB receiver according to claim 12, wherein gains of the amplifiers are controlled by switching coefficients. 16. The amplifier of the automatic gain control means is a multiplier capable of changing an amplification value according to a separately given coefficient, and the amplifier of the clock recovery means is composed of a high gain operational amplifier and a small gain operational amplifier. The automatic gain control means switches a coefficient to be applied to the multiplier according to the segment synchronization detection signal, so that the clock regenerating means controls any one of the operational amplifiers according to the segment synchronization detection signal. 13. The VSB receiver according to claim 12, wherein the gain is controlled by switching to one of the amplifiers. 17. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having A segment synchronization detection unit for detecting the segment synchronization signal from the signal subjected to the multi-level VSB modulation; and a level of the segment synchronization signal based on the segment synchronization signal detected by the segment synchronization detection unit. Automatic gain control means for feedback-controlling the loop gain through a gain detector, an amplifier, and a loop filter; and a clock frequency to be reproduced based on the segment synchronization signal detected by the segment synchronization detection means. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means in accordance with the segment synchronization detection signal indicating the presence or absence of detection of said segment sync signal,
Until the segment synchronization signal is detected, the loop filter is controlled in a wide band, and after the detection, the loop filter is controlled in a narrow band. A VSB receiver, wherein the gain of the amplifier is controlled to be large until the signal is detected, and the gain of the amplifier is controlled to be small after the signal is detected. 18. The loop filter of the automatic gain control means is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor,
The amplifier of the clock recovery means is composed of two of a high gain operational amplifier and a small gain operational amplifier, and the automatic gain control means is configured to determine when the resistor and the capacitor are determined according to the segment synchronization detection signal. By switching the value of the constant by a switching process, the bandwidth of the loop filter is controlled, and the clock recovery unit switches the operational amplifier to one of them according to the segment synchronization detection signal, thereby increasing the gain of the amplifier. 18. The VSB receiver according to claim 17, wherein the VSB receiver controls. 19. The automatic gain control means includes a loop filter having a wide band and a loop filter having a narrow band, each of which includes a resistor and a capacitor.
The amplifier of the clock recovery unit is a multiplier that can vary an amplification value according to a separately given coefficient, and the automatic gain control unit is a time constant value determined by the resistor and the capacitor according to the segment synchronization detection signal. Controlling the bandwidth of the loop filter by switching processing, and the clock recovery unit controls the gain of the amplifier by switching a coefficient applied to the multiplier according to the segment synchronization detection signal. 2. The method according to claim 1, wherein
8. The VSB receiver according to 7. 20. The loop filter of the automatic gain control means is a digital filter whose bandwidth can be varied according to a separately provided filter coefficient, and the amplifier of the clock recovery means has a large gain operational amplifier and a small gain operational amplifier. The automatic gain control means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter in accordance with the segment synchronization detection signal, and the clock recovery means The VSB receiver according to claim 17, wherein the gain of the amplifier is controlled by switching the operational amplifier to one of the operational amplifiers according to the segment synchronization detection signal. 21. The loop filter of the automatic gain control means is a digital filter capable of varying a bandwidth according to a separately provided filter coefficient, and the amplifier of the clock recovery means varies an amplification value according to a separately provided coefficient. The automatic gain control means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter according to the segment synchronization detection signal, and the clock recovery means 18. The VSB receiver according to claim 17, wherein the gain of said amplifier is controlled by switching a coefficient applied to said multiplier according to a synchronization detection signal. 22. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having A segment synchronization detection unit for detecting the segment synchronization signal from the signal subjected to the multi-level VSB modulation; and a level of the segment synchronization signal based on the segment synchronization signal detected by the segment synchronization detection unit. Automatic gain control means for feedback-controlling the loop gain through a gain detector, an amplifier, and a loop filter; and a clock frequency to be reproduced based on the segment synchronization signal detected by the segment synchronization detection means. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means in accordance with the segment synchronization detection signal indicating the presence or absence of detection of said segment sync signal,
The gain of the amplifier is controlled to be large until the segment synchronization signal is detected, and the gain of the amplifier is controlled to be small after the detection. The clock recovery means detects the segment synchronization signal in accordance with the segment synchronization detection signal. The VSB receiver controls the loop filter to a wide band until the detection is performed, and controls the loop filter to a narrow band after the detection. 23. The automatic gain control means includes an amplifier having a large gain and an operational amplifier having a small gain. The loop filter of the clock recovery means includes a resistor and a capacitor. A wide-band loop filter and a narrow-band loop filter, wherein the automatic gain control means controls the gain of the amplifier by switching the operational amplifier to one of them according to the segment synchronization detection signal, and 23.Controlling the bandwidth of the loop filter by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to the segment synchronization detection signal, wherein the bandwidth of the loop filter is controlled. VSB receiver. 24. The automatic gain control means comprises an amplifier having a large gain and an operational amplifier having a small gain. The loop filter of the clock recovery means has a band according to a filter coefficient provided separately. A digital filter having a variable width, wherein the automatic gain control means controls the gain of the amplifier by switching the operational amplifier to one of the operational amplifiers in accordance with the segment synchronization detection signal; and 23. The VSB receiver according to claim 22, wherein a bandwidth of the loop filter is controlled by switching a filter coefficient applied to the digital filter according to a synchronization detection signal. 25. The amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately given coefficient, and the loop filter of the clock recovery means is a wideband loop composed of a resistor and a capacitor. A filter and a narrow-band loop filter, wherein the automatic gain control means controls a gain of the amplifier by switching a coefficient applied to the multiplier according to the segment synchronization detection signal, and the clock recovery means includes 23. The VSB receiver according to claim 22, wherein a bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to a segment synchronization detection signal. . 26. The amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately provided coefficient, and the loop filter of the clock recovery means is capable of varying a bandwidth according to a separately provided filter coefficient. A digital filter capable of controlling the gain of the amplifier by switching a coefficient applied to the multiplier in accordance with the segment synchronization detection signal. 23. The VSB receiver according to claim 22, wherein the bandwidth of the loop filter is controlled by switching a filter coefficient applied to the digital filter according to the following. 27. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter, wherein the automatic gain control means includes a field synchronization detection signal for notifying the presence or absence of detection of the field synchronization signal. According to
The VSB receiver controls the loop filter to a wide band until the field synchronization signal is detected, and controls the loop filter to a narrow band after the field synchronization signal is detected. 28. The loop filter is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor, and the automatic gain controller is configured to control the automatic gain control by the resistor and the capacitor according to the field synchronization detection signal. 28. The VSB receiver according to claim 27, wherein the bandwidth of the loop filter is controlled by switching a value of a determined time constant by a switching process. 29. The loop filter is a digital filter capable of varying a bandwidth according to a separately given filter coefficient, and the automatic gain control means switches a filter coefficient to be given to the digital filter according to the field synchronization detection signal. 28. The VSB according to claim 27, wherein a bandwidth of the loop filter is controlled.
Receiving machine. 30. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter, wherein the automatic gain control means includes a field synchronization detection signal for notifying the presence or absence of detection of the field synchronization signal. According to
A VSB receiver, wherein the gain of the amplifier is controlled to be large until the field synchronization signal is detected, and the gain of the amplifier is controlled to be small after detection. 31. The amplifier comprises two high-gain operational amplifiers and a small-gain operational amplifier, and the automatic gain control means switches the operational amplifier to one of them according to the field synchronization detection signal. The VSB receiver according to claim 30, wherein the VSB receiver controls the gain of the amplifier. 32. The amplifier, wherein the amplifier is a multiplier capable of varying an amplification value according to a separately given coefficient, wherein the automatic gain control means switches a coefficient to be given to the multiplier according to the field synchronization detection signal, The VSB receiver according to claim 30, wherein the gain of the amplifier is controlled. 33. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter; and, based on the field synchronization signal detected by the field synchronization detection means, a clock frequency to be reproduced is a reception signal. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means and said clock reproducing means,
According to a field synchronization detection signal that notifies the presence or absence of the detection of the field synchronization signal, the loop filter is controlled to a wide band until the field synchronization signal is detected, and the loop filter is controlled to a narrow band after the detection. A VSB receiver, characterized by: 34. The automatic gain control means and the clock recovery means, wherein the loop filters of the clock recovery means are a wideband loop filter and a narrowband loop filter, both comprising a resistor and a capacitor. The reproduction means
The VSB according to claim 33, wherein a bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to the field synchronization detection signal. Receiving machine. 35. The automatic gain control means and the loop filter of the clock recovery means are digital filters each of which can vary a bandwidth according to a separately provided filter coefficient. The automatic gain control means and the clock recovery means,
34. The VSB receiver according to claim 33, wherein a bandwidth of each of the loop filters is controlled by switching a filter coefficient applied to the digital filter according to the field synchronization detection signal. 36. The loop filter of the automatic gain control means includes a wide-band loop filter and a narrow-band loop filter including a resistor and a capacitor,
The loop filter of the clock recovery means is a digital filter capable of varying a bandwidth according to a separately provided filter coefficient, and the automatic gain control means has a time constant determined by the resistor and the capacitor according to the field synchronization detection signal. The clock recovery means controls the bandwidth of the loop filter by switching the filter coefficient given to the digital filter according to the field synchronization detection signal by switching the value of the loop filter by the switching process. The VSB receiver according to claim 33. 37. The loop filter of the automatic gain control means is a digital filter whose bandwidth can be varied according to a separately given filter coefficient, and the loop filter of the clock recovery means has a wide band composed of a resistor and a capacitor. Wherein the automatic gain control means switches a filter coefficient to be applied to the digital filter according to the field synchronization detection signal, so that the clock recovery means according to the field synchronization detection signal 34. The VSB receiver according to claim 33, wherein the bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process. 38. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter; and, based on the field synchronization signal detected by the field synchronization detection means, a clock frequency to be reproduced is a reception signal. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means and said clock reproducing means,
The gain of the amplifier is controlled to be large until the field synchronization signal is detected, and the gain of the amplifier is controlled to be small after the detection, in accordance with a field synchronization detection signal indicating whether or not the field synchronization signal is detected. VSB receiver. 39. The automatic gain control means and the amplifier of the clock recovery means are both composed of a large gain operational amplifier and a small gain operational amplifier. The automatic gain control means and the clock recovery means ,
39. The VSB receiver according to claim 38, wherein the gain of each of the operational amplifiers is controlled by switching the operational amplifier to one of the operational amplifiers according to the field synchronization detection signal. 40. The automatic gain control means and the amplifier of the clock recovery means are multipliers each of which can vary an amplification value according to a separately provided coefficient. The automatic gain control means and the clock recovery means
39. The V of claim 38, wherein the gain of each of the amplifiers is controlled by switching a coefficient applied to the multiplier in accordance with the field synchronization detection signal.
SB receiver. 41. The amplifier of the automatic gain control means is composed of two of a large gain operational amplifier and a small gain operational amplifier, and the amplifier of the clock recovery means adjusts an amplification value according to a coefficient given separately. A variable multiplier, wherein the automatic gain control means switches the operational amplifier to one of them according to the field synchronization detection signal, and the clock recovery means provides the multiplier to the multiplier according to the field synchronization detection signal. The VSB receiver according to claim 38, wherein the gain of each of the amplifiers is controlled by switching a coefficient. 42. The amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately given coefficient, and the amplifier of the clock recovery means is composed of a high gain operational amplifier and a small gain operational amplifier. The automatic gain control means switches the coefficient to be applied to the multiplier according to the field synchronization detection signal, so that the clock recovery means controls the operational amplifier according to the field synchronization detection signal. 39. The VSB receiver according to claim 38, wherein the gain is controlled by switching to one of the amplifiers. 43. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter; and, based on the field synchronization signal detected by the field synchronization detection means, a clock frequency to be reproduced is a reception signal. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means in accordance with the field synchronization detection signal indicating the presence or absence of detection of the field sync signal,
Until the field synchronization signal is detected, the loop filter is controlled to have a wide band, and after the detection, the loop filter is controlled to have a narrow band. A VSB receiver, wherein the gain of the amplifier is controlled to be large until the signal is detected, and the gain of the amplifier is controlled to be small after the signal is detected. 44. The loop filter of the automatic gain control means is a wide-band loop filter and a narrow-band loop filter composed of a resistor and a capacitor,
The amplifier of the clock recovery means is constituted by two of a high gain operational amplifier and a small gain operational amplifier, and the automatic gain control means is provided when the automatic gain control means is determined by the resistor and the capacitor according to the field synchronization detection signal. By switching the value of the constant by a switching process, the bandwidth of the loop filter is controlled, and the clock recovery unit switches the operational amplifier to one of the operational amplifiers according to the field synchronization detection signal, thereby increasing the gain of the amplifier. The VSB receiver according to claim 43, wherein the VSB receiver is controlled. 45. The loop filter of the automatic gain control means includes a wide-band loop filter and a narrow-band loop filter including a resistor and a capacitor,
The amplifier of the clock recovery unit is a multiplier that can vary an amplification value according to a separately given coefficient, and the automatic gain control unit is a time constant value determined by the resistor and the capacitor according to the field synchronization detection signal. Controlling the bandwidth of the loop filter by switching processing, and controlling the gain of the amplifier by switching the coefficient applied to the multiplier in accordance with the field synchronization detection signal. 5. The method according to claim 4, wherein
4. The VSB receiver according to 3. 46. The loop filter of the automatic gain control means is a digital filter whose bandwidth can be varied according to a separately provided filter coefficient, and the amplifier of the clock recovery means has a large gain operational amplifier and a small gain operational amplifier. The automatic gain control means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter in accordance with the field synchronization detection signal, and the clock recovery means 44. The VSB receiver according to claim 43, wherein the gain of the amplifier is controlled by switching the operational amplifier to one of the operational amplifiers according to the field synchronization detection signal. 47. The loop filter of the automatic gain control means is a digital filter capable of varying a bandwidth according to a separately provided filter coefficient, and the amplifier of the clock recovery means varies an amplification value according to a separately provided coefficient. The automatic gain control means controls the bandwidth of the loop filter by switching a filter coefficient applied to the digital filter in accordance with the field synchronization detection signal, and The VSB receiver according to claim 43, wherein the gain of the amplifier is controlled by switching a coefficient applied to the multiplier according to a synchronization detection signal. 48. A segment synchronization signal at the beginning of each segment, a field synchronization signal at the beginning of each field,
A VSB receiver for receiving a terrestrial digital broadcast signal transmitted by applying multi-level VSB (8-level or 16-level VSB) modulation to video and audio data in a format having Field synchronization detecting means for detecting the field synchronization signal from the signal subjected to multi-level VSB modulation, and the level of the field synchronization signal is constant based on the field synchronization signal detected by the field synchronization detection means. Automatic gain control means for feedback-controlling the loop gain via a gain detector, an amplifier, and a loop filter; and, based on the field synchronization signal detected by the field synchronization detection means, a clock frequency to be reproduced is a reception signal. Clock frequency detector, amplifier and loop to match the clock frequency of And a clock reproducing means for feedback control of the loop gain through a filter and a variable clock oscillator, said automatic gain control means in accordance with the field synchronization detection signal indicating the presence or absence of detection of the field sync signal,
The gain of the amplifier is controlled to be large until the field synchronization signal is detected, and the gain of the amplifier is controlled to be small after the detection. The clock recovery means detects the field synchronization signal in accordance with the field synchronization detection signal. The VSB receiver controls the loop filter to a wide band until the detection is performed, and controls the loop filter to a narrow band after the detection. 49. The amplifier of the automatic gain control means includes two operational amplifiers having a large gain and a small gain, and the loop filter of the clock recovery means includes a resistor and a capacitor. A wide-band loop filter and a narrow-band loop filter, wherein the automatic gain control means controls the gain of the amplifier by switching the operational amplifier to one of them according to the field synchronization detection signal, and 49. The method according to claim 48, wherein the bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to the field synchronization detection signal. VSB receiver. 50. The automatic gain control means comprises two amplifiers, a large gain operational amplifier and a small gain operational amplifier, wherein the loop filter of the clock recovery means has a band width in accordance with a separately provided filter coefficient. A digital filter having a variable width, wherein the automatic gain control means controls the gain of the amplifier by switching the operational amplifier to one of the operational amplifiers in accordance with the field synchronization detection signal; and 49. The VSB receiver according to claim 48, wherein a bandwidth of the loop filter is controlled by switching a filter coefficient applied to the digital filter according to a synchronization detection signal. 51. The amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately given coefficient, and the loop filter of the clock recovery means is a wideband loop composed of a resistor and a capacitor. A filter and a narrow-band loop filter, wherein the automatic gain control means controls a gain of the amplifier by switching a coefficient applied to the multiplier according to the field synchronization detection signal, and the clock recovery means includes 49. The VSB receiver according to claim 48, wherein the bandwidth of the loop filter is controlled by switching a value of a time constant determined by the resistor and the capacitor by a switching process according to a field synchronization detection signal. . 52. The amplifier of the automatic gain control means is a multiplier capable of varying an amplification value according to a separately provided coefficient, and the loop filter of the clock recovery means is capable of varying a bandwidth according to a separately provided filter coefficient. A digital filter capable of controlling the gain of the amplifier by switching a coefficient applied to the multiplier in accordance with the field synchronization detection signal. 49. The VSB receiver according to claim 48, wherein a bandwidth of said loop filter is controlled by switching a filter coefficient given to said digital filter according to: