JP2000174016A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance and reliability of a wiring layer, which includes a barrier metal film. SOLUTION: This method includes a step of forming grooves on an insulating film 10 composed of a silicon oxide film and the like on a semiconductor substrate (substrate) 1, a step forming a barrier metal film 12 on sides and bottoms of the grooves and a surface of the insulating film 10, a step of reducing a thickness of the barrier metal film 12 on the surface of the insulating film 10 other than on or around the grooves, and a step of after a wiring metallic layer 13 is stacked on the semiconductor substrate 1, removing the barrier metal film 10 and a wiring metallic layer 13 on the insulating film 10 by CMP (chemomechanical polishing) method so as to form a wiring layer, which is composed of the wiring metallic layer 13 and the barrier metal films 12 burried in the grooves.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device capable of improving the performance and reliability of a wiring layer having a barrier metal film and manufacturing the same. It is about the method.

[0002]

2. Description of the Related Art The present inventors have studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a wiring layer in a semiconductor integrated circuit device, a groove is formed in an insulating film such as an interlayer insulating film made of a silicon oxide film or the like, and a barrier metal film made of a tantalum (Ta) film or the like is formed in the groove. And copper (Cu)
In some cases, a wiring layer (a wiring layer including a mode of a wiring layer called a damascene wiring layer) including a wiring metal layer including a layer is formed.

In this case, a barrier metal film made of a tantalum film or the like and a wiring metal layer made of a copper layer or the like formed on the surface thereof are formed by a CMP (chemical mechanical polishing).
g, chemical mechanical polishing) using a CMP method
A manufacturing process is used in which a wiring metal layer in an unnecessary region and a barrier metal film on the back surface thereof are polished to form a patterned wiring layer as a damascene wiring layer.

As a document describing a CMP apparatus and a CMP processing technology, for example, “Electronic Materials May 1996” issued by the Industrial Research Council on May 1, 1996.
There are those described on pages 28 to 32.

[0006]

However, in the above-described method for manufacturing a semiconductor integrated circuit device, there is a problem that when a damascene wiring layer is formed, a step occurs in an insulating film adjacent to the damascene wiring layer. Have been found by the present inventors.

As a result, the step of the interlayer insulating film adjacent to the damascene wiring layer cannot be eliminated, so that when the damascene wiring layer is formed, an electrical short circuit or the like due to the unpolished residue of the wiring metal layer such as a copper layer is caused. There is a problem that a defective phenomenon occurs.

In this case, as a result of the study by the present inventors, CMP
When a barrier metal film made of a tantalum film or the like is polished by using a CMP method using an apparatus, the polishing speed of the barrier metal film is lower than the polishing speed of a copper layer as a wiring metal layer. Tend to be.

Therefore, in order to completely polish a barrier metal film such as a tantalum film formed on the surface of the insulating film in a region other than the groove for the damascene wiring layer, if the amount of over-polishing is increased, the polishing speed is increased. Excessive polishing of the copper layer causes dishing in the grooves for the damascene wiring layer and erosion that simultaneously polishes the insulating film such as the silicon oxide film around the wiring layer. Was revealed.

An object of the present invention is to provide a semiconductor integrated circuit device capable of improving the performance and reliability of a wiring layer having a barrier metal film and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1). In the semiconductor integrated circuit device of the present invention, a groove is formed in an insulating film such as a silicon oxide film on a substrate such as a semiconductor substrate, and a wiring comprising a barrier metal film and a wiring metal layer embedded in the groove. The surface of the wiring layer is 0.05 μm from the same plane or the same plane as the surface of the insulating film other than the groove.
Within.

(2). The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a groove in an insulating film made of a silicon oxide film or the like on a substrate made of a semiconductor substrate or the like; A step of forming a metal film, a step of reducing the thickness of a barrier metal film on the surface of the insulating film in a region other than the groove or the vicinity of the groove, and a step of depositing a wiring metal layer on the substrate, and then performing a CMP method. Use,
Removing the barrier metal film and the wiring metal layer on the insulating film, and forming a wiring layer composed of the barrier metal film and the wiring metal layer embedded in the trench.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIGS. 1 to 6 are schematic sectional views showing a manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention. A feature of the method for manufacturing a semiconductor integrated circuit device of the present embodiment is a method for manufacturing a wiring layer including a barrier metal film and a wiring metal layer embedded in a groove formed in an insulating film on a substrate, Various other aspects can be applied to a method of manufacturing a semiconductor integrated circuit device other than the above. The semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 1, a p-type semiconductor substrate (substrate) 1 made of, for example, single crystal silicon is prepared.
Various techniques, such as the prior art, are used to form MOSFETs.

That is, for example, a selective region on the surface of a p-type semiconductor substrate 1 made of single-crystal silicon is thermally oxidized to form a field insulating film for element isolation made of a silicon oxide film having a LOCOS (Local Oxidation of Silicon) structure. Form 2

Next, after forming a gate insulating film 3 made of, for example, a silicon oxide film on the surface of the semiconductor substrate 1, a gate electrode 4 made of a conductive polycrystalline silicon film is deposited. Thereafter, an insulating film 5 made of a silicon oxide film or the like is formed on the gate electrode 4, and a pattern such as the gate electrode 4 is formed using a lithography technique and a selective etching technique. Next, a sidewall spacer 6 made of a silicon oxide film or the like is formed.

Thereafter, for example, phosphorus (P) is formed on the semiconductor substrate 1.
Ion implantation of n-type impurities such as
An n-type semiconductor region 7 serving as a source and a drain of the FET is formed. Next, an insulating film 8 is formed on the semiconductor substrate 1. The insulating film 8 is, for example, a silicon oxide film formed by CVD.
(Chemical Vapor Deposition)
By polishing the surface and flattening the surface,
A flattened insulating film 8 is formed. In the planarization process, the surface of the insulating film 8 is formed by, for example, an etch-back method or a CMP (chem.
It is possible to adopt a mode of flattening by ical mechanical polishing, chemical mechanical polishing) or the like. afterwards,
Using lithography technology and selective etching technology,
After forming a through hole (connection hole) in a selective region of the insulating film 8, a conductive material such as conductive polycrystalline silicon or tungsten is buried in the through hole, and a plug 9 is formed in the through hole.

Next, after forming an insulating film 10 as a first-layer interlayer insulating film on the semiconductor substrate 1, a trench 11 for a wiring layer is formed therein (FIG. 2). That is, on the semiconductor substrate 1, for example, a silicon oxide film is
After forming using the VD method, using lithography technology and selective etching technology such as dry etching,
A groove 11 is formed in a portion where a wiring layer is to be arranged.

In this case, the insulating film 10 is formed of a silicon oxide film having a small dielectric constant (dielectric constant) in order to reduce the capacitance of the wiring layer formed in the trench 11 and the wiring layer in which the insulating film 10 is interposed. Is about 4.2) or inorganic SOG
(Spin on glass) coating insulation film (dielectric constant about 4
The following insulating film) is used. Also, the groove 11
Is 250 nm, for example, and the thickness (depth) of the groove 11 is
Is 400 nm, for example.

Thereafter, a barrier metal film 12 made of tantalum is deposited on the semiconductor substrate 1 by using a sputtering method or a CVD method (FIG. 3). In this case, groove 1
The thickness of the barrier metal film 12 made of tantalum formed on the surface of the insulating film 10 in a region other than 1 is, for example, 100 nm.
The film thickness is as follows.

Next, the barrier metal film 12 at the bottom of the groove 11 is formed.
A step of reducing the thickness of the barrier metal film 12 on the surface of the insulating film 10 in a region other than the groove 11 is performed without reducing the thickness of the substrate (FIG. 4).

In this case, in the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the process using the CMP method is performed, and the thickness of the barrier metal film 12 on the surface of the insulating film 10 in the region other than the trench 11 is set to 10 nm. The following is a feature of this embodiment.

In this step, since the CMP method is used, the overhang barrier metal film 12 formed (formed) at the corner of the groove 11 is tapered at the same time as this step. Forming (applying).

Thereafter, a wiring metal layer 13 made of a copper layer having a thickness of, for example, 400 nm or more is deposited on the semiconductor substrate 1 by using a sputtering method, a CVD method, or a plating method. The work of embedding the metal layer 13 for use is performed (FIG. 5). In this case, in order to completely embed the wiring metal layer 13 as a wiring layer in the groove 11, the thickness of the groove 11 (for example, 4
00 nm) (for example, 600 nm).

Next, the wiring metal layer 13 is polished from the surface of the wiring metal layer 13 by using the CMP method.
Work of polishing the barrier metal film 12 on the surface of the insulating film 10 other than the region shown in FIG. 2 and removing the wiring metal layer 13 and the wiring metal layer 13 and the barrier metal film 12 other than the barrier metal film 12 buried in the groove 11. (FIG. 6). In this case, the surface of the wiring metal layer 13 buried in the groove 11 becomes the same plane (the same plane) as the surface of the insulating film 10, and the barrier metal film 12 made of tantalum on the insulating film 10 is removed. . In addition, as a result of the study of the present invention, the groove 1
The surface of the wiring metal layer 13 buried in 1 is within 0.05 μm (an extremely short distance level) from the same plane as the surface of the insulating film 10, and the barrier metal film 12 of tantalum on the insulating film 10 is formed. Is removed.

Thereafter, according to the design specifications, the insulating film 10 as the first interlayer insulating film, the barrier metal film 12 as the first wiring layer, and the wiring metal layer 13 according to the design specifications.
Is applied on the semiconductor substrate 1 by applying a manufacturing method for forming
After depositing the second interlayer insulating film, a groove for forming a second wiring layer is formed in a selective area thereof, and a barrier metal film and a wiring as a second wiring layer are formed in the groove. A metal layer for use. After the above-described manufacturing process is repeatedly used to form a multilayer wiring layer as necessary, a passivation film (not shown) is formed, and the manufacturing process of the semiconductor integrated circuit device of the present embodiment is completed. .

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment described above, the thickness of the barrier metal film 12 at the bottom of the wiring layer groove 11 can be reduced without insulating the region other than the groove 11. After performing the step of reducing the thickness of the barrier metal film 12 on the surface of the film 10, the wiring metal layer 13 is polished from the surface of the wiring metal layer 13 using a CMP method,
Next, the barrier metal film 12 on the surface of the insulating film 10 other than the region of the groove 11 is polished, and the wiring metal layer 13 and the wiring metal layer 13 other than the barrier metal film 12 and the barrier metal film embedded in the groove 11 are polished. In the state where the thickness of the barrier metal film 12 on the surface of the insulating film 10 in the region other than the groove 11 is reduced by performing the operation of removing the CM 12, the CM
Using the P method, the wiring metal layer 1 other than the wiring metal layer 13 and the barrier metal film 12 embedded in the trench 11
3 and the barrier metal film 12 are removed.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the groove 1 is formed by using the CMP method.
When the wiring metal layer 13 and the barrier metal film 12 other than the wiring metal layer 13 and the barrier metal film 12 embedded in the wiring layer 1 are removed, dishing in the wiring layer groove 11 and insulating film around the wiring layer are performed. Erosion of simultaneously polishing 10 can be reduced. Moreover, as a result of the study by the present inventors, when the barrier metal film 12 other than the barrier metal film 12 buried in the trench 11 is removed, the thickness is set to 10 nm or less, so that dishing and erosion are extremely reduced. It has been found that dishing and erosion can be prevented depending on the design specifications.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the thickness of the barrier metal film 12 at the bottom of the trench 11 for the wiring layer is not reduced, and the insulating film 10 in a region other than the trench 11 is formed. As a step of reducing the thickness of the barrier metal film 12 on the surface of the insulating film 10 in a region other than the groove 11, the barrier metal film 1 is formed using a CMP method.
2 has a thickness of 10 nm or less.
The taper is formed (applied) on the overhang-shaped barrier metal film 12 formed (formed) at the corner portion of the groove 11, thereby forming a film at the corner portion of the wiring layer groove 11. Since the shape of the formed overhang-shaped barrier metal film 12 can be improved, the buried shape of the wiring metal layer 13 can be improved, and a high-performance and highly reliable wiring layer can be formed.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, erosion, in which dishing in the wiring layer groove 11 and polishing of the insulating film 10 around the wiring layer at the same time, is reduced. Since the taper is formed (applied) on the overhang-shaped barrier metal film 12 formed (formed) at the corner of the groove 11, the wiring metal layer 13 is buried. Can form a high-performance and highly-reliable wiring layer, and can eliminate an additional step for reducing a step caused by erosion, thereby further increasing the manufacturing yield. Can be.

According to the semiconductor integrated circuit device of the present embodiment, since the semiconductor integrated circuit device is manufactured using the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the wiring layer formed on the insulating film 10 is formed. Since the wiring layer is formed of a damascene wiring layer or the like in which the barrier metal film 12 and the wiring metal layer 13 are buried in the groove 11, the pattern of the wiring layer is formed using lithography technology and selective etching technology. The barrier metal film 12 and the wiring metal layer 13 as the wiring layer can be formed without using the conventional wiring layer pattern manufacturing process, and the wiring layer width and the distance between adjacent wiring layers are extremely small. Even if it has a layer structure, it is a wiring layer that is finely processed and has high dimensional accuracy, and the surface of the wiring layer has the same plane or surface as the surface of the insulating film 10 except the groove 11. Can be the semiconductor integrated circuit device having less 0.05μm from the same plane (very short level) may be a semiconductor integrated circuit device of high performance, yet reliable.

(Embodiment 2) FIGS. 7 to 12 are schematic sectional views showing manufacturing steps of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The feature of the method of manufacturing a semiconductor integrated circuit device according to the present embodiment is, like the method of manufacturing a semiconductor integrated circuit device according to the first embodiment described above, embedded in a groove formed in an insulating film on a substrate. This is a method for manufacturing a wiring layer including a barrier metal film and a metal layer for wiring, and various other methods for manufacturing a semiconductor integrated circuit device can be applied. The semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 7, a p-type semiconductor substrate (substrate) 1 made of, for example, single crystal silicon is prepared.
Various techniques, such as the prior art, are used to form MOSFETs. In this case, the same manufacturing process as that of the semiconductor integrated circuit device according to the first embodiment shown in FIG. 1 is used.

Next, after forming an insulating film 10 as a first-layer interlayer insulating film on the semiconductor substrate 1, a groove 11 for a wiring layer is formed therein (FIG. 8). In this case, the same manufacturing process as that of the above-described semiconductor integrated circuit device of the first embodiment shown in FIG. 2 is used.

Thereafter, a barrier metal film 12 made of tantalum is deposited on the semiconductor substrate 1 by using a sputtering method or a CVD method. In this case, the thickness of the barrier metal film 12 made of tantalum formed on the surface of the insulating film 10 in a region other than the groove 11 is, for example, 100 nm.

Next, after a resist film 14 made of a photoresist film or the like is applied on the semiconductor substrate 1, the patterned resist film 1 is formed by using a lithography technique.
4 (FIG. 9).

In this case, the patterned resist film 1
4 is a step of reducing the thickness of the barrier metal film 12 on the surface of the insulating film 10 in a region other than the groove 11 without reducing the thickness of the barrier metal film 12 at the bottom of the groove 11 (after the following description). ) Is applied as a mask used in the above step). Therefore, the patterned resist film 14
Is set to a width similar to the width of the groove 11 or a width slightly larger than the width of the groove 11 according to the design specifications.

Next, the barrier metal film 12 at the bottom of the groove 11 is formed.
A step of reducing the thickness of the barrier metal film 12 on the surface of the insulating film 10 in a region other than the trench 11 without reducing the thickness of the gate insulating film 10 (FIG. 10). In this case, in the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the resist film 14 is used as a mask and the step of using the selective etching technique of the barrier metal film 12 is performed. The feature of the present embodiment is that the thickness of the barrier metal film 12 on the surface is set to 10 nm or less.

Next, after removing the unnecessary resist film 14, a taper is formed on the overhang-shaped barrier metal film 12 formed (formed) at the corner of the groove 11 according to the design specification. (Apply) process is applied.

Thereafter, a wiring metal layer 13 made of a copper layer having a thickness of, for example, 400 nm or more is deposited on the semiconductor substrate 1 by using a sputtering method, a CVD method, or a plating method. The work of embedding the metal layer 13 for use is performed (FIG. 11). In this case, in order to completely embed the wiring metal layer 13 as a wiring layer in the groove 11, when depositing the wiring metal layer 13, a film thickness (for example, 600 nm) larger than the thickness of the groove 11 (for example, 400 nm). ).

Next, the wiring metal layer 13 is polished from the surface of the wiring metal layer 13 by using the CMP method.
Work of polishing the barrier metal film 12 on the surface of the insulating film 10 other than the region shown in FIG. 2 and removing the wiring metal layer 13 and the wiring metal layer 13 and the barrier metal film 12 other than the barrier metal film 12 buried in the groove 11. (FIG. 12).
In this case, the wiring metal layer 13 embedded in the groove 11
Is the same plane (same plane) as the surface of the insulating film 10, and the barrier metal film 12 made of tantalum on the insulating film 10 is removed. As a result of the study of the present invention, the surface of the wiring metal layer 13 buried in the trench 11 is within 0.05 μm (an extremely short distance level) from the same plane as the surface of the insulating film 10, and The barrier metal film 12 made of tantalum on the top is removed.

Thereafter, in accordance with the design specifications, the above-described insulating film 10 as the first interlayer insulating film, the barrier metal film 12 as the first wiring layer, and the wiring metal layer 13 are formed.
Is applied on the semiconductor substrate 1 by applying a manufacturing method for forming
After depositing the second interlayer insulating film, a groove for forming a second wiring layer is formed in a selective area thereof, and a barrier metal film and a wiring as a second wiring layer are formed in the groove. A metal layer for use. After the above-described manufacturing process is repeatedly used to form a multilayer wiring layer as necessary, a passivation film (not shown) is formed, and the manufacturing process of the semiconductor integrated circuit device of the present embodiment is completed. .

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment described above, the insulation of the region other than the trench 11 can be achieved without reducing the thickness of the barrier metal film 12 at the bottom of the trench 11 for the wiring layer. After performing the step of reducing the thickness of the barrier metal film 12 on the surface of the film 10, the wiring metal layer 13 is polished from the surface of the wiring metal layer 13 using a CMP method,
Next, the barrier metal film 12 on the surface of the insulating film 10 other than the region of the groove 11 is polished, and the wiring metal layer 13 and the wiring metal layer 13 other than the barrier metal film 12 and the barrier metal film embedded in the groove 11 are polished. In the state where the thickness of the barrier metal film 12 on the surface of the insulating film 10 in the region other than the groove 11 is reduced by performing the operation of removing the CM 12, the CM
Using the P method, the wiring metal layer 1 other than the wiring metal layer 13 and the barrier metal film 12 embedded in the trench 11
3 and the barrier metal film 12 are removed.

Therefore, according to the semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, the semiconductor integrated circuit device of the first embodiment is similar to the semiconductor integrated circuit device of the first embodiment and the method of manufacturing the same. The same effects as those of the device and the manufacturing method thereof can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the semiconductor integrated circuit device and the method of manufacturing the same according to the present invention, the barrier metal film 12
In addition to tantalum, titanium (Ti), tungsten (W), molybdenum (Mo) or tantalum nitride (TaN), titanium nitride (TiN), TiW
A high melting point metal film using an alloy such as

In the semiconductor integrated circuit device and the method of manufacturing the same according to the present invention, as the wiring metal film 13, a wiring metal layer such as an aluminum (Al) layer or a gold (Au) layer other than the copper layer is applied. be able to.

Further, in the semiconductor integrated circuit device and the method of manufacturing the same according to the present invention, a substrate such as an SOI (Silicon on Insulator) substrate can be used as the substrate in addition to the semiconductor substrate.

Further, the present invention relates to a MOSFET, a CMOS,
A semiconductor integrated circuit device in which various semiconductor elements such as an FET and a bipolar transistor are combined and a method for manufacturing the same can be provided.

Further, the present invention relates to a MOSFET, a CMO
Logic system or DR with SFET etc. as components
AM (Dynamic Random Access Memory), SRAM (St
The present invention can be applied to various semiconductor integrated circuit devices having a memory system such as an aticRandom Access Memory) and a method of manufacturing the same.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the thickness of the barrier metal film on the surface of the insulating film in a region other than the groove is not reduced without reducing the thickness of the barrier metal film at the bottom of the groove for the wiring layer. After performing the step of thinning, using a CMP method, polishing the wiring metal layer from the surface of the wiring metal layer, and then polishing the barrier metal film on the surface of the insulating film other than the groove region, By removing the wiring metal layer and barrier metal film other than the wiring metal layer and barrier metal film embedded in the trench, the thickness of the barrier metal film on the surface of the insulating film in the region other than the trench is removed. In a state where the thickness is reduced, an operation of removing the wiring metal layer and the barrier metal film other than the wiring metal layer and the barrier metal film embedded in the trench is performed by using the CMP method.

Therefore, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the wiring metal layer and the barrier metal film other than the wiring metal layer and the barrier metal film buried in the trench are formed by using the CMP method. When removing the erosion, it is possible to reduce the erosion of dishing in the trench for the wiring layer and the simultaneous polishing of the insulating film around the wiring layer. In addition, as a result of the study by the present inventors, when removing the barrier metal film other than the barrier metal film embedded in the trench, the thickness is set to 10 nm or less, so that dishing and erosion can be extremely reduced. It has been found that dishing and erosion can be prevented according to the design specifications.

(2). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the thickness of the barrier metal film on the surface of the insulating film in a region other than the groove is not reduced without reducing the thickness of the barrier metal film at the bottom of the groove for the wiring layer. CM as a process to make
The process uses the P method, and the thickness of the barrier metal film on the surface of the insulating film in the region other than the groove is set to 10 nm or less. Simultaneously with this process, the over-layer formed (formed) in the corner of the groove is formed. Since the taper is formed (applied) on the hang-shaped barrier metal film, the shape of the overhang-shaped barrier metal film formed at the corner of the wiring layer groove can be improved. Therefore, the buried shape of the wiring metal layer can be improved, and a high-performance and highly reliable wiring layer can be formed.

(3). ADVANTAGE OF THE INVENTION According to the manufacturing method of the semiconductor integrated circuit device of this invention, the dishing in the groove | channel for wiring layers and the erosion which simultaneously grinds the insulating film around a wiring layer can be reduced, and the corner part of a groove | channel can be reduced. Formation (film formation)
The taper is formed (applied) on the overhang-shaped barrier metal film, so that the embedded shape of the wiring metal layer can be improved.
A high-performance and highly reliable wiring layer can be formed, an additional step for reducing a step caused by erosion can be omitted, and the manufacturing yield can be further increased.

(4). According to the semiconductor integrated circuit device of the present invention, since the semiconductor integrated circuit device is manufactured using the manufacturing method of the semiconductor integrated circuit device of the present invention, the barrier metal film and the wiring are formed in the wiring layer groove formed in the insulating film. And a conventional wiring layer pattern forming process using a lithography technique and a selective etching technique to form a wiring layer pattern. Without using, it is possible to form a barrier metal film and a wiring metal layer as a wiring layer,
Even if the wiring layer width and the distance between adjacent wiring layers are extremely small, the wiring layer is finely processed and has high dimensional accuracy, and the surface of the wiring layer is the surface of the insulating film other than the groove. From the same plane or 0.05 from the same plane
Since a semiconductor integrated circuit device having a size of μm or less (an extremely short distance level) can be obtained, a semiconductor integrated circuit device having high performance and high reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a schematic sectional view showing a manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 9 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 10 is a schematic sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate (substrate) 2 Field insulating film 3 Gate insulating film 4 Gate electrode 5 Insulating film 6 Sidewall spacer 7 Semiconductor region 8 Insulating film 9 Plug 10 Insulating film 11 Groove 12 Barrier metal film 13 Wiring metal layer 14 Resist film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Eiji Sasaki 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Shinichi Fukada Tokyo 6-16-16 Shinmachi, Ome-shi F-term in Hitachi, Ltd. Device Development Center 5F033 JJ11 JJ21 MM01 MM05 MM13 NN12 PP06 PP15 QQ37 QQ48

Claims (9)

[Claims] A groove is formed in an insulating film on a substrate,
A wiring layer composed of a barrier metal film and a wiring metal layer embedded in the groove is formed, and the surface of the wiring layer is formed on the same plane or the same plane as the surface of the insulating film other than the groove. A semiconductor integrated circuit device having a size within .05 μm. 2. The semiconductor integrated circuit device according to claim 1, wherein said wiring layer is a damascene wiring layer, said barrier metal film is a tantalum film, and said wiring metal layer is a copper layer. A semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein said wiring layer is a damascene wiring layer, and said barrier metal film is tantalum, titanium, tungsten, molybdenum or tantalum nitride, titanium nitride. And a high melting point metal film using an alloy such as an alloy. 4. A step of forming a groove in an insulating film on a substrate; a step of forming a barrier metal film on side and bottom portions of the groove and a surface of the insulating film; Reducing the thickness of the barrier metal film on the surface of the insulating film in a region; and depositing a wiring metal layer on the substrate, and then using CMP to form the barrier metal film on the insulating film. Forming a wiring layer composed of the barrier metal film and the wiring metal layer embedded in the trench by removing a metal film and the wiring metal layer, and manufacturing the semiconductor integrated circuit device. Method. 5. A step of forming a groove in an insulating film on a substrate; a step of forming a barrier metal film on side and bottom portions of the groove and a surface of the insulating film; As a step simultaneously with or after the step of reducing the thickness of the barrier metal film on the surface of the insulating film in the region, the shape of the overhang-shaped barrier metal film formed at the corner of the groove Forming a taper on the substrate, depositing a wiring metal layer on the substrate, and removing the barrier metal film and the wiring metal layer on the insulating film using a CMP method; Forming a wiring layer made of the barrier metal film and the wiring metal layer embedded in the trench. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the thickness of the barrier metal film on the surface of the insulating film in a region other than the groove or the vicinity of the groove is reduced. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a thickness of the barrier metal film on a surface of the insulating film in a region other than the groove or the vicinity of the groove is 10 nm or less. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein a thickness of said barrier metal film on a surface of said insulating film in a region other than said groove is reduced. The method of manufacturing a semiconductor integrated circuit device, wherein the step of performing is a step using a CMP method. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said barrier metal film is formed on a surface of said insulating film in a region other than said groove or a region near said groove. The step of reducing the thickness, after applying a resist film on the groove or on the insulating film near the groove and the groove, using the resist film as a mask,
A step of etching the barrier metal film on the surface of the insulating film in the groove or in a region other than the vicinity of the groove. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said wiring layer comprises:
A method for manufacturing a semiconductor integrated circuit device, wherein a damascene wiring layer is used, the barrier metal film is a tantalum film, and the wiring metal layer is a copper layer.