JP2000173061A - Optical disk signal-reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and optimally set an optimum amount of delay by equipping a rough delay means for roughly adjusting the delay of a specific reproduction signal and an accurate delay means for finely adjusting the delay of the specific reproduction signal with accuracy that is equal to or less than the minimum delay resolution of the rough delay means. SOLUTION: A variable delay element 12b that is an accurate delay means in a digital control system for rough adjustment delays a signal S2 that is generated by a laser beam L2 by τ2 as a signal S2a. An A/D converter 14b converts a signal S2a to a digital signal and transmits it to registers 25a-25d in a shift register 25 that is a rough delay means in an analog control system for fine successive adjustment in synchronization with a clock CLK. The registers 25a-25d output a digital delay signal that is obtained by delaying the signal S2a by a delay nT at a clock cycle of T. By selecting an optimum signal from the digital delay signals by a tap switching means 27, a required amount of delay τ2+nT can be accurately obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk signal reproducing apparatus for irradiating a plurality of laser beams to an optical disk medium on which high-density recording is performed, and reproducing information while removing adjacent track crosstalk from respective light receiving signals. is there.

[0002]

2. Description of the Related Art In recent years, as the density of optical disk media has increased, more sophisticated technology has been required for optical disk signal reproducing devices.

An example of the above-described conventional optical disk signal reproducing apparatus will be described with reference to the drawings. FIG.
1 shows a block diagram of a conventional optical disk signal reproducing apparatus. 7, the tracks T1, T2, and T3 formed on the optical disc medium 100 are irradiated with laser beams L1, L2, and L3, respectively, and the reflected light is projected on the light receiving elements 111, 121, and 131, respectively, and the electric signal S1 is received. , S2, S3. Assuming that the track from which an information reproduction signal is actually to be obtained is T2, the laser beams L1 and L3 (sub-beams)
This is for canceling crosstalk components leaking from adjacent tracks T1 and T3 when the laser beam L2 (main beam) scans the track T2. That is, when obtaining the information reproduction signal SX, the coefficient units 113 and 13
SX = S2-k * (S1 + S3) is calculated by 3 and the addition / subtraction amplifier 130, and the crosstalk component is electrically canceled.

However, for the following reasons, the three laser beams applied to the optical disk medium must be spaced apart in the tangential direction of the track to some extent. Can not. That is, ideally, the laser beams L1, L2, and L3 should be irradiated adjacent to each other in the track perpendicular (radial) direction. In this case, however, the laser beams overlap each other because the track pitch is narrow. I will wrap. Inevitably, the beams projected on the light receiving element also overlap each other, and each beam is independently transmitted to the light receiving element 11.
1, 112 and 113 cannot receive it. Therefore, it is necessary to arrange each beam at a certain distance in the tangential direction. However, at this time, the light receiving element 1
The output signals 11, 121 and 131 have a time difference corresponding to the tangential separation distance. Therefore, the time difference generated here is corrected by the first and second variable delay elements 112 and 122.

However, it is difficult to strictly control the distance between the laser beams L1, L2, and L3. If possible, the time difference fluctuates depending on the rotational linear velocity of the optical disk medium. And the amount of delay to be generated must always be set to an optimal state. The multiplier 141 calculates the correlation between the output signal of the light receiving element 131 and the output signal of the second variable delay element 122, and the multiplier 142 calculates the correlation between the output signal of the second variable delay element 122 and the output of the first variable delay element 112. The correlation with the signal,
The maximizing control means 136 detects the delay element 1 so that each of them is maximized.
The delay adjustment of each of the steps 12 and 122 is performed (for example, Japanese Patent Application Laid-Open No. H7-176052).

[0006]

However, in the above configuration, it is difficult to realize the delay elements 112 and 122 satisfying both the delay amount and the delay accuracy, and the multipliers 141 and 142 detect the correlation signal. There is a problem that the delay amount cannot be adjusted to the optimum value due to low sensitivity.

[0007] These problems will be described below. First, the laser beams L1, L on the optical disk medium
2 or the distance between the laser beams L2 and L3 in the track tangential direction is the light receiving element 11.
10 μ in consideration of the shape and arrangement of 1, 121 and 131
About m is necessary. On the other hand, the recording linear density of information recorded on an optical disk medium is, for example, 0.1 μm per channel bit in a DVD (digital video disk) recorded by PWM using an 8-16 conversion code.
m. Therefore, even though the interval is 10 μm,
This is equivalent to a difference of 100 bits.

As a specific means for delaying, a configuration in which a plurality of analog delay elements are connected in series in a ladder shape is conceivable, but the analog delay elements themselves have group delay characteristics. The delay amount at which the delay does not matter is at most about 10 bits, and it is almost impossible to realize a delay of 100 bits.

As a method of obtaining the delay amount, for example, a sample-and-hold type filter such as a switched capacitor filter or a digital filter can be considered. If these are used, the group delay can be maintained regardless of the delay amount. However, in a sample-and-hold type filter, the delay accuracy is determined by the sampling clock. Therefore, in order to increase the accuracy, the sampling clock frequency must be increased, and the number of sample-and-hold elements and the operation speed must be increased accordingly. When a channel clock is used as the sampling clock, one clock is equivalent to a one-bit delay, so that 100-bit delay requires 100 sample-and-hold elements. 2
Must operate at 7 MHz.

However, when a channel clock is used,
The delay amount can be changed only in 1-bit increments, which causes a problem in delay accuracy. According to our experiments, in order to ideally perform crosstalk cancellation, it is necessary to adjust the delay with at least 1/4 bit precision. If this is to be realized by sample and hold, the sampling frequency will be four times (108 MHz) the channel clock, and the required sample and hold element will be four times (4
00 elements).

SUMMARY OF THE INVENTION In view of the above problems, the present invention adjusts the necessary delay by adjusting a coarse delay means of a digital control system constituted by a shift register and a fine delay of an analog control system constituted by a group delay filter and the like. It is an object of the present invention to provide an optical disc signal reproducing apparatus which can realize an optimum delay amount with high accuracy by realizing the same in combination with the means, and further executing a search for the optimum delay amount using the jitter detecting means.

[0012]

In order to achieve the above object, an optical disk reproducing apparatus of the present invention reads a recording signal by irradiating a plurality of beams on a plurality of adjacent tracks formed on an optical disk medium, Rough adjustment of a predetermined reproduction signal in an optical disk signal reproduction apparatus that generates a plurality of reproduction signals corresponding to each track and cancels crosstalk included in the read signal by the plurality of reproduction signals to generate an information reproduction signal A coarse delay means for delaying the delay signal; and a fine delay means for finely delaying the predetermined reproduction signal with an accuracy equal to or less than the minimum delay resolution of the coarse delay means.

[0013] The optical disk reproducing apparatus may further comprise means for detecting jitter of the information reproduction signal and controlling delay amounts of the fine delay means and the coarse delay means so as to minimize the jitter. .

The coarse delay means is constituted by a group of sample-and-hold elements connected in series, which operate according to a synchronous clock. The optical disc reproducing apparatus is characterized in that the optical disc reproducing apparatus has a means for setting the delay amount of the coarse delay means in a stepwise manner by selecting an output of an arbitrary sample and hold element of the sample and hold element group.

The coarse delay means is constituted by a shift register constituted by the sample and hold element group, and the fine delay means is constituted by a filter for generating an arbitrary group delay. I do.

The fine delay means can continuously vary the delay amount, the coarse delay means can set the delay amount in integral multiples of the clock cycle, and the maximum delay amount of the fine delay means is equivalent to the clock cycle. It is characterized by being within the delay amount.

Also, the optical disk reproducing apparatus of the present invention reads a recording signal by irradiating a plurality of beams on a plurality of tracks adjacent to each other formed on an optical disk medium, and generates a plurality of reproduction signals corresponding to each track. An optical disc signal reproducing apparatus for generating an information reproduction signal by canceling crosstalk included in a read signal from the plurality of reproduction signals, a delay means for delaying a predetermined reproduction signal, and detecting a jitter of the information reproduction signal Means, and means for controlling the amount of delay of the delay means so that the jitter is minimized.

With the above arrangement, the coarse delay means for executing the delay means in synchronization with the clock and the fine delay means for continuously generating a delay within one clock are provided, so that the distance between the main beam and the sub beam in the track tangential direction can be reduced. The corresponding time difference can be accurately corrected. Further, by executing the search for the optimum delay amount using the jitter, it is possible to set the optimum delay amount with high accuracy.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an optical disc reproducing apparatus according to a first embodiment of the present invention will be described with reference to the drawings. In the first embodiment, both the delay amount and the delay accuracy are achieved by using both the coarse delay unit and the fine delay unit.
Further, by searching for the optimum delay amount so that the jitter is minimized, the optimum delay amount can be set with high accuracy. Here, it is assumed that the fine delay means is configured to finely delay a predetermined reproduction signal with a finer precision than the minimum delay resolution of the coarse delay means.

FIG. 1 is a block diagram showing an optical disk reproducing apparatus according to the first embodiment of the present invention. In FIG. 1, 11a, 11b and 11c are the first,
Second and third light receiving elements, three adjacent tracks T1, T2, T3 formed on the optical disc medium 1;
The reflected light of the laser beams L1, L2, L3 applied to the laser beam is converted into an electric signal, and reproduced signals S1, S2, S
3 is output. Here, the laser beam L2 is a so-called main beam, which irradiates a track on which information is to be reproduced, and the laser beams L1, L3 are sub-beams, which are used for removing crosstalk of the main beam. . Although a specific method of generating the laser beams L1, L2, and L3 is not particularly illustrated, for example, the laser beams may be generated from three laser beam emission sources, or one laser beam may be formed using a diffraction grating. May be obtained by diffracting in three directions.

Reference numerals 12a and 12b denote first and second fine-adjustment delay elements, respectively, which arbitrarily and continuously generate a delay of one channel clock cycle (corresponding to one bit) or less. Of the analog control type precision delay means. Reference numerals 13a and 13c denote first and second coefficient units having a gain adjusting function, which are multiplied by a weighting coefficient k for obtaining an optimum crosstalk canceling effect.

14a, 14b and 14c are the first,
The second and third AD converters are used for reproducing signals S1a and S2.
a and S3a are converted into digital signals. Reference numeral 15 denotes a first shift register, which includes registers 15a to 15h that operate in synchronization with the clock CLK. Similarly, 25
Denotes a second shift register, and registers 25a to 25
d. Here, the AD converter 14a or 14
Since the output of b is a parallel (for example, 8 bits) output, each register must have a parallel configuration. However, for simplicity, the register is shown in a single-bit configuration. Reference numerals 26 and 27 denote first and second tap switching means, respectively, which are the first and second shift registers 15,
25 arbitrary register outputs are selected to adjust the delay amount in bit units. The AD converters 14a, 14b, 14
c, shift registers 15, 25, and tap switching means 2
The coarse delay means 6 and 27 constitute the coarse delay means of the digital control method for coarse adjustment in the present embodiment. As described above, the coarse delay means is configured by a series-connected sample and hold element group that operates according to the synchronous clock (CLK).

Numeral 30 denotes an adding / subtracting means constituted by an operational amplifier or the like for executing crosstalk addition / subtraction, and 31 denotes a DA.
It is a converter, which converts the output signal of the addition / subtraction means 30 from digital to analog to generate an information reproduction signal SX. A comparator 32 binarizes the information reproduction signal SX to generate an information reproduction pulse signal PX. 33 is a PLL (phase lock loo)
p) A circuit which generates and extracts a clock CLK by inputting the reproduction pulse signal PX, and sends the clock CLK together with the clock CLK to the subsequent stage (for example, a digital video decoder) as a reproduction information signal (DATA) by the latch circuit 34. 3
Reference numeral 5 denotes a jitter detector, which measures a jitter between the information reproduction pulse signal PX and the clock CLK and outputs a signal corresponding to the amount of the jitter (the jitter will be described later). The minimization controller 36 controls the continuously variable delay amounts τ1, τ2 of the fine adjustment delay elements 12a, 12b so that the jitter amount is minimized.
Analog control and adjustment, and tap switching means 2
Search and set the optimum register output selected for digital control adjustment by 6, 27.

The operation of the optical disk reproducing apparatus configured as described above will be described below with reference to FIGS. 1, 2 and 3.

FIG. 2 is a timing chart illustrating the sharing of the delay amount adjustment function between the second delay element 12b for fine adjustment and the second shift register 25 for coarse adjustment corresponding to the main beam L2. First, the signal S2 generated by the laser beam L2 is delayed by .tau.2 by the second delay element 12b to become a signal S2a. Signal S2a
Is sampled by the second AD converter 14b in synchronization with the clock CLK, and is converted into a digital signal. This digital signal is sequentially transmitted to the registers 25a to 25d in the shift register 25 in synchronization with the clock CLK.
Therefore, digital delay signals obtained by delaying the signal S2a by the clock cycle (T) are obtained at the outputs of the registers 25a to 25d. Assuming that a signal obtained by selecting one of the optimum registers by the tap switching means 27 is S2b,
The signal S2b is delayed from the signal S2a by an integer multiple of the clock period (T), that is, nT (4T in the example of FIG. 2). Therefore, the amount of delay from the initial signal S2 is τ2 + nTn: integer.

Therefore, it is necessary to use the delay element 12b for fine adjustment in which the delay amount can be continuously varied and the shift register for coarse adjustment in which the delay amount can be set in integral multiples of the clock cycle. The delay amount can be obtained with high accuracy. At this time, the maximum delay amount of the delay element 12b is sufficient for the above-described clock cycle (T), that is, a delay amount corresponding to 1 bit in the case of a channel clock. Therefore, as a specific configuration of the delay element 12b, an expression obtained by dividing the Laplace transform of the output signal by the Laplace transform of the corresponding input signal is represented by the following equation: G = (1−jω / ω2) / (1 + jω / ω2) An analog group delay filter or the like having a transfer function such as Here, the relationship between ω2 and τ2 may be, for example, ω2 = 2π / τ2.

The first delay means 12a and the first shift register 15 corresponding to the first sub-laser beam L1 are also
Second delay element 12b and second shift register 25
What is necessary is just to have the function equivalent to. However, the first sub-laser beam L1 needs to be approximately twice as far from the second sub-laser beam L3 as compared to the main laser beam L2, so that the number of constituent registers (15a to 15h) in the first shift register 15 is large. Is required about twice the register of the second shift register 25.

The output of the third AD converter 14c and the first
Tap changer 26 via shift register 15 of FIG.
Is input to the operational amplifier 30 by subtraction, while the second tap changer 2 via the second shift register 25
The output signal of No. 7 is added and input to the operational amplifier 30, and the following crosstalk addition / subtraction is executed to obtain the information reproduction signal SX. That is, SX (t) = S2 (t− (τ2 + nT)) − k × ｛S1
(T− (τ1 + mT)) + S3 (t))｝ m, n: integer t: time Here, mT and nT are delay amounts determined by the first and second shift registers 15 and 25, respectively, and these values switch the tap switching means 26 and 27 based on the determination of the minimization control means 36. It is set by the following. Hereinafter, a determination method of the minimization control unit 36 will be described.

First, the information reproducing pulse signal PX obtained by the comparator 32 and the channel clock generated by the PLL, that is, the clock CLK, are supplied to the jitter detecting means 35.
And jitter is detected. Jitter is an uncorrelated error between data and clock, and is a parameter that indicates the reproduction state of a signal, which increases or decreases according to the degree of noise, intersymbol interference, or crosstalk between tracks. If this is large and exceeds the data window margin, an error occurs. Conversely, minimizing the jitter suppresses crosstalk between tracks. As a specific method of detecting the jitter, for example, a root mean square value or an average value of absolute values of phase errors between data clocks may be obtained.

As shown in FIG. 3, the minimizing control means 36 controls the tap switching means 26 to minimize the jitter.
27 (digital coarse adjustment) and delay element 12
The delay amounts τ1 and τ2 of a and 12b are respectively adjusted (analog fine adjustment). That is, if the time difference caused by the distance between the laser beams L1 and L3 or the distance between the laser beams L2 and L3 in the track tangential direction can be completely corrected, the crosstalk between tracks can be removed to the maximum, and as a result, the jitter is minimized. Therefore, in FIG. 3, the delay amount is set to D0 within one cycle to minimize the jitter.
, This delay amount becomes the optimal set value. Specifically, for example, the first and second shift registers 15,
While sequentially switching the 25 output taps, a tap search is first performed so as to select a register where the jitter is minimized (coarse adjustment), and the continuously variable delay amounts τ1 and τ2 of the delay elements 12a and 12b are finely adjusted to minimize the jitter. Delay amount D0
What should I do?

Here, in FIG. 1, the second tap switching means 27 is displayed as if it selects only the outputs of the registers 25c and 25d. However, for the purpose of the present invention,
It is assumed that all register outputs corresponding to the required variable width are switched. In FIG. 1, the second shift register 25
Is shown as consisting of four registers,
Since the number of the registers needs to be the number of bits corresponding to the interval between the laser beams L2 and L3, if the distance between the two is 100 bits as described above, of course, about 100 registers are required. The same applies to the first shift register 15 and the first tap switching means 26.

In this embodiment, the reason why jitter is used as an index for searching for the optimum value of the delay
This is because a high detection sensitivity and high reliability can be obtained when a signal modulated by an LL (Run Length Limited) code is reproduced. Here, the RLL code is, for example, EFM (8-14 modulation) on CD or 8 on DVD.
Like the -16 modulation, the shortest mark length and the longest mark length are limited to increase the recording density. In both cases, the shortest mark length is three times the channel clock cycle. When the RLL code is used, information is intensively stored at the edge of each code, so that the recording density is increased,
The recorded information easily causes an edge shift due to noise or crosstalk, and thus an error easily occurs. If the edge shift occurs, the reproduced signal jitter naturally increases. In other words, by observing the jitter,
It is possible to know the degree of crosstalk with high sensitivity.

As another method for detecting the degree of crosstalk other than the method based on the jitter observation, there is a method for calculating a correlation signal. This method uses an RLL code.
On the contrary, the detection sensitivity tends to decrease. In other words, since the correlation signal performs not only the edge but also the peak and bottom parts that are not easily affected by crosstalk,
As the code with the longest mark length is reproduced, the detection sensitivity decreases in accordance with the shortest mark length.

On the other hand, the present inventors have paid attention to the fact that the error of delay adjustment can be detected with high accuracy by using jitter detection, and adopted a method of detecting the degree of crosstalk by observing jitter. Things. By the way, the delay allowable error (so-called margin) at which the jitter increases by 0.5% in the clock window ratio from the delay amount at which the jitter becomes minimum is about 1/4 of the clock cycle. That is, in order to perform ideal crosstalk cancellation, it is necessary to adjust the delay to 1/4 bit precision. Hereinafter, this will be briefly described.

FIG. 4 illustrates the relationship between the error in the amount of delay and the jitter of the reproduced signal due to the error. In the figure, the horizontal axis represents a delay amount error. When the error is 0, that is, when the crosstalk cancellation is performed in a state where there is no error, the reproduction signal jitter is about 5%. When a delay error corresponding to one bit (one cycle) occurs, the jitter deteriorates by about 2.5%.
It is about 5%. Normally, an increase of about 0.1% of the jitter can be detected, and it can be seen that the alignment error can be sufficiently detected with a precision of 1/4 bit of the clock cycle. However, this does not only mean that the detection sensitivity of the optimum delay amount becomes higher when jitter is used, but also means that the delay amount must be actually adjusted with this accuracy. . This is because jitter is a parameter directly related to the reproduction error rate.

The reproduction signal jitter of about 5% is an amount that does not cause any problem in reproducing information, but when a delay error corresponding to one bit occurs, the jitter is 7.5 as described above.
%. Usually, this 7.5% jitter is not a problem in reproducing information. However, if jitter due to contamination of a disk or a head or jitter due to noise is added, an error may occur in reproduced information. is there. Therefore, in order to limit the deterioration of the jitter to a level having no practical problem, a delay error corresponding to one bit is insufficient, and it is necessary to adjust at least about 1/2 bit. When a delay error corresponding to ビ ッ ト bit occurs, the jitter is reduced by about 1% to about 6% as shown in FIG. 4, but this value is considered to be practically acceptable. Therefore, ideally, if the adjustment of about 1/4 bit can be performed, the increase in the jitter will be within a negligible range.

As described above, according to the present embodiment, the shift register for coarse adjustment that varies the delay amount by the digital control method at every clock cycle, and the analog shift register that continuously varies the delay amount within one clock cycle. By using the delay element for fine adjustment together, the delay amount of about 100 bits generated according to the distance between the laser beams in the tangential direction of the track can be accurately corrected. By using (35), it is possible to search for the optimum correction amount with high sensitivity.

In this embodiment, the delay element 1
Although 2a and 12b correct one clock cycle, this does not mean that the maximum variable amount is strictly limited to within one clock cycle. In order to increase the maximum variable amount, for example, four periods may be provided.

Further, in the present embodiment, the coarse delay means is configured to AD-convert the reproduction signals S1, S2, and S3, respectively, and to generate a delay in the shift register. However, the reproduction signals are sequentially synchronized in synchronization with the clock. If multiple sample-and-hold elements that can be sampled are connected in series,
For example, an analog element such as a switched capacitor filter may be used.

In the present embodiment, the coefficient unit 13,
33, the weighting coefficient k is assumed to be fixed.
For example, the optimum value may be automatically searched so as to minimize the jitter.

Further, in this embodiment, after the digital processing of the crosstalk addition / subtraction processing, the DA conversion (3
1) Although the clock is supplied to the PLL circuit, the clock may be directly extracted using a digital PLL without DA conversion.

Next, a second embodiment of the present invention will be described. FIG. 5 shows a block diagram of the second embodiment, in which a fine delay can be adjusted without using a delay element. In FIG. 5, the light receiving elements 11a, 11b, 1
1c, coefficient units 13a and 13c, AD converters 14a and 14
b, 14c, the first shift register 15 (register 15
a to 15h), the second shift register 25 (register 2
5a to 25d), tap switching means 26 and 27, addition / subtraction means 30, DA converter 31, comparator 32, PLL circuit 33, and jitter detection means 35 have the same functions as those shown in FIG.

FIG. 5 is different from FIG.
Performs fine delay adjustment of 1 channel clock cycle T or less
The first and second latch registers without using a delay element
Star 41, 42 and first and second interpolation calculating means 43,
Approximate delay is generated by the interpolation means composed of 44
It is making it. This function is described with reference to FIG.
I will explain it. First, the second AD converter 14b sumps
Channel shift in the second shift register 25.
Sampling data (V _n) Is
It is composed of a latch register 41 and a first interpolation calculating means 43.
To the delay means to be implemented. Where nT
The data directly supplied to the interpolation calculating means 43 by V_n
And Latch register 41 is one channel clock
(T) holds sampling data during
Data supplied from the first register 41 to the interpolation calculating means 43.
The timer is one channel clock before, that is, the (n-1) T
Data V_n-1Becomes Where the minimization system
The delay amount set by the control means 46 is aT (0 ≦ a
Suppose <1). The interpolation operation means 43 calculates V ′ = a × V_n-1 + (1-a) × V_n Is calculated, and the interpolated value V 'is
V_n Instead, it is output and input to the addition / subtraction means 30.

The above operation is performed on all data series, and as a result, as shown in FIG.
Data delayed by T is obtained. First AD converter 1
4, a shift register 15, a latch register 42, and an interpolation operation means 44 perform the same processing, and a delay processing of approximately bT (0 ≦ b <1) is executed. As described in the first embodiment, the optimization of the delay amounts a and b can be performed with high accuracy by searching so as to minimize the jitter. In the above embodiment, the fine delay means executes interpolation processing using an arbitrary coefficient (a, b) from a discrete signal sequence sampled and held by the sample and hold element group (4).
1, 42, 43, 44).

As described above, according to the present embodiment, fine delay adjustment can be approximately performed by executing delay processing using interpolation processing of sampling data. As a result, the delay elements 12 and 22 become unnecessary, and lower cost can be realized.

In this embodiment, the interpolation means 43 and 44 execute the linear interpolation processing.
The approximation accuracy is further improved by using higher-order curve interpolation.
That is, in the linear interpolation, as shown in FIG.
There arises a problem that an error in a portion where the curvature of the signal is large (near a local maximum / minimum point) becomes large. If a higher-order curve interpolation such as a quadratic curve interpolation is used, the curve portion can be well approximated, and the error is reduced.

[0047]

As described above, the present invention provides a coarse delay means for executing a delay means in synchronization with a clock and a fine delay means for continuously generating a delay within one clock.
The time difference according to the distance between the main beam and the sub beam in the track tangential direction can be accurately corrected. Further, by executing the search for the optimum delay amount using the jitter, it is possible to set the optimum delay amount with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of an optical disk signal reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation in the embodiment.

FIG. 3 is a characteristic diagram for describing an operation in the embodiment.

FIG. 4 is a graph showing a relationship between a delay amount error and a reproduced signal jitter in the embodiment.

FIG. 5 is a block diagram of an optical disk signal reproducing device according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining an operation in the embodiment.

FIG. 7 is a block diagram of a conventional optical disc reproducing apparatus.

[Explanation of symbols]

 11a, 11b, 11c Light receiving element 12a, 12b Variable delay element 13a, 13c Coefficient unit 14a, 14b, 14c A / D converter 15, 25 Shift register 30 Addition / subtraction unit 31 D / A converter 35 Jitter detector 36, 46 Minimization controller 41 , 42 Latch register 43, 44 Interpolating means

Claims (10)

[Claims] 1. A recording signal is read by irradiating a plurality of beams on a plurality of tracks adjacent to each other formed on an optical disk medium, and a plurality of reproduction signals corresponding to each track are generated. An optical disc signal reproducing apparatus for generating an information reproduction signal by canceling crosstalk included in a read signal, comprising: a coarse delay means for coarsely adjusting a predetermined reproduction signal; and a minimum delay of the coarse reproduction means for the predetermined reproduction signal. An optical disc signal reproducing apparatus, comprising: fine delay means for finely delaying with finer precision than resolution. 2. The apparatus according to claim 1, further comprising means for detecting jitter of said information reproduction signal and controlling delay amounts of said fine delay means and coarse delay means so as to minimize said jitter. Optical disk signal reproducing device. 3. An optical disk signal reproducing apparatus according to claim 1, wherein said coarse delay means comprises a series-connected sample-hold element group which operates in accordance with a synchronous clock. 4. The apparatus according to claim 3, further comprising means for setting a delay amount of said coarse delay means in a stepwise manner by selecting an output of an arbitrary sample and hold element of said sample and hold element group. Optical disk signal reproduction device. 5. An optical disk signal reproducing apparatus according to claim 3, wherein said coarse delay means is constituted by a shift register constituted by said sample and hold element group. 6. An optical disk signal reproducing apparatus according to claim 1, wherein said fine delay means comprises a filter for generating an arbitrary group delay. 7. The fine delay means includes an arbitrary coefficient a, b of 0 or more and less than 1 according to a discrete signal sequence sampled and held by the sample and hold element group, where 0 ≦ a <
4. The optical disk signal reproducing apparatus according to claim 3, wherein said optical disk signal reproducing apparatus is configured to execute an interpolation process using 1, 0≤b <1. 8. The fine delay means can continuously vary a delay amount, the coarse delay means can set a delay amount in integral multiples of the clock cycle, and the maximum delay amount of the fine delay means is the clock cycle. 4. The optical disk signal reproducing apparatus according to claim 3, wherein the delay is within a considerable delay amount. 9. A recording signal is read by irradiating a plurality of beams on a plurality of tracks adjacent to each other formed on an optical disk medium, a plurality of reproduction signals corresponding to each track are generated, and reading is performed from the plurality of reproduction signals. In an optical disc signal reproducing apparatus for generating an information reproduction signal by canceling crosstalk included in a signal, a delay means for delaying a predetermined reproduction signal, a means for detecting jitter of the information reproduction signal, Means for controlling the amount of delay of said delay means. 10. The delay means comprises: a coarse delay means for coarsely delaying the predetermined reproduction signal; and a fine delay means for finely delaying the predetermined reproduction signal with an accuracy equal to or less than a minimum delay resolution of the coarse delay means. 10. The optical disk signal reproducing apparatus according to claim 9, comprising: